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-rw-r--r--tcl/board/spear310evb20.cfg48
-rw-r--r--tcl/board/spear310evb20_mod.cfg25
2 files changed, 73 insertions, 0 deletions
diff --git a/tcl/board/spear310evb20.cfg b/tcl/board/spear310evb20.cfg
new file mode 100644
index 00000000..887e7993
--- /dev/null
+++ b/tcl/board/spear310evb20.cfg
@@ -0,0 +1,48 @@
+# Configuration for the ST SPEAr310 Evaluation board
+# EVALSPEAr310 Rev. 2.0
+# http://www.st.com/spear
+#
+# Date: 2010-08-17
+# Author: Antonio Borneo <borneo.antonio@gmail.com>
+
+# The standard board has JTAG SRST not connected.
+# This script targets such boards using quirky code to bypass the issue.
+#
+# Check ST Application Note (FIXME: put reference) on how to fix SRST on
+# the board, then use the script board/spear310evb20_mod.cfg
+
+
+source [find mem_helper.tcl]
+source [find target/spear3xx.cfg]
+source [find chip/st/spear/spear310.tcl]
+source [find chip/st/spear/spear3xx_ddr.tcl]
+source [find chip/st/spear/spear3xx.tcl]
+
+arm7_9 dcc_downloads enable
+arm7_9 fast_memory_access enable
+
+# CFI parallel NOR on EMI CS0. 2x 16bit 8M devices = 16Mbyte.
+set _FLASHNAME0 $_CHIPNAME.pnor
+flash bank $_FLASHNAME0 cfi 0x50000000 0x01000000 2 4 $_TARGETNAME
+
+if { [info exists BOARD_HAS_SRST] } {
+ # Modified board has SRST on JTAG connector
+ reset_config trst_and_srst separate srst_gates_jtag \
+ trst_push_pull srst_open_drain
+} else {
+ # Standard board has no SRST on JTAG connector
+ reset_config trst_only separate srst_gates_jtag trst_push_pull
+ source [find chip/st/spear/quirk_no_srst.tcl]
+}
+
+$_TARGETNAME configure -event reset-init { spear310evb20_init }
+
+proc spear310evb20_init {} {
+ reg pc 0xffff0020 # loop forever
+
+ sp3xx_clock_default
+ sp3xx_common_init
+ sp3xx_ddr_init "mt47h64m16_3_333_cl5_async"
+ sp310_init
+ sp310_emi_init
+}
diff --git a/tcl/board/spear310evb20_mod.cfg b/tcl/board/spear310evb20_mod.cfg
new file mode 100644
index 00000000..bf62915d
--- /dev/null
+++ b/tcl/board/spear310evb20_mod.cfg
@@ -0,0 +1,25 @@
+# Configuration for the ST SPEAr310 Evaluation board
+# EVALSPEAr310 Rev. 2.0, modified to enable SRST on JTAG connector
+# http://www.st.com/spear
+#
+# List of board modifications to enable SRST, as per ST Application Note
+# (FIXME: put reference to AN)
+# - Modifications on the top layer:
+# 1. remove R137 and C57, located near the SMII PHY U18;
+# 2. remove R172 and C75, located near the SMII PHY U19;
+# 3. remove R207 and C90, located near the SMII PHY U20;
+# 4. remove C236, located near the SMII PHY U21;
+# 5. remove U12, located near the JTAG connector;
+# 6. solder together pins 7, 8 and 9 of U12;
+# 7. solder together pins 11, 12, 13, 14, 15, 16, 17 and 18 of U12.
+# - Modifications on the bottom layer:
+# 8. replace reset chip U11 with a STM6315SDW13F;
+# 9. add 0 ohm resistor R329. It is located close to JTAG connector.
+#
+# Date: 2009-10-31
+# Author: Antonio Borneo <borneo.antonio@gmail.com>
+
+
+# Modified boards has SRST on JTAG connector
+set BOARD_HAS_SRST 1
+source [find board/spear310evb20.cfg]