summaryrefslogtreecommitdiff
path: root/tcl/board
diff options
context:
space:
mode:
Diffstat (limited to 'tcl/board')
-rw-r--r--tcl/board/csb732.cfg6
-rw-r--r--tcl/board/dm355evm.cfg2
-rw-r--r--tcl/board/openrd.cfg2
-rw-r--r--tcl/board/sheevaplug.cfg2
4 files changed, 6 insertions, 6 deletions
diff --git a/tcl/board/csb732.cfg b/tcl/board/csb732.cfg
index 9022fafc..cad38e2e 100644
--- a/tcl/board/csb732.cfg
+++ b/tcl/board/csb732.cfg
@@ -19,13 +19,13 @@ proc csb732_init { } {
# We assume the interpreter latency is enough.
# Allow access to all coprocessors
- mcr 15 0 15 1 0 0x2001
+ arm mcr 15 0 15 1 0 0x2001
# Disable MMU, caches, write buffer
- mcr 15 0 1 0 0 0x78
+ arm mcr 15 0 1 0 0 0x78
# Grant manager access to all domains
- mcr 15 0 3 0 0 0xFFFFFFFF
+ arm mcr 15 0 3 0 0 0xFFFFFFFF
# Set ARM clock to 532 MHz, AHB to 133 MHz
mww 0x53F80004 0x1000
diff --git a/tcl/board/dm355evm.cfg b/tcl/board/dm355evm.cfg
index 2c8bea82..db47b8d4 100644
--- a/tcl/board/dm355evm.cfg
+++ b/tcl/board/dm355evm.cfg
@@ -182,7 +182,7 @@ proc dm355evm_init {} {
########################
# turn on icache - set I bit in cp15 register c1
- mcr 15 0 0 1 0 0x00051078
+ arm mcr 15 0 0 1 0 0x00051078
}
# NAND -- socket has two chipselects, MT29F16G08FAA puts 1GByte on each one.
diff --git a/tcl/board/openrd.cfg b/tcl/board/openrd.cfg
index 12cc79e4..6371effa 100644
--- a/tcl/board/openrd.cfg
+++ b/tcl/board/openrd.cfg
@@ -29,7 +29,7 @@ proc openrd_init { } {
jtag_reset 0 0
wait_halt
- mcr 15 0 0 1 0 0x00052078
+ arm mcr 15 0 0 1 0 0x00052078
mww 0xD0001400 0x43000C30 # DDR SDRAM Configuration Register
mww 0xD0001404 0x37543000 # Dunit Control Low Register
diff --git a/tcl/board/sheevaplug.cfg b/tcl/board/sheevaplug.cfg
index 9267eb95..b843213b 100644
--- a/tcl/board/sheevaplug.cfg
+++ b/tcl/board/sheevaplug.cfg
@@ -29,7 +29,7 @@ proc sheevaplug_init { } {
jtag_reset 0 0
wait_halt
- mcr 15 0 0 1 0 0x00052078
+ arm mcr 15 0 0 1 0 0x00052078
mww 0xD0001400 0x43000C30 # DDR SDRAM Configuration Register
mww 0xD0001404 0x39543000 # Dunit Control Low Register