diff options
Diffstat (limited to 'tcl')
| -rw-r--r-- | tcl/target/ti_dm365.cfg | 97 |
1 files changed, 97 insertions, 0 deletions
diff --git a/tcl/target/ti_dm365.cfg b/tcl/target/ti_dm365.cfg new file mode 100644 index 00000000..f889432b --- /dev/null +++ b/tcl/target/ti_dm365.cfg @@ -0,0 +1,97 @@ +#
+# Texas Instruments DaVinci family: TMS320DM365
+#
+if { [info exists CHIPNAME] } {
+ set _CHIPNAME $CHIPNAME
+} else {
+ set _CHIPNAME dm365
+}
+
+#
+# For now, expect EMU0/EMU1 jumpered LOW (not TI's default) so ARM and ETB
+# are enabled without making ICEpick route ARM and ETB into the JTAG chain.
+#
+# Also note: when running without RTCK before the PLLs are set up, you
+# may need to slow the JTAG clock down quite a lot (under 2 MHz).
+#
+source [find target/icepick.cfg]
+set EMU01 "-enable"
+#set EMU01 "-disable"
+
+# Subsidiary TAP: ARM ETB11, with scan chain for 4K of ETM trace buffer
+if { [info exists ETB_TAPID ] } {
+ set _ETB_TAPID $ETB_TAPID
+} else {
+ set _ETB_TAPID 0x2b900f0f
+}
+jtag newtap $_CHIPNAME etb -irlen 4 -ircapture 0x1 -irmask 0xf \
+ -expected-id $_ETB_TAPID $EMU01
+jtag configure $_CHIPNAME.etb -event tap-enable \
+ "icepick_c_tapenable $_CHIPNAME.jrc 1"
+
+# Subsidiary TAP: ARM926ejs with scan chains for ARM Debug, EmbeddedICE-RT, ETM.
+if { [info exists CPU_TAPID ] } {
+ set _CPU_TAPID $CPU_TAPID
+} else {
+ set _CPU_TAPID 0x0792602f
+}
+jtag newtap $_CHIPNAME arm -irlen 4 -ircapture 0x1 -irmask 0xf \
+ -expected-id $_CPU_TAPID $EMU01
+jtag configure $_CHIPNAME.arm -event tap-enable \
+ "icepick_c_tapenable $_CHIPNAME.jrc 0"
+
+# Primary TAP: ICEpick (JTAG route controller) and boundary scan
+if { [info exists JRC_TAPID ] } {
+ set _JRC_TAPID $JRC_TAPID
+} else {
+ set _JRC_TAPID 0x0b83e02f
+}
+jtag newtap $_CHIPNAME jrc -irlen 6 -ircapture 0x1 -irmask 0x3f \
+ -expected-id $_JRC_TAPID
+
+################
+
+# various symbol definitions, to avoid hard-wiring addresses
+# and enable some sharing of DaVinci-family utility code
+global dm365
+set dm365 [ dict create ]
+
+# Physical addresses for controllers and memory
+# (Some of these are valid for many DaVinci family chips)
+dict set dm365 sram0 0x00010000
+dict set dm365 sram1 0x00014000
+dict set dm365 sysbase 0x01c40000
+dict set dm365 pllc1 0x01c40800
+dict set dm365 pllc2 0x01c40c00
+dict set dm365 psc 0x01c41000
+dict set dm365 gpio 0x01c67000
+dict set dm365 a_emif 0x01d10000
+dict set dm365 a_emif_cs0 0x02000000
+dict set dm365 a_emif_cs1 0x04000000
+dict set dm365 ddr_emif 0x20000000
+dict set dm365 ddr 0x80000000
+
+source [find target/davinci.cfg]
+
+################
+# GDB target: the ARM, using SRAM1 for scratch. SRAM0 (also 16K)
+# and the ETB memory (4K) are other options, while trace is unused.
+set _TARGETNAME $_CHIPNAME.arm
+
+target create $_TARGETNAME arm926ejs -chain-position $_TARGETNAME
+
+# NOTE that work-area-virt presumes a Linux 2.6.30-rc2+ kernel,
+# and that the work area is used only with a kernel mmu context ...
+$_TARGETNAME configure \
+ -work-area-virt [expr 0xfffe0000 + 0x4000] \
+ -work-area-phys [dict get $dm365 sram1] \
+ -work-area-size 0x4000 \
+ -work-area-backup 0
+
+arm7_9 dbgrq enable
+arm7_9 fast_memory_access enable
+arm7_9 dcc_downloads enable
+
+# trace setup
+etm config $_TARGETNAME 16 normal full etb
+etb config $_TARGETNAME $_CHIPNAME.etb
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