diff options
Diffstat (limited to 'tcl')
| -rw-r--r-- | tcl/board/hitex_lpc2929.cfg | 105 | ||||
| -rw-r--r-- | tcl/target/lpc2900.cfg | 65 |
2 files changed, 170 insertions, 0 deletions
diff --git a/tcl/board/hitex_lpc2929.cfg b/tcl/board/hitex_lpc2929.cfg new file mode 100644 index 00000000..d0b28647 --- /dev/null +++ b/tcl/board/hitex_lpc2929.cfg @@ -0,0 +1,105 @@ +# Hitex eval board for LPC2929/LPC2939 +# http://www.hitex.com/ + +# Delays on reset lines +jtag_nsrst_delay 50 +jtag_ntrst_delay 1 + +# Maximum of 1/8 of clock frequency (XTAL = 16 MHz). +# Adaptive clocking through RTCK is not supported. +jtag_khz 2000 + +# Target device: LPC29xx with ETB +# The following variables are used by the LPC2900 script: +# HAS_ETB Must be set to 1. The CPU on this board has ETB. +# FLASH_CLOCK CPU frequency at the time of flash programming (in kHz) +set HAS_ETB 1 +set FLASH_CLOCK 112000 +source [find target/lpc2900.cfg] + +# A working area will help speeding the flash programming +#$_TARGETNAME configure -work-area-phys 0x80000000 -work-area-size 0x2000 -work-area-backup 0 +$_TARGETNAME configure -work-area-phys 0x58000000 -work-area-size 0x10000 -work-area-backup 0 + +# Event handlers +$_TARGETNAME configure -event reset-start { + # Back to the slow JTAG clock + jtag_khz 2000 +} + +# External 16-bit flash at chip select CS7 (SST39VF3201-70, 4 MiB) +flash bank cfi 0x5C000000 0x400000 2 2 $_TARGETNAME jedec_probe + + +$_TARGETNAME configure -event reset-init { + # Flash + mww 0x20200010 0x00000007 # FBWST: 7 wait states, not chached + + # Use PLL + mww 0xFFFF8020 0x00000001 # XTAL_OSC_CONTROL: enable, 1-20 MHz + mww 0xFFFF8070 0x01000000 # SYS_CLK_CONF: Crystal + mww 0xFFFF8028 0x00000005 # PLL: (power down) + mww 0xFFFF8028 0x01060004 # PLL: M=7, 2P=2 (power up) + # --> f=112 MHz, fcco=224 MHz + sleep 100 + mww 0xFFFF8070 0x02000000 # SYS_CLK_CONF: PLL + + # Increase JTAG speed + jtag_khz 6000 + + # Enable external memory bus (16-bit SRAM at CS6, 16-bit flash at CS7) + mww 0xE0001138 0x0000001F # P1.14 = D0 + mww 0xE000113C 0x0000001F # P1.15 = D1 + mww 0xE0001140 0x0000001F # P1.16 = D2 + mww 0xE0001144 0x0000001F # P1.17 = D3 + mww 0xE0001148 0x0000001F # P1.18 = D4 + mww 0xE000114C 0x0000001F # P1.19 = D5 + mww 0xE0001150 0x0000001F # P1.20 = D6 + mww 0xE0001154 0x0000001F # P1.21 = D7 + mww 0xE0001200 0x0000001F # P2.0 = D8 + mww 0xE0001204 0x0000001F # P2.1 = D9 + mww 0xE0001208 0x0000001F # P2.2 = D10 + mww 0xE000120C 0x0000001F # P2.3 = D11 + mww 0xE0001210 0x0000001F # P2.4 = D12 + mww 0xE0001214 0x0000001F # P2.5 = D13 + mww 0xE0001218 0x0000001F # P2.6 = D14 + mww 0xE000121C 0x0000001F # P2.7 = D15 + mww 0xE0001104 0x00000007 # P1.1 = A1 + mww 0xE0001108 0x00000007 # P1.2 = A2 + mww 0xE000110C 0x00000007 # P1.3 = A3 + mww 0xE0001110 0x00000007 # P1.4 = A4 + mww 0xE0001114 0x00000007 # P1.5 = A5 + mww 0xE0001118 0x00000007 # P1.6 = A6 + mww 0xE000111C 0x00000007 # P1.7 = A7 + mww 0xE0001028 0x00000007 # P0.10 = A8 + mww 0xE000102C 0x00000007 # P0.11 = A9 + mww 0xE0001030 0x00000007 # P0.12 = A10 + mww 0xE0001034 0x00000007 # P0.13 = A11 + mww 0xE0001038 0x00000007 # P0.14 = A12 + mww 0xE000103C 0x00000007 # P0.15 = A13 + mww 0xE0001048 0x00000007 # P0.18 = A14 + mww 0xE000104C 0x00000007 # P0.19 = A15 + mww 0xE0001050 0x00000007 # P0.20 = A16 + mww 0xE0001054 0x00000007 # P0.21 = A17 + mww 0xE0001058 0x00000007 # P0.22 = A18 + mww 0xE000105C 0x00000007 # P0.23 = A19 + mww 0xE0001238 0x00000007 # P2.14 = BLS0 + mww 0xE000123C 0x00000007 # P2.15 = BLS1 + mww 0xE0001300 0x00000007 # P3.0 = CS6 + mww 0xE0001304 0x00000007 # P3.1 = CS7 + mww 0xE0001130 0x00000007 # P1.12 = OE_N + mww 0xE0001134 0x00000007 # P1.13 = WE_N + mww 0x600000BC 0x00000041 # Bank6 16-bit mode, RBLE=1 + mww 0x600000B4 0x00000000 # Bank6 WSTOEN=0 + mww 0x600000AC 0x00000005 # Bank6 WST1=5 + mww 0x600000B8 0x00000001 # Bank6 WSTWEN=1 + mww 0x600000B0 0x00000006 # Bank6 WST2=6 + mww 0x600000A8 0x00000002 # Bank6 IDCY=2 + mww 0x600000D8 0x00000041 # Bank7 16-bit mode, RBLE=1 + mww 0x600000D0 0x00000000 # Bank7 WSTOEN=0 + mww 0x600000C8 0x0000000A # Bank7 WST1=10 + mww 0x600000D4 0x00000001 # Bank7 WSTWEN=1 + mww 0x600000CC 0x0000000C # Bank7 WST2=8 + mww 0x600000C4 0x00000002 # Bank7 IDCY=2 +} + diff --git a/tcl/target/lpc2900.cfg b/tcl/target/lpc2900.cfg new file mode 100644 index 00000000..fa5bd5bb --- /dev/null +++ b/tcl/target/lpc2900.cfg @@ -0,0 +1,65 @@ + +if { [info exists CHIPNAME] } { + set _CHIPNAME $CHIPNAME +} else { + set _CHIPNAME lpc2900 +} + +if { [info exists CPUTAPID ] } { + set _CPUTAPID $CPUTAPID +} else { + set _CPUTAPID 0x0596802B +} + +if { [info exists HAS_ETB ] } { +} else { + # Set default (no ETB). + # Show a warning, because this should have been configured explicitely. + set HAS_ETB 0 + # TODO warning? +} + +if { [info exists ETBTAPID ] } { + set _ETBTAPID $ETBTAPID +} else { + set _ETBTAPID 0x1B900F0F +} + +# TRST and SRST both exist, and can be controlled independently +reset_config trst_and_srst separate + +# Define the _TARGETNAME +set _TARGETNAME [format "%s.cpu" $_CHIPNAME] + +# Include the ETB tap controller if asked for. +# Has to be done manually for newer devices (not an "old" LPC2917/2919). +if { $HAS_ETB == 1 } { + # Clear the HAS_ETB flag. Must be set again for a new tap in the chain. + set HAS_ETB 0 + + # Add the ETB tap controller and the ARM9 core debug tap + jtag newtap $_CHIPNAME etb -irlen 4 -ircapture 0x1 -irmask 0xf -expected-id $_ETBTAPID + jtag newtap $_CHIPNAME cpu -irlen 4 -ircapture 0x1 -irmask 0xf -expected-id $_CPUTAPID + + # Create the ".cpu" target + target create $_TARGETNAME arm966e -endian little -chain-position $_TARGETNAME -variant arm966e + + # Configure ETM and ETB + etm config $_TARGETNAME 8 normal full etb + etb config $_TARGETNAME $_CHIPNAME.etb + +} else { + # Add the ARM9 core debug tap + jtag newtap $_CHIPNAME cpu -irlen 4 -ircapture 0x1 -irmask 0xf -expected-id $_CPUTAPID + + # Create the ".cpu" target + target create $_TARGETNAME arm966e -endian little -chain-position $_TARGETNAME -variant arm966e +} + +arm7_9 dbgrq enable +arm7_9 dcc_downloads enable + +# Flash bank configuration: +# Flash: flash bank lpc2900 0 0 0 0 <target#> <flash clock (CLK_SYS_FMC) in kHz> +# Flash base address, total flash size, and number of sectors are all configured automatically. +flash bank lpc2900 0 0 0 0 $_TARGETNAME $FLASH_CLOCK |