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* David Brownell <david-b@pacbell.net>More Thumb2 disassembly:oharboe2009-08-201-2/+136
| | | | | | | | | | | | | | | ARMv7-M: A5.3.6 Load/store dual or exclusive, table branch GCC will generate the table branch instructions, usually with inlined tables that will confuse this disassembler. LDREX and STREX are not issued by GCC without inline assembly. This means all Thumb2 instructions implemented by Cortex-M3 can now be disassembled. Cortex-A8 cores support more Thumb2 instructions, but most of those aren't yet publicly documented. git-svn-id: svn://svn.berlios.de/openocd/trunk@2598 b42882b7-edfa-0310-969c-e2dbd0fdcd60
* Jonas Horberg [jhorberg@sauer-danfoss.com]:ntfreak2009-08-191-1/+1
| | | | | | Fix small typo in ftd2xx type detection git-svn-id: svn://svn.berlios.de/openocd/trunk@2597 b42882b7-edfa-0310-969c-e2dbd0fdcd60
* David Brownell <david-b@pacbell.net>Fix some command helptext:oharboe2009-08-191-4/+13
| | | | | | | | | - spell "address" right - list bp/wp params as optional And make those source lines wrap at sane margins. git-svn-id: svn://svn.berlios.de/openocd/trunk@2596 b42882b7-edfa-0310-969c-e2dbd0fdcd60
* David Brownell <david-b@pacbell.net> Clean up some Cortex-M3 reset handling.oharboe2009-08-191-17/+39
| | | | | | | | | | | | | | - AIRCR_SYSRESETREQ is generic; use it on any system where SRST won't fly, not just on Stellaris-based ones. - Reformat and improve comments about the Stellaris quirk; and xref the only public docs (an email) about the issue. It seems that *most* Stellaris chips have this problem. Tempest parts aren't yet in general sampling; and if rev B silicon for earlier chips exists, it's not very visible yet. git-svn-id: svn://svn.berlios.de/openocd/trunk@2595 b42882b7-edfa-0310-969c-e2dbd0fdcd60
* David Brownell [david-b@pacbell.net]:ntfreak2009-08-181-10/+21
| | | | | | | | | | | | | Simplify dumping of register lists by only printing cached values if they are marked as valid. Most of the time, they are invalid; so printing *any* value is just misleading. Note that for ARM7 and ARM9 most EmbeddedICE registers (except for debug status) could be cached most of the time; and their register cache isn't maintained properly (many accesses seem to bypass that cache code). git-svn-id: svn://svn.berlios.de/openocd/trunk@2594 b42882b7-edfa-0310-969c-e2dbd0fdcd60
* Brian Findlay <findlaybrian@gmail.com> Board support for mini2440 ↵oharboe2009-08-181-0/+321
| | | | | | (friendlyARM) samsung s3c2440 based board git-svn-id: svn://svn.berlios.de/openocd/trunk@2593 b42882b7-edfa-0310-969c-e2dbd0fdcd60
* - add cfg file for Amontec JTAGKey2 jtag interfacentfreak2009-08-182-0/+14
| | | | git-svn-id: svn://svn.berlios.de/openocd/trunk@2592 b42882b7-edfa-0310-969c-e2dbd0fdcd60
* Jonas Horberg [jhorberg@sauer-danfoss.com]ntfreak2009-08-183-217/+229
| | | | | | | | | | | | | | | | | | | | | | | | | https://lists.berlios.de/pipermail/openocd-development/2009-August/009939.html 1. It can only be built with the FTD2XX driver. libftdi supports FT2232H/FT4232H since version 0.16 2. A speed value of 0 is used as a RTCK request indicator. This clashes with the valid clock division value 0 that provide the highest fixed clock frequency. 3. The ft2232_speed_div function return the maximum selectable frequency (30MHz) when RTCK is activated. It should return 0. 4. The ft2232_khz function return ERROR_OK when RTCK is requested even for devices lacking RTCK support. It should return ERROR_FAIL so the upper driver layers can detect this and try to fallback to a fixed frequency. 5. FT2232H/FT4232H have a backward compatibility function that divide the clock by 5 to get the same frequency range as FT2232D. There is no code that disable this functionality. I can not find anything about if this is enabled or disabled by default. I think it is safest to actively disable it. git-svn-id: svn://svn.berlios.de/openocd/trunk@2591 b42882b7-edfa-0310-969c-e2dbd0fdcd60
* Jonas Horberg [jhorberg@sauer-danfoss.com]ntfreak2009-08-184-39/+131
| | | | | | Change jtag_rclk behaviour so it can be called before the interface init function git-svn-id: svn://svn.berlios.de/openocd/trunk@2590 b42882b7-edfa-0310-969c-e2dbd0fdcd60
* David Brownell <david-b@pacbell.net> Cleanup the Stellaris target configs:oharboe2009-08-185-59/+21
| | | | | | | | | | | | | | | | - remove endianness options; these chips hard-wire "little" - $_TARGETNAME updates: * don't pass $_TARGETNAME where a TAP label is required * flash config uses $_TARGETNAME (it might not be target #0) * simplify one $_TARGETNAME construction - update work area setup: * remove VM spec; these chips have no VM! * fix some wrong sizes (0x4000 == 16K, not 4K) * simplify: take defaults - comment fixups git-svn-id: svn://svn.berlios.de/openocd/trunk@2589 b42882b7-edfa-0310-969c-e2dbd0fdcd60
* David Brownell <david-b@pacbell.net> Add "cortex_m3 vector_catch" command ↵oharboe2009-08-183-4/+115
| | | | | | | | | | | | | | | | and docs. One minor issue with this is that the core debug support uses this mechanism, then trashes its state over reset. Users can Work around that (for now) by re-assigning the desired config after reset. Also fixes "target halted due to target-not-halted" goof. When we can't describe the reason using OpenOCD's limited vocabulary, say "reason undefined" instead of saying it's not halted. git-svn-id: svn://svn.berlios.de/openocd/trunk@2588 b42882b7-edfa-0310-969c-e2dbd0fdcd60
* David Brownell <david-b@pacbell.net> Clean up ARM7/ARM9 EmbeddedICE register ↵oharboe2009-08-182-49/+131
| | | | | | | | | | | | | | handling ... don't use parallel arrays (error prone) or assume all registers are 32-bits wide (they can have fewer bits); don't use spaces in register names, so they can be passed more easily to the "reg" command. Minor updates for ARM9 vector_catch support: it's an 8-bit value. This seems to help this core's vector_catch command work a bit better; but its behavior wih the register cache is still goofy. git-svn-id: svn://svn.berlios.de/openocd/trunk@2587 b42882b7-edfa-0310-969c-e2dbd0fdcd60
* David Brownell <david-b@pacbell.net> Several of the ARMv7M registers are 8 ↵oharboe2009-08-181-29/+30
| | | | | | | | | bits or less; don't display them as 32 bits unless that's their true size. (Removes some confusion. git-svn-id: svn://svn.berlios.de/openocd/trunk@2586 b42882b7-edfa-0310-969c-e2dbd0fdcd60
* Piotr Ziecik <kosmo@semihalf.com> Due to errors in chipselect management in ↵oharboe2009-08-181-3/+3
| | | | | | | | | | davinci_nand driver OpenOCD was able to access only to chips attached to first EMIF chipselect. This patch fixes chipselect management code and allows OpenOCD to access to NAND devices attached to any EMIF CS line. git-svn-id: svn://svn.berlios.de/openocd/trunk@2585 b42882b7-edfa-0310-969c-e2dbd0fdcd60
* Xiaofan Chen <xiaofanc@gmail.com> Split LM3S811 config file into target file ↵oharboe2009-08-162-12/+21
| | | | | | and board file git-svn-id: svn://svn.berlios.de/openocd/trunk@2584 b42882b7-edfa-0310-969c-e2dbd0fdcd60
* michal smulski <michal.smulski@ooma.com> arm11 target config filesoharboe2009-08-162-0/+74
| | | | git-svn-id: svn://svn.berlios.de/openocd/trunk@2583 b42882b7-edfa-0310-969c-e2dbd0fdcd60
* Xiaofan Chen <xiaofanc@gmail.com> Add config file for TI-Luminary LM3S1968 ↵oharboe2009-08-162-0/+58
| | | | | | chip and EK-LM3S1968 board git-svn-id: svn://svn.berlios.de/openocd/trunk@2582 b42882b7-edfa-0310-969c-e2dbd0fdcd60
* Ferdinand Postema <ferdinand@postema.eu> cygwin 32 bit warningoharboe2009-08-161-1/+1
| | | | git-svn-id: svn://svn.berlios.de/openocd/trunk@2581 b42882b7-edfa-0310-969c-e2dbd0fdcd60
* added note w/reference to discussion on whether or not arm11 code is broken ↵oharboe2009-08-161-0/+4
| | | | | | or not. git-svn-id: svn://svn.berlios.de/openocd/trunk@2580 b42882b7-edfa-0310-969c-e2dbd0fdcd60
* Audrius Urmanavičius [didele.deze@gmail.com]:ntfreak2009-08-135-84/+264
| | | | | | | Add flash programming support for NXP LPC1700 cortex_m3 based family git-svn-id: svn://svn.berlios.de/openocd/trunk@2579 b42882b7-edfa-0310-969c-e2dbd0fdcd60
* David Brownell <david-b@pacbell.net>:ntfreak2009-08-071-0/+3
| | | | | | Warn about anyone using "jtag_speed" commands; that command is obsolete, and will someday be removed. git-svn-id: svn://svn.berlios.de/openocd/trunk@2578 b42882b7-edfa-0310-969c-e2dbd0fdcd60
* David Brownell <david-b@pacbell.net>:ntfreak2009-08-071-1/+4
| | | | | | | Better explanation for the TAP "-ircapture" parameter. git-svn-id: svn://svn.berlios.de/openocd/trunk@2577 b42882b7-edfa-0310-969c-e2dbd0fdcd60
* Ferdinand Postema [ferdinand@postema.eu]ntfreak2009-08-071-0/+3
| | | | | | - fix vector catch issues with certain ARM9 cores - AT91SAM9260 and STR9 git-svn-id: svn://svn.berlios.de/openocd/trunk@2576 b42882b7-edfa-0310-969c-e2dbd0fdcd60
* - fix segfault introduced during cortex reg cleanupntfreak2009-08-071-2/+2
| | | | git-svn-id: svn://svn.berlios.de/openocd/trunk@2575 b42882b7-edfa-0310-969c-e2dbd0fdcd60
* Gary Carlson [gcarlson@carlson-minot.com]:ntfreak2009-08-061-3/+1
| | | | | | - revert patch from rev1507 as it was causing reset issues with arm9 cores git-svn-id: svn://svn.berlios.de/openocd/trunk@2574 b42882b7-edfa-0310-969c-e2dbd0fdcd60
* - Bring all the ftdi names inline in the cfg scripts. scripts will now work ↵ntfreak2009-08-0618-18/+18
| | | | | | for either ftd2xx or libftdi drivers. git-svn-id: svn://svn.berlios.de/openocd/trunk@2573 b42882b7-edfa-0310-969c-e2dbd0fdcd60
* michal smulski <michal.smulski@ooma.com>:zwelch2009-08-061-2/+2
| | | | | | | Fix ARM11 half-word bulk memory read and write. git-svn-id: svn://svn.berlios.de/openocd/trunk@2572 b42882b7-edfa-0310-969c-e2dbd0fdcd60
* - add configure error if building parport interface under cygwin and ↵ntfreak2009-07-311-0/+4
| | | | | | sys/io.h missing git-svn-id: svn://svn.berlios.de/openocd/trunk@2571 b42882b7-edfa-0310-969c-e2dbd0fdcd60
* Fix NPE in GDB_EVENT_END as logforwarding was not disabled early enoughoharboe2009-07-271-1/+7
| | | | git-svn-id: svn://svn.berlios.de/openocd/trunk@2570 b42882b7-edfa-0310-969c-e2dbd0fdcd60
* add "dummy" interface trick to the BUGS reporting suggestionsoharboe2009-07-271-1/+8
| | | | git-svn-id: svn://svn.berlios.de/openocd/trunk@2569 b42882b7-edfa-0310-969c-e2dbd0fdcd60
* David Brownell <david-b@pacbell.net> More testcase work:oharboe2009-07-261-7/+16
| | | | | | | | | | | | | | | | A5.3.11 Data processing (shifted register) The usual kinds of problems; the most noteworthy were that the "S"et flags bit was mis-handled in these instructions. --- This is the last patch from a quickie set of tests covering all encodings of the instructions with 32-bit opcodes. There may be some corner cases left, plus the instructions that aren't yet handled, but the Thumb2 disassembler is no longer just "lightly" tested with GCC output ... the new code paths have mostly been verified. git-svn-id: svn://svn.berlios.de/openocd/trunk@2568 b42882b7-edfa-0310-969c-e2dbd0fdcd60
* More instruction decoding fixes:oharboe2009-07-261-16/+32
| | | | | | | | | | | A5.3.5 Load/store multiple A5.3.7 Load word There was a longstanding bug in Thumb-1 LDM; the rest of the LDM/STM fixes are just using width specs to match UAL syntax, except for two opcode name typos. Load word had two bitmask goofs. git-svn-id: svn://svn.berlios.de/openocd/trunk@2567 b42882b7-edfa-0310-969c-e2dbd0fdcd60
* David Brownell <david-b@pacbell.net> More fixes from test cases:oharboe2009-07-261-7/+11
| | | | | | | | | | A5.3.8 Load halfword, unallocated memory hints It's mostly the usual sort of bitmasking goofage and getting the width specs right. In one case an older x86 GCC generated bad code unless I structred a conditional differently (sigh). git-svn-id: svn://svn.berlios.de/openocd/trunk@2566 b42882b7-edfa-0310-969c-e2dbd0fdcd60
* David Brownell <david-b@pacbell.net> More instruction decoding fixes:oharboe2009-07-261-8/+12
| | | | | | | | | | | A5.3.5 Load/store multiple A5.3.7 Load word There was a longstanding bug in Thumb-1 LDM; the rest of the LDM/STM fixes are just using width specs to match UAL syntax, except for two opcode name typos. Load word had two bitmask goofs. git-svn-id: svn://svn.berlios.de/openocd/trunk@2565 b42882b7-edfa-0310-969c-e2dbd0fdcd60
* David Brownell <david-b@pacbell.net> More instruction decoding fixes based ↵oharboe2009-07-241-9/+10
| | | | | | | | | | | | | | | | on test cases, covering ARMv7-M arch manual: A5.3.1 Data processing (modified immediate) A5.3.3 Data processing (plain binary immediate) A5.3.4 Branches and miscellaneous control and other (immediate) encodings referenced there. Several of these just tweak the new syntax ("Unified" ARM/Thumb: UAL) but there were a few bugs too. git-svn-id: svn://svn.berlios.de/openocd/trunk@2564 b42882b7-edfa-0310-969c-e2dbd0fdcd60
* David Brownell <david-b@pacbell.net> Bugfix some instruction decoding ... ↵oharboe2009-07-241-4/+4
| | | | | | | | | | | | | | | | | I've crafted asm files with testcases covering several new encodings in these sections of the ARMv7-M arch manual: A5.3.12 Data processing (register) A5.3.13 Miscellaneous operations A5.3.14 Multiply, and multiply accumulate A5.3.15 Long multiply, long multiply accumulate, and divide The issues were mostly in '12 and '13; some new related 16-bit opcodes had issues too. git-svn-id: svn://svn.berlios.de/openocd/trunk@2563 b42882b7-edfa-0310-969c-e2dbd0fdcd60
* Andreas Fritiofson <andreas.fritiofson@gmail.com> I noticed there are a few ↵oharboe2009-07-241-10/+5
| | | | | | | | | checks for (rt == 0xf) even though that case is handled with an early return at the top of the function. git-svn-id: svn://svn.berlios.de/openocd/trunk@2562 b42882b7-edfa-0310-969c-e2dbd0fdcd60
* David Brownell <david-b@pacbell.net> thumb2 disassembly for Load halfwordoharboe2009-07-231-1/+86
| | | | git-svn-id: svn://svn.berlios.de/openocd/trunk@2561 b42882b7-edfa-0310-969c-e2dbd0fdcd60
* David Brownell <david-b@pacbell.net> thumb2 disassembly for Load byte, ↵oharboe2009-07-231-0/+170
| | | | | | memory hints git-svn-id: svn://svn.berlios.de/openocd/trunk@2560 b42882b7-edfa-0310-969c-e2dbd0fdcd60
* Ferdinand Postema <ferdinand@postema.eu> fix cygwin warningsoharboe2009-07-233-6/+6
| | | | git-svn-id: svn://svn.berlios.de/openocd/trunk@2559 b42882b7-edfa-0310-969c-e2dbd0fdcd60
* David Brownell <david-b@pacbell.net> fix warningsoharboe2009-07-231-44/+50
| | | | git-svn-id: svn://svn.berlios.de/openocd/trunk@2558 b42882b7-edfa-0310-969c-e2dbd0fdcd60
* Jonathan Cameron <jic23@cam.ac.uk> fix regression from 1836 when the ↵oharboe2009-07-221-0/+2
| | | | | | reset_config command was removed from pxa270.cfg git-svn-id: svn://svn.berlios.de/openocd/trunk@2557 b42882b7-edfa-0310-969c-e2dbd0fdcd60
* Stefano Voulaz <s.voulaz@projecktstudio.com> first cut samsung_s3c2450 oharboe2009-07-221-0/+49
| | | | git-svn-id: svn://svn.berlios.de/openocd/trunk@2556 b42882b7-edfa-0310-969c-e2dbd0fdcd60
* David Brownell <david-b@pacbell.net>:ntfreak2009-07-211-3/+10
| | | | | | | | | | | Dump SP on poll, and show whether it's MSP or PSP. Thread mode can use either stack pointer, so this is part of the state that's not yet displayed. Shrink some lines. git-svn-id: svn://svn.berlios.de/openocd/trunk@2555 b42882b7-edfa-0310-969c-e2dbd0fdcd60
* David Brownell <david-b@pacbell.net>:ntfreak2009-07-213-104/+152
| | | | | | | | | | | | | | | | | | | | | | Clean up treatment of registers in ARMv7-M and Cortex-M3. - At the arch level: * Just list registers and names; don't impose core-specific policy about how they are accessed. * Each register has a symbol. * Remove the register mode field (irrelevant to debugger) - At the core/implementation level: * Just map the registers to their relevant access methods; don't require the arch level to say how that should work (cores other than Cortex-M3 could do it differently). * Don't use undefined bits from register 20. * Use register IDs that are part of the ARMv7-M interface. In short, there's now a real distinction between the arch and core layers. git-svn-id: svn://svn.berlios.de/openocd/trunk@2554 b42882b7-edfa-0310-969c-e2dbd0fdcd60
* David Brownell <david-b@pacbell.net>:ntfreak2009-07-211-11/+18
| | | | | | | | | | | | | | | Minor updates to the Thumb2 disassembly: - Bugfixes: * Distinguish branch from misc via "!=" not "==" * MRS register shift is 8 bits (vs MSR being 16) - Format tweaks: * CPS needed tab (not space) * add commma before some shifts * add space after comma in LDM/STM * use ".W" width spec on various instructions git-svn-id: svn://svn.berlios.de/openocd/trunk@2553 b42882b7-edfa-0310-969c-e2dbd0fdcd60
* David Brownell <david-b@pacbell.net>:ntfreak2009-07-214-75/+32
| | | | | | | | | Revert parts of the previous ARMv7-M register patch. It turns out that part of the issue is a documentation problem for the Cortex-M3 r1 parts. So for the rest, simpler fixes are possible (in followup patch). git-svn-id: svn://svn.berlios.de/openocd/trunk@2552 b42882b7-edfa-0310-969c-e2dbd0fdcd60
* - fix issue with reading device id, bug appeared when flash_address code was ↵ntfreak2009-07-201-3/+4
| | | | | | | | added - fix issue when multiple flash chips are connected, eg. x16 x 2 on 32bit mcu bus git-svn-id: svn://svn.berlios.de/openocd/trunk@2551 b42882b7-edfa-0310-969c-e2dbd0fdcd60
* aduc flash problems have been resolvedoharboe2009-07-191-8/+0
| | | | git-svn-id: svn://svn.berlios.de/openocd/trunk@2550 b42882b7-edfa-0310-969c-e2dbd0fdcd60
* Andreas Fritiofson <andreas.fritiofson@gmail.com> UTF8 fixesoharboe2009-07-1772-76/+76
| | | | git-svn-id: svn://svn.berlios.de/openocd/trunk@2549 b42882b7-edfa-0310-969c-e2dbd0fdcd60
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