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* Add board/redbee-usb.cfgMariano Alvira2010-02-283-0/+14
| | | | | | | | | | | The Redbee USB is a small form-factor usb stick from Redwire, LLC (www.redwirellc.com/store), built around a Freescale MC13224V ARM7TDMI + 802.15.4 radio (plus antenna). It includes an FT2232H for debugging, with Channel B connected to the mc13224v's JTAG interface (unusual) and Channel A connected to UART1. Signed-off-by: David Brownell <dbrownell@users.sourceforge.net>
* add board/redbee-econotag.cfg and JTAG supportMariano Alvira2010-02-273-0/+112
| | | | | | | | | | | | | | | | | | | | | | | | | | The Redbee Econotag is an open hardware development kit from Redwire, LLC (www.redwirellc.com/store), for the Freescale MC13224V ARM7TDMI + 802.15.4 radio. It includes both an MC13224V and an FT2232H (for JTAG and UART support). It has flexible power supply options. Additional features are: - inverted-F pcb antenna - 36 GPIO brought out to 0.1" pin header (includes all peripheral pins) - Reset button - Two push buttons (on kbi1-5 and kbi0-4) - USB-A connector, powered from USB - up to 16V external input - pads for optional buck inductor - pads for optional 32.768kHz crystal - 2x LEDS on TX_ON and RX_ON [ dbrownell@users.sourceforge.net: shrink lines; texi ] Signed-off-by: David Brownell <dbrownell@users.sourceforge.net>
* Add target/mc13224v.cfgMariano Alvira2010-02-271-0/+54
| | | | | | | | | | | | | | | | | The MC13224V is a FreeScale ARM7TDMI based IEEE802.15.4 platform for Zigbee and similar low-power wireless applications. Using PIP (Platform In Package) technology, it integrates: an RF balun and matching network; a buck converter (only an external inductor is necessary); 96KB of SRAM; and 128KB of non-volatile memory. It has an integrated bootloader and can boot from a variety of sources: external SPI or I2C non-volatile memory, an image loaded over UART1, or the internal non-volatile memory. The image loaded from one of these sources is executed directly from SRAM starting at location 0x00400000. Open source development code at http://mc1322x.devl.org Signed-off-by: David Brownell <dbrownell@users.sourceforge.net>
* new "stellaris recover" commandDavid Brownell2010-02-273-0/+87
| | | | | | | | | | | | | | | Stellaris chips have a procedure for restoring the chip to what's effectively the "as-manufactured" state, with all the non-volatile memory erased. That includes all flash memory, plus things like the flash protection bits and various control words which can for example disable debugger access. clearly, this can be useful during development. Luminary/TI provides an MS-Windows utility to perform this procedure along with its Stellaris developer kits. Now OpenOCD users will no longer need to use that MS-Windows utility. Signed-off-by: David Brownell <dbrownell@users.sourceforge.net>
* ADIv5 DAP ops switching to JTAG or SWD modesDavid Brownell2010-02-272-0/+121
| | | | | | | | | | | Define two new DAP operations which use the new jtag_add_tms_seq() calls to put the DAP's transport into either SWD or JTAG mode, when the hardware allows. Tested with the Stellaris 'Recovering a "Locked" Device' procedure, which loops five times over both of these. Signed-off-by: David Brownell <dbrownell@users.sourceforge.net>
* ft2232: implement TMS sequence commandDavid Brownell2010-02-271-2/+72
| | | | | | | Implement the new TMS_SEQ command on FT2232 hardware. Also, swap a bogus exit() call with a clean failure return. Signed-off-by: David Brownell <dbrownell@users.sourceforge.net>
* interface: define TMS sequence commandDavid Brownell2010-02-278-11/+124
| | | | | | | | | | | | | | | | | | | | | | | For support of SWD we need to be able to clock out special bit sequences over TMS or SWDIO. Create this as a generic operation, not yet called by anything, which is split as usual into: - upper level abstraction ... here, jtag_add_tms_seq(); - midlayer implementation logic hooking that to the lowlevel code; - lowlevel minidriver operation ... here, interface_add_tms_seq(); - message type for request queue, here JTAG_TMS. This is done slightly differently than other operations: there's a flag saying whether the interface driver supports this request. (In fact a flag *word* so upper layers can learn about other capabilities too ... for example, supporting SWD operations.) That approach (flag) lets this method *eventually* be used to eliminate pathmove() and statemove() support from most adapter drivers, by moving all that logic into the mid-layer and increasing uniformity between the various drivers. (Which will in turn reduce subtle bugginess.) Signed-off-by: David Brownell <dbrownell@users.sourceforge.net>
* ft2232: add a mechanism to specify channel in layout structsMariano Alvira2010-02-251-3/+7
| | | | | | | | | | | | | | | | | | | | | | | FT2232-family chips have two or more MPSSE modules. FTDI documentation calls these channels. JTAG adapter drivers thus need to be able to choose which channel to use. (For example, one channel may connect to a board's microcontroller, while another connects to a CPLD.) Since each channel has its own USB interface, libftdi (somewhat confusingly) identifies channels using INTERFACE_* symbols. Most boards use INTERFACE_A for JTAG, which is the default in OpenOCD. But some wire up a different one. Note that there are two facets of what makes a wiring "layout": - The mapping between debug signals map and channel signals ... embedded in C functions. - Label used in Tcl configuration scripts ... part of the "layout" structure. By letting the channel be part of the layout struct, we permit sharing the C functions between Tcl-visible layouts, when those signal mappings are reused. Signed-off-by: David Brownell <dbrownell@users.sourceforge.net>
* ARM ADIv5 doxygen and cleanupDavid Brownell2010-02-241-15/+42
| | | | | | | Add doxygen for mem_ap_read_buf_u{8,16,32}() calls, and shrink a few overlong lines. Signed-off-by: David Brownell <dbrownell@users.sourceforge.net>
* AVR flash: handle AT90CAN128 chipsHans Peter Mortensn2010-02-241-4/+26
| | | | | | | | | I have successfully programmed the AT90CAN128, based on the mega128   with some small modifications. [ dbrownell@users.sourceforge.net: patch cleanup ] Signed-off-by: David Brownell <dbrownell@users.sourceforge.net>
* ARM ADIv5: rename more JTAG-specific routinesDavid Brownell2010-02-231-11/+11
| | | | | | | Highlight more of the internal JTAG-specific utilities, so it's easier to identify code needing changes to become transport-neutral. Signed-off-by: David Brownell <dbrownell@users.sourceforge.net>
* arm11: improve performance using minidriver hookØyvind Harboe2010-02-221-3/+65
| | | | | | | | | | | | | | | | zy1000 performance for GDB load went from 100kBytes/s to 300kBytes/s @ 8 MHz by implementing the inner loop of unack arm11 memory writes directly on top of the hw fifo. Profiling info: 78.57 0.77 0.77 arm11_run_instr_data_to_core_noack_inner 5.10 0.82 0.05 memcpy 4.08 0.86 0.04 jtag_tap_next_enabled 3.06 0.89 0.03 gdb_input Signed-off-by: Øyvind Harboe <oyvind.harboe@zylin.com>
* arm11: allow minidrivers to implement inner loop of memory writesØyvind Harboe2010-02-222-45/+100
| | | | | | | | | | | | | | | This allows minidrivers to e.g. hardware accelerate memory writes. Same trick as is used for arm7/9 dcc writes. Added error propagation for memory transfer failures in code rearrangement. Also the JTAG end state is not updated until after the memory write run is complete. Signed-off-by: Øyvind Harboe <oyvind.harboe@zylin.com>
* zy1000: jtag_add_dr_scan() performance improvementØyvind Harboe2010-02-221-8/+15
| | | | | | Reduce overhead in jtag_add_dr_scan() a bit. Signed-off-by: Øyvind Harboe <oyvind.harboe@zylin.com>
* ft2232 table init cleanupDavid Brownell2010-02-211-19/+78
| | | | | | | | Use labeled initializers in the table of layouts instead of positional ones. This ls cleaner and less error prone, plus it simplifies patches which add members to these structure. Signed-off-by: David Brownell <dbrownell@users.sourceforge.net>
* Developer's Guide: refresh release proceduresDavid Brownell2010-02-211-44/+99
| | | | | | | | | | Be a closer match to what I've actually done for the past few cycles. In particular, hold off pushing repository updates until after the packages are published, as part of opening the merge window, and mention the utility commands which actually create the archives. Signed-off-by: David Brownell <dbrownell@users.sourceforge.net>
* ADIv5: relocate memacess_tck cyclesDavid Brownell2010-02-211-12/+12
| | | | | | | | | | | | | When using an AP to access a memory (or a memory-mapped register), some extra TCK (assuming JTAG) cycles should be added to ensure the AP has enugh time to complete that access before trying to collect the response. The previous code was adding these cycles *before* trying to access (read or write) data to that address, not *after*. Fix by putting the delays in the right location. Signed-off-by: David Brownell <dbrownell@users.sourceforge.net>
* ADIv5: remove ATOMIC/COMPOSITE interface modeDavid Brownell2010-02-213-98/+29
| | | | | | | | | | | | | This removes context-sensitivity from the programming interface and makes it possible to know what a block of code does without needing to know the previous history (specifically, the DAP's "trans_mode" setting). The mode was only set to ATOMIC briefly after DAP initialization, making this patch be primarily cleanup; almost everything depends on COMPOSITE. The transactions which shouldn't have been queued were already properly flushing the queue. Signed-off-by: David Brownell <dbrownell@users.sourceforge.net>
* ARM: ADIv5, deadcode cleanupDavid Brownell2010-02-211-13/+13
| | | | | | | | | | | | I have no idea what the scan_inout_check() was *expecting* to achieve by issuing a read of the DP_RDBUFF register. But in any case, that code was clearly never being called ("invalue" always NULL) ... so remove it, and the associated comment. Also rename it as ap_write_check(), facilitating a cleanup of its single call site by removing constant parameters. Signed-off-by: David Brownell <dbrownell@users.sourceforge.net>
* ARM: ADIv5 code shrinkage, cleanupDavid Brownell2010-02-211-40/+16
| | | | | | | | | | adi_jtag_dp_scan_u32() now wraps adi_jtag_dp_scan(), removing code duplication. Include doxygen for the former. Comment some particularly relevant points. Minor fault handling fixes for both routines: don't register a callback that can't run, or return ERROR_OK after an error. Signed-off-by: David Brownell <dbrownell@users.sourceforge.net>
* ADIv5 clean up AP fault handlingDavid Brownell2010-02-211-32/+46
| | | | | | | | | | | | | | | | | Pass up fault codes from various routines, so their callers can clean up after failures, and remove the FIXME comments highlighting those previously goofy code paths. dap_ap_{read,write}_reg_u32() dap_ap_write_reg() mem_ap_{read,write}_u32() mem_ap_{read,write}_atomic_u32() dap_setup_accessport() Make dap_ap_write_reg_u32() just wrap dap_ap_write_reg(), instead of cloning its core code (and broken fault handling). Signed-off-by: David Brownell <dbrownell@users.sourceforge.net>
* ADIv5 clean up AP selection and register cachingDavid Brownell2010-02-214-34/+60
| | | | | | | | | | | | | | | | | | | Handling of AP (and AP register bank) selection, and cached AP registers, is pretty loose ... start tightening it: - It's "AP bank" select support ... there are no DP banks. Rename. + dap_dp_bankselect() becomes dap_ap_bankselect() + "dp_select_value" struct field becomes "ap_bank_value" - Remove duplicate AP cache init paths ... only use dap_ap_select(), and don't make Cortex (A8 or M3) cores roll their own code. - For dap_ap_bankselect(), pass up any fault code from writing the SELECT register. (Nothing yet checks those codes.) - Add various bits of Doxygen Signed-off-by: David Brownell <dbrownell@users.sourceforge.net>
* ARM: keep a handle to the PCDavid Brownell2010-02-2116-88/+106
| | | | | | | | | | | | | | | | Keep a handle to the PC in "struct arm", and use it. This register is used a fair amount, so this is a net minor code shrink (other than some line length fixes), but mostly it's to make things more readable. For XScale, fix a dodgy sequence while stepping. It was initializing a variable to a non-NULL value, then updating it to handle the step-over-active-breakpoint case, and then later testing for non-NULL to see if it should reverse that step-over-active logic. It should have done like ARM7/ARM9 does: init to NULL. Signed-off-by: David Brownell <dbrownell@users.sourceforge.net>
* ARM DPM: support adding/removing HW breakpointsDavid Brownell2010-02-211-38/+113
| | | | | | | | | | | | | | Generalize the core of watchpoint setup so that it can handle breakpoints too. Create breakpoint add/remove routines which will use that, and hook them up to target types which don't provide their own breakpoint support (nothing, yet). This suffices for hardware-only breakpoint support. The ARM11 code will be able to switch over to this without much trouble, since it doesn't yet handle software breakpoints. Switching Cortex-A8 will be a bit more involved. Signed-off-by: David Brownell <dbrownell@users.sourceforge.net>
* ARM11: per-core options should not be globalDavid Brownell2010-02-212-33/+44
| | | | | | | | | | Address some FIXME comments by getting rid of globals, moving per-core parameters in the existing per-core data structure. This will matter most whenever there are multiple ARM11 cores, e.g. ARM11 MPcore chips, but in general is just cleanup. Signed-off-by: David Brownell <dbrownell@users.sourceforge.net>
* ARMv7-M: start using "struct arm"David Brownell2010-02-215-9/+74
| | | | | | | | | | | | | | | | | | | | | | | | | | | This sets up a few of the core "struct arm" data structures so they can be used with ARMv7-M cores. Specifically, it: - defines new ARM core_modes to match the microcontroller modes (e.g. HANDLER not IRQ, and two types of thread mode); - Establishes a new microcontroller "core_type", which can be used to make sure v7-M (and v6-M) cores are handled right; - adds "struct arm" to "struct armv7m" and arranges for the target_to_armv7m() converter to use it; - sets up the arm.core_cache and arm.cpsr values - makes the Cortex-M3 code maintain arm.map and arm.core_mode. This is currently set up as a parallel data structure, primarily to minimize special cases for the semihosting support with microcontroller profile cores. Later patches can rip out the duplicative ARMv7-M support and start reusing core ARM code. Signed-off-by: David Brownell <dbrownell@users.sourceforge.net>
* Open the merge window for the 0.5.0 release cycle.David Brownell2010-02-213-69/+101
| | | | Signed-off-by: David Brownell <dbrownell@users.sourceforge.net>
* Label builds as OpenOCD v0.4.0David Brownell2010-02-211-1/+1
| | | | Signed-off-by: David Brownell <dbrownell@users.sourceforge.net>
* User's Guide mentions OS-specific installationDavid Brownell2010-02-212-2/+14
| | | | | | | | | | Specifically the Linux issue of needing "udev" rules, and MS-Windows needing driver configuration. Also, update the existing udev note to use the correct name of that rules file in the source tree. Signed-off-by: David Brownell <dbrownell@users.sourceforge.net>
* arm920t line length cleanupDavid Brownell2010-02-201-115/+247
| | | | | | | | | | | | The recent patch to fixbreakpoints and dcache handling added a bunch of overlong lines (80+ chars) ... shrink them, and do the same to a few lines which were already overlong. Also add a few FIXME comments to nudge (a) replacement of some magic numbers with opcode macros, which will be much better at showing what's actually going on, and (b) correct return codes. Signed-off-by: David Brownell <dbrownell@users.sourceforge.net>
* CSB337 board cleanup (quasi-regression)David Brownell2010-02-201-0/+2
| | | | | | | | Get rid of new nasty warning: NOTE! Severe performance degradation without fast memory access enabled... Signed-off-by: David Brownell <dbrownell@users.sourceforge.net>
* FreeBSD buildfixDavid Brownell2010-02-201-2/+2
| | | | | | | | | Fix an unused variable warning seen when building the parport driver under FreeBSD. Using information from Xiaofan Chen <xiaofanc@gmail.com> Signed-off-by: David Brownell <dbrownell@users.sourceforge.net>
* atm920t : fix breakpoints and data cache handlingMarc Pignat2010-02-191-17/+103
| | | | | | | | | Breakpoints did not work because the data cache was not flushed properly. As a bonus add capability to write to memory marked as read only by the MMU, which allows software breakpoints in such memory regions.
* ARM920T scanchain 15 comments/cleanupDavid Brownell2010-02-161-51/+112
| | | | | | | | | | | | | | | | | For folk who don't know the ARM920 JTAG interface very well, the two modes of scan chain 15 access to CP15 are confusing. Make those parts of the ARM920 code less opaque, by: - Adding comments referencing the relevant parts of the TRM, catching up to similar updates in the User's Guide. - Replacing magic numbers in physical access clients with symbolic equivalents. No functional change. Signed-off-by: David Brownell <dbrownell@users.sourceforge.net>
* gpl: fix GPL startup messageØyvind Harboe2010-02-152-2/+3
| | | | Signed-off-by: Øyvind Harboe <oyvind.harboe@zylin.com>
* LPC1768.cfg -- partial fixes for bogus reset-init handlerDavid Brownell2010-02-151-4/+4
| | | | | | | | | Cortex-M targets don't support ARM instructions. Leave the NVIC.VTOR setup alone, but comment how the whole routine looks like one big bug... Signed-off-by: David Brownell <dbrownell@users.sourceforge.net>
* fix crash with DSP563XXMathias Kuester2010-02-141-0/+25
| | | | | | | | | | | When a DSP563xx-aware GDB asks OpenOCD for target registers, the result should be a GDB with register data ... not an OpenOCD crash. (Note that mainline GDB doesn't currently support this core, so for now, this requires a GDB with FreeScale patches.) Signed-off-by: David Brownell <dbrownell@users.sourceforge.net>
* NEWS: mention removal of obsolete commandsDavid Brownell2010-02-131-0/+2
| | | | | | | | | | | | | Removed remaining support for various commands, like advice for migrating old-style TAP declarations. The documentation no longer describes them either ... so if users have been delaying config updates, they may need to consult older releases. ALL this stuff has been clearly marked as "do not use" for at least a year now, so anyone still using it hasn't been holding up their end. Signed-off-by: David Brownell <dbrownell@users.sourceforge.net>
* Restore "-dev" version suffix (0.4.0-rc2-dev)David Brownell2010-02-131-1/+1
| | | | Signed-off-by: David Brownell <dbrownell@users.sourceforge.net>
* v4.0-rc2 milestoneDavid Brownell2010-02-131-1/+1
| | | | Signed-off-by: David Brownell <dbrownell@users.sourceforge.net>
* STR9xpec: issue warning when unlocking deviceSpencer Oliver2010-02-121-0/+8
| | | | | | | Issue warning to user when unlocking or writing the option bytes. The new settings will not take effect until a target reset. Signed-off-by: Spencer Oliver <ntfreak@users.sourceforge.net>
* STM32x: issue warning when unlocking device (bug #16)Spencer Oliver2010-02-121-2/+6
| | | | | | | Issue warning to user when unlocking or writing the option bytes. The new settings will not take effect until a target reset. Signed-off-by: Spencer Oliver <ntfreak@users.sourceforge.net>
* arm720t: virt2phys callback addedØyvind Harboe2010-02-121-4/+14
| | | | | | | | This is a copy and paste of arm926ejs. Not tested, but ready for testing at least. There is a good chance that it will work if the generic armv4_5 fn's are robust enough... Signed-off-by: Øyvind Harboe <oyvind.harboe@zylin.com>
* arm920: add virt2phys fnMarc Pignat2010-02-121-3/+13
| | | | | | | Copy of the 926ejs function. I have tested it only using my rtems application (where virtual address mapping == physical). Signed-off-by: Øyvind Harboe <oyvind.harboe@zylin.com>
* target library: configuration files for openocd tested with Atmel SAM-ICE V6 ↵Viktar Palstsiuk2010-02-112-0/+119
| | | | | | JTAG. Signed-off-by: Øyvind Harboe <oyvind.harboe@zylin.com>
* User's Guide: "#" in filesystems names is badDavid Brownell2010-02-101-6/+14
| | | | | | | | Sometimes MS-Windows users try to use filesystem names which include the "#" character. That's generally unwise, since it begins Tcl comments. Signed-off-by: David Brownell <dbrownell@users.sourceforge.net>
* arm11: fix another infinite loop bugØyvind Harboe2010-02-101-4/+23
| | | | | | | | | | | | | reset init would get stuck in an infinite loop when e.g. khz was too high. Added timeout. This is a copy of paste of a number of such bugfixes in the arm11 code. Arm11 code reviewed for further such infinite loop bugs and I couldn't find any more. Xing fingers it's the last one... Signed-off-by: Øyvind Harboe <oyvind.harboe@zylin.com>
* User's Guide: clarify jtag_rclk adviceDavid Brownell2010-02-101-2/+4
| | | | | | | | | | Not all cores and boards support adaptive clocking, so qualify all advice to use it to depend on core and board support. It's primarily ARM cores which support this; and many of the newer ones (like Cortex-M series) don't. Signed-off-by: David Brownell <dbrownell@users.sourceforge.net>
* target: add todo in target_write_memory() about alignmentØyvind Harboe2010-02-091-2/+13
| | | | | | | target_write_buffer() does not align "buffer" in host memory passed to target_write_memory(). Signed-off-by: Øyvind Harboe <oyvind.harboe@zylin.com>
* str730.cfg: fix incorrect mem regionsSpencer Oliver2010-02-091-2/+2
| | | | | | - update str73x mem regions to correct values. Signed-off-by: Spencer Oliver <ntfreak@users.sourceforge.net>
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