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* rtos : compilation error on amd64Michel Jaouen2011-04-194-23/+23
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* Fix non cfi x16 nor flash connected to x8 bus. The ids in the table should ↵Alexandre Pereira da Silva2011-04-191-1/+7
| | | | be masked before comparison.
* Make the LPC32xx nand driver support up to 5 address cycles. This will only ↵Alexandre Pereira da Silva2011-04-191-1/+1
| | | | work in the SLC driver.
* Make the LPC32xx slc nand driver the defaultAlexandre Pereira da Silva2011-04-191-2/+2
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* jtag: clarify jtag->init() and jtag->quit() definitionsØyvind Harboe2011-04-192-7/+15
| | | | | | | | | only set jtag global pointer if jtag->init() succeeds. Less code, more clear what the rules are. Fix nit that error value from init() was not propagated unmodified. Signed-off-by: Øyvind Harboe <oyvind.harboe@zylin.com>
* RTOS Thread awareness support wipBroadcom Corporation (Evan Hunter)2011-04-1513-10/+1975
| | | | | | | | | | | - works on Cortex-M3 with ThreadX and FreeRTOS Compared to original patch a few nits were fixed: - remove stricmp usage - unsigned compare fix - printf formatting fixes - fixed a bug with overrunning a memory buffer allocated with malloc.
* pic32: update pic32mx flash driverSpencer Oliver2011-04-141-31/+67
| | | | | | | | | Update devices as per the latest programming manual. We now use the full DEVID to identify the target. Previously we used a 8bit id but that has now been changed in the manual. Signed-off-by: Spencer Oliver <ntfreak@users.sourceforge.net>
* Replace byte-access to memory with faster word-accessLuca Ellero2011-04-131-21/+69
| | | | | | | | | Freescale iMX53 doesn't seem to like unaligned accesses to his memory mapped registers. Anyway this patch makes dump_image/load_image 4X faster for every access through APB. Signed-off-by: Luca Ellero <lroluk@gmail.com>
* Add opcodes for load/store registers words immediate post-indexedLuca Ellero2011-04-131-0/+12
| | | | Signed-off-by: Luca Ellero <lroluk@gmail.com>
* Add preliminary support for Freescale iMX53Luca Ellero2011-04-131-0/+51
| | | | Signed-off-by: Luca Ellero <lroluk@gmail.com>
* Add the REV A tap id to the LPC3250 configurationAlexandre Pereira da Silva2011-04-131-1/+8
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* cortex_a :apb mem read/write working with mmu_onMichel JAOUEN2011-04-131-159/+171
| | | | | | Conflicts: src/target/cortex_a.c
* cortex_a : multiple target on the same dapMichel JAOUEN2011-04-132-0/+12
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* cortex_a : use dap ref from armv4_5commonMichel JAOUEN2011-04-131-18/+18
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* at91: add at91sam9263 chip register definitionJean-Christophe PLAGNIOL-VILLARD2011-04-093-4/+238
| | | | | | Signed-off-by: Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com> Cc: Nicolas Ferre <nicolas.ferre@atmel.com> Cc: Patrice Vilchez <patrice.vilchez@atmel.com>
* at91: add chip register definition and generic init supportJean-Christophe PLAGNIOL-VILLARD2011-04-099-0/+416
| | | | | | | | | | | | | | for - pio - pmc - rstc - wdt - sdramc - smc Signed-off-by: Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com> Cc: Nicolas Ferre <nicolas.ferre@atmel.com> Cc: Patrice Vilchez <patrice.vilchez@atmel.com>
* add at91sam9263-ek supportJean-Christophe PLAGNIOL-VILLARD2011-04-091-0/+63
| | | | | | Signed-off-by: Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com> Cc: Nicolas Ferre <nicolas.ferre@atmel.com> Cc: Patrice Vilchez <patrice.vilchez@atmel.com>
* add at91sam9261-ek supportJean-Christophe PLAGNIOL-VILLARD2011-04-091-0/+63
| | | | | | Signed-off-by: Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com> Cc: Nicolas Ferre <nicolas.ferre@atmel.com> Cc: Patrice Vilchez <patrice.vilchez@atmel.com>
* at91: add at91sam9261 chip register definitionJean-Christophe PLAGNIOL-VILLARD2011-04-092-0/+136
| | | | | | Signed-off-by: Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com> Cc: Nicolas Ferre <nicolas.ferre@atmel.com> Cc: Patrice Vilchez <patrice.vilchez@atmel.com>
* jlink: jlink_debug_buffer use inline function when _DEBUG_USB_COMMS_ not defineJean-Christophe PLAGNIOL-VILLARD2011-04-091-10/+4
| | | | | | Signed-off-by: Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com> Cc: Nicolas Ferre <nicolas.ferre@atmel.com> Cc: Patrice Vilchez <patrice.vilchez@atmel.com>
* Buffering for up to 64 bytes in USB Blaster.Ali Lown2011-04-081-12/+38
| | | | | Uses a global buffer. Add self to acknowledgements.
* Add support for LED to USB Blaster code.Ali Lown2011-04-081-0/+9
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* build: correctly use AC_LANG_PROGRAMSpencer Oliver2011-04-061-27/+20
| | | | | | | With newer versions of autoconf >= 2.68 we receive warnings about the incorrect use of AC_LANG_PROGRAM. This fixes those warnings. Signed-off-by: Spencer Oliver <ntfreak@users.sourceforge.net>
* cortex_a : implement jtag console for cortex_aMichel JAOUEN2011-04-061-46/+13
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* Added mips_ejtag_drscan_32_out() for optimization.Drasko DRASKOVIC2011-04-054-6/+22
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* Corrected waiting on PrAcc in wait_for_pracc_rw(). Added necessary check ↵Drasko DRASKOVIC2011-04-051-14/+42
| | | | that PrAcc is "1" before FASTDATA access.
* Added correct endianess treatment for big endian targets. Now it is possible ↵Drasko DRASKOVIC2011-04-051-6/+72
| | | | to use mips_m4k_write_memory() and mips_m4k_read_memory() to correctly set-up SDRAM, as well as bulk data write, which already handled endianess well. Also added correct endianess manipulation in case of fallback from erroneus bulk write to simple write (to avoid byte swapping two times).
* pandaboard: use new -dbgbase option to workaround broken ROM tableØyvind Harboe2011-04-021-1/+14
| | | | Signed-off-by: Øyvind Harboe <oyvind.harboe@zylin.com>
* cortex_a: delete dbgbase hack vestigesØyvind Harboe2011-04-011-15/+0
| | | | Signed-off-by: Øyvind Harboe <oyvind.harboe@zylin.com>
* cortex_a: fix gaffe in first implementation of -dbgbaseMichel JAOUEN2011-04-011-9/+9
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* Merge remote branch 'origin/master' into HEADØyvind Harboe2011-04-0136-199/+196
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| * cortex_a: remove broken dbgbase patchup codeØyvind Harboe2011-04-011-25/+0
| | | | | | | | | | | | | | | | | | | | the patchup code would get false positives when checking whether a dbgbase had to be corrected. The solution is to have autodetect default, with manual override in scripts. Signed-off-by: Øyvind Harboe <oyvind.harboe@zylin.com>
| * Added s19 to (fast_)load_image documentation to match the online help.Phil2011-04-011-3/+3
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| * mips: illustrates how to improve performanceØyvind Harboe2011-04-014-14/+21
| | | | | | | | | | | | | | Do not require unecessary roundtrips for clocking out data. Signed-off-by: Øyvind Harboe <oyvind.harboe@zylin.com>
| * types: write memory now uses constØyvind Harboe2011-04-0130-85/+85
| | | | | | | | Signed-off-by: Øyvind Harboe <oyvind.harboe@zylin.com>
| * mips: delete kludgy code that modifies data sent to write_memory()Øyvind Harboe2011-03-311-1/+16
| | | | | | | | | | | | | | | | Could this cause confusion as data sent to write would be flipped and then if the caller subsequently used the data, e.g. a compare mismatch might happen? Signed-off-by: Øyvind Harboe <oyvind.harboe@zylin.com>
| * startup: fix bugs in cleanup upon errors during startupØyvind Harboe2011-03-311-26/+33
| | | | | | | | | | | | Importantly adapter cleanup will now happen upon startup failure. Signed-off-by: Øyvind Harboe <oyvind.harboe@zylin.com>
| * mips: mips32_pracc_exec error propagation fixesØyvind Harboe2011-03-312-29/+21
| | | | | | | | Signed-off-by: Øyvind Harboe <oyvind.harboe@zylin.com>
| * mips: mips_ejtag_get_impcode error propagation addedØyvind Harboe2011-03-312-2/+7
| | | | | | | | Signed-off-by: Øyvind Harboe <oyvind.harboe@zylin.com>
| * mips: fix mips_ejtag_set_instr error handlingØyvind Harboe2011-03-312-14/+10
| | | | | | | | | | | | this fn does not fail, it queues data. Signed-off-by: Øyvind Harboe <oyvind.harboe@zylin.com>
* | mips: fix gaffe in previous commitØyvind Harboe2011-04-011-1/+4
|/ | | | | | | | accidentally invoked return jtag_execute_queue() in the middle of a fn. Hmm.... I would have expected gcc or at least lint to catch this. Signed-off-by: Øyvind Harboe <oyvind.harboe@zylin.com>
* mips: fix error handling for jtag_execute_queue()Øyvind Harboe2011-03-312-8/+8
| | | | Signed-off-by: Øyvind Harboe <oyvind.harboe@zylin.com>
* xscale: fix gaffe in phys writeØyvind Harboe2011-03-311-1/+1
| | | | | | | it would *read* instead of *write* to memory when the MMU was disabled. Signed-off-by: Øyvind Harboe <oyvind.harboe@zylin.com>
* cortex-a: use -dbgbase optionØyvind Harboe2011-03-311-5/+12
| | | | Signed-off-by: Øyvind Harboe <oyvind.harboe@zylin.com>
* target: add -dbgbase option to target configurationØyvind Harboe2011-03-312-0/+23
| | | | | | | | | Really a Cortex-A specific option, but there is no system in place to support target specific options currently and there has been no need for such a system until now. Signed-off-by: Øyvind Harboe <oyvind.harboe@zylin.com>
* at91sam3: Modified cidr comparisson to ignore version bitsOlivier Schonken2011-03-301-1/+2
| | | | | | production processor versions increment, thus the version bits should be ignored for future proofing. e.g. Engineering sample version == 0x00, production version 0x01
* docs: add HACKING file to help users get started with patchesØyvind Harboe2011-03-301-0/+49
| | | | Signed-off-by: Øyvind Harboe <oyvind.harboe@zylin.com>
* Clarify LPC32XX address cycles messageAlexandre Pereira da Silva2011-03-301-1/+1
| | | | | | | | | Hi, This is a more descriptive message about LPC32XX error, when the nand chip needs 5 address cycles. Thanks.
* Add Micron 2GiB nandAlexandre Pereira da Silva2011-03-301-0/+2
| | | | | | | | Hi, This will add support for a new nand chip device. Thanks.
* bugfix for step <address> mips_m4kAndrew Lyon2011-03-291-0/+4
| | | | | | | | | The patch below fixes step <address> on mips_m4k. Spencer Oliver <spen@spen-soft.co.uk>: The current code is used on all other arch's - is there a underlying issue with those aswell ?
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