| Commit message (Collapse) | Author | Age | Files | Lines | ||
|---|---|---|---|---|---|---|
| ... | ||||||
| * | - merged several changes from XScale | drath | 2007-01-31 | 1 | -0/+53 | |
| | | | | | | | | | - complain about identify_chain scan with all bits one (jtag communication problem) - add 0x80000 as a valid size for lpc2000_v2 flash banks (previously only the user accessible 0x7d000 were valid) git-svn-id: svn://svn.berlios.de/openocd/trunk@129 b42882b7-edfa-0310-969c-e2dbd0fdcd60 | |||||
| * | - added a PLD (programmable logic device) subsystem for FPGA, CPLD etc. ↵ | drath | 2006-11-22 | 1 | -0/+507 | |
| configuration - added support for loading .bit files into Xilinx Virtex-II devices - added support for the Gateworks GW16012 JTAG dongle - merged CFI fixes from XScale branch - a few minor fixes git-svn-id: svn://svn.berlios.de/openocd/trunk@116 b42882b7-edfa-0310-969c-e2dbd0fdcd60 | ||||||
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index : openocd+libswd.git | |
| Unnamed repository; edit this file 'description' to name the repository. | Trygve Laugstøl |
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