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* Finish transforming 'u32' to 'uint32_t'.zwelch2009-06-181-1/+1
| | | | | | | | - Replace '\([^_]\)u32' with '\1uint32_t'. - Replace '^u32' with 'uint32_t'. git-svn-id: svn://svn.berlios.de/openocd/trunk@2281 b42882b7-edfa-0310-969c-e2dbd0fdcd60
* Transform 'u8' to 'uint8_t'zwelch2009-06-181-6/+6
| | | | | | | | - Replace '\([^_]\)u8' with '\1uint8_t'. - Replace '^u8' with 'uint8_t'. git-svn-id: svn://svn.berlios.de/openocd/trunk@2276 b42882b7-edfa-0310-969c-e2dbd0fdcd60
* - added a PLD (programmable logic device) subsystem for FPGA, CPLD etc. ↵drath2006-11-221-0/+38
configuration - added support for loading .bit files into Xilinx Virtex-II devices - added support for the Gateworks GW16012 JTAG dongle - merged CFI fixes from XScale branch - a few minor fixes git-svn-id: svn://svn.berlios.de/openocd/trunk@116 b42882b7-edfa-0310-969c-e2dbd0fdcd60
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