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* target: create/use register_cache_invalidate()David Brownell2009-11-191-16/+0
| | | | | | | | | | | | | | | Create a generic register_cache_invalidate(), and use it to replace three all-but-identical core-specific routines: - armv4_5_invalidate_core_regs() - armv7m_invalidate_core_regs - mips32_invalidate_core_regs() too. Make cache->num_regs be unsigned, avoiding various errors. Net code shrink and simplification. Signed-off-by: David Brownell <dbrownell@users.sourceforge.net>
* ARM: remove per-register mallocDavid Brownell2009-11-191-1/+1
| | | | | | | Just pre-allocate memory for the cached register value. Shrinks heap overhead; increases locality-of-reference. Signed-off-by: David Brownell <dbrownell@users.sourceforge.net>
* ARM: streamline register initDavid Brownell2009-11-191-74/+88
| | | | | | | | | Combine register names with other per-register data into a single template structure. This saves space, and makes it easier to change how registers get handled (by shrinking the number of places that care about cache indices). Signed-off-by: David Brownell <dbrownell@users.sourceforge.net>
* ARMv7-A: use standard ARM core statesDavid Brownell2009-11-191-1/+1
| | | | | | | | | | | | | | | We don't want an ARMv7-specific core state enumeration just to add ThumbEE state. Update the generic stuff to handle that, and replace the V7-specific bits with it. For Cortex-A8: on debug entry, check both the T and J bits instead of just the T bit. When the J bit is set, set the right state and warn appropriately. (And while we're at it, move the generic arm struct to the front of the v7a structure, for somewhat better code generation.) Signed-off-by: David Brownell <dbrownell@users.sourceforge.net>
* ARM: rework "arm reg" output for new modeDavid Brownell2009-11-181-35/+113
| | | | | | | | | | | | | | | | Change the layout to show the "Secure Monitor" registers too, when they're present. Instead of lining registers for each of six (or seven) modes up in adjacent vertical columns, display each mode's registers (or shadows) in a single block, avoiding duplicate value displays. This also lets us shrink the line length to fits in standard 80 character lines ... six or seven 18-character columns can't fit. Relabel "r13" as "sp", so it's more meaningful. Signed-off-by: David Brownell <dbrownell@users.sourceforge.net>
* ARM: add a default full_context() methodDavid Brownell2009-11-181-3/+24
| | | | | | | | | | | | If the core doesn't provide an optimized version of this method, provide one without core-specific optimizations. Use this to make Cortex-A8 support the "arm reg" command. Related: make the two register access methods properly static, have the "set" log a "not halted" error too, and make sure that the "valid" flag is set on successful reads. Signed-off-by: David Brownell <dbrownell@users.sourceforge.net>
* ARM: setup "secure monitor mode" shadow regsDavid Brownell2009-11-181-19/+50
| | | | | | | | | | | | | Teach the "armv4_5" register code to understand about the secure monitor mode: - Add the other three shadowed registers to the arrays - Support another internal mode number (sigh) in mappings - Catch malloc/calloc failures building that register cache This should kick in for Cortex-A8 and ARM1176. Signed-off-by: David Brownell <dbrownell@users.sourceforge.net>
* ARM: add "core_type" field to "struct arm"David Brownell2009-11-181-0/+3
| | | | | | | | | | It's used to flag cores with the "TrustZone" extension, and is used in subsequent patches to set up support for the registers shadowed by its new secure monitor mode. The ARM1176 and Cortex-A8 both support this new mode. Signed-off-by: David Brownell <dbrownell@users.sourceforge.net>
* ARM: add is_arm_mode()David Brownell2009-11-171-12/+23
| | | | | | | | | | | | | | | | | | Add a new is_arm_mode() predicate, and use it to replace almost all calls to current armv4_5_mode_to_number(). Eventually those internal mode numbers should vanish... along with their siblings in the armv7a.c file. Remove a handful of superfluous checks ... e.g. the mode number was just initialized, or (debug entry methods) already validated. Move one of the macros using internal mode numbers into the only file which uses that macro. Make the tables manipulated with those numbers be read-only and, where possible, static so they're not confused with part of the generic ARM interface. Signed-off-by: David Brownell <dbrownell@users.sourceforge.net>
* ARM: add arm_mode_name()David Brownell2009-11-171-7/+58
| | | | | | | | | | | | | | | Add and use arm_mode_name() to map from PSR bits to user meaningful names. It uses a new table which, later, can be used to hold other mode-coupled data. Add definitions for the "Secure Monitor" mode, as seen on some ARM11 cores (like ARM1176) and on Cortex-A8. The previous mode name scheme didn't understand that mode. Remove the old mechanism ... there were two copies, caused by Cortex-A8 needing to add "Secure Monitor" mode support. Signed-off-by: David Brownell <dbrownell@users.sourceforge.net>
* ARM: only use one set of dummy FPA registersDavid Brownell2009-11-171-17/+28
| | | | | | | | | | | | | | | | All ARM cores need to provide obsolete FPA registers in their GDB register dumps. (Even though cores with floating point support now generally use some version of VFP...) Clean up that support a bit by sharing the same dummy registers, and removing the duplicate copies. Eventually we shouldn't need to export those dummies. (This makes the ARMv7-M support include the armv4_5 header, and cleans up related #includes, but doesn't yet use anything from there except those dummies.) Signed-off-by: David Brownell <dbrownell@users.sourceforge.net>
* command_handler: change 'cmd_ctx' to CMD_CTXZachary T Welch2009-11-171-14/+14
| | | | Convert all command handler 'cmd_ctx' parameter usage with CMD_CTX.
* command_handler: change 'args' to CMD_ARGVZachary T Welch2009-11-171-5/+5
| | | | | This patch converts all instances of 'args' in COMMAND_HANDLER routines to use CMD_ARGV macro.
* command_handler: change to 'argc' to CMD_ARGCZachary T Welch2009-11-171-2/+2
| | | | | This patch converts all instances of 'argc' in COMMAND_HANDLER routines to use CMD_ARGC.
* target: simplify register get/set opsDavid Brownell2009-11-171-8/+6
| | | | | | | | | | | No need to indirect from registered integers to pointers. Just stash the pointers directly in the register struct, and don't even bother registering. This is a small code shrink, speeds register access just a smidgeon, and gets rid of another rude exit() path. Signed-off-by: David Brownell <dbrownell@users.sourceforge.net>
* ARMv4/ARMv5: no exit() callsDavid Brownell2009-11-161-6/+8
| | | | Signed-off-by: David Brownell <dbrownell@users.sourceforge.net>
* ARM11: register (most) standard ARM commandsDavid Brownell2009-11-161-1/+8
| | | | | | | Have ARM11 register the "standard" ARM commands. For now, only disassembly really works. Signed-off-by: David Brownell <dbrownell@users.sourceforge.net>
* ARM: "armv4_5" command prefix becomes "arm"David Brownell2009-11-161-9/+9
| | | | | | | | | | Rename the "armv4_5" command prefix to straight "arm" so it makes more sense for newer cores. Add a simple compatibility script. Make sure all the commands give the same "not an ARM" diagnostic message (and fail properly) when called against non-ARM targets. Signed-off-by: David Brownell <dbrownell@users.sourceforge.net>
* ARM: standard disassembler uses Thumb2 entryDavid Brownell2009-11-161-36/+32
| | | | | | | | | | | | | | | | | Tweak "standard" ARM disassembler diagnostics to fail if the target is not "an ARM" (vs. not "an ARMV4/5"), so it makes more sense for cores inheriting this as the "generic" disassembler. Also, to use the Thumb2 entry instead of the original Thumb entry. This makes it work better for both newer cores (which support those added instructions) and for BL and BLX instructions on older cores. (Those instructions are 32-bits, which requires curious state-aware code to go through a 16-bit decode interface...) Plus minor cleanups, notably to have fewer exit paths and to make sure they all return failure codes. Signed-off-by: David Brownell <dbrownell@users.sourceforge.net>
* ARM: move mode functions out of headerDavid Brownell2009-11-161-2/+52
| | | | | | | | | They're really too big to inline, at least for code that's not in any performance-critical loops. Also move the associated string table to the rodata section. Signed-off-by: David Brownell <dbrownell@users.sourceforge.net>
* target: less implicit inclusion of "etm.h"David Brownell2009-11-161-0/+1
| | | | | | | Don't include it in more headers than necessary; just use it in the few files that actually need it. Signed-off-by: David Brownell <dbrownell@users.sourceforge.net>
* move ARRAY_SIZE macro to types.hZachary T Welch2009-11-161-2/+2
| | | | | | | | The ARRAY_SIZE macro was defined in several target files, so move it to types.h. This patch also removes two other identical macros: DIM (from jtag.h) and asizeof (from arm11.h).
* target: no implicit #includes of "register.h"David Brownell2009-11-161-0/+1
| | | | | | | | | | | | Same deal: "register.h" got needlessly included all over the place because of being in a few widely included headers. So take it out of the header files which included it, and put it in files which use it ... reduce needless interdependencies. Also, don't need that extra "types.h" inclusion. Signed-off-by: David Brownell <dbrownell@users.sourceforge.net>
* target: don't implicitly include "algorithm.h"David Brownell2009-11-161-0/+1
| | | | | | | | | | | | | | Most files in the tree seem to have ended up including this, and *quite* needlessly ... only code implementing or using downloadable algorithms actually needs these declarations. So take it out of the header files which included it, and put it in files which use it ... reduce needless interdependencies. Also: "algorithm.h" doesn't need to include "types.h" again; it already comes from a different header. Signed-off-by: David Brownell <dbrownell@users.sourceforge.net>
* target: don't implicitly include "breakpoint.h"David Brownell2009-11-161-0/+1
| | | | | | | | | | | Most files in the tree seem to have ended up including this, and *quite* needlessly ... only code implementing or using breakpoints actually needs these declarations. So take it out of the header files which included it, and put it in files which use it ... reduce needless interdependencies. Signed-off-by: David Brownell <dbrownell@users.sourceforge.net>
* ARM: memory utils aren't ARM7/ARM9 dependentDavid Brownell2009-11-151-0/+170
| | | | | | | | | | | | | | | | The arm7_9_checksum_memory() and arm7_9_blank_check_memory() routines are not actually specific to the ARM7 and ARM9 core generations ... they can work for any core which can run algorithms using basic ARM (not Thumb) instructions. Rename them; move the declarations to a more generic site; likewise move the code (and tidy it a bit in the process). NOTE: the blank_check() method falsely returned a success status (0) on one error path, when the algorithm failed. Fixed this bug. Signed-off-by: David Brownell <dbrownell@users.sourceforge.net>
* target: remove unused "bitfield" infrastructureDavid Brownell2009-11-131-20/+14
| | | | | | | | | | | | | | We have too many different registers, and too many version and context dependent interpretations, for this type of bitfield management to be scalable. (Anyone who really wants bitfield interpretation *can* do that in Tcl code...) There are ... quite a few copies of the same ARM dummy registers. There should eventually be one copy; this many is craziness. Signed-off-by: David Brownell <dbrownell@users.sourceforge.net>
* command_t -> struct commandZachary T Welch2009-11-131-1/+1
| | | | Remove misleading typedef and redundant suffix from struct command.
* command_context_t -> struct command_contextZachary T Welch2009-11-131-1/+1
| | | | Remove misleading typedef and redundant suffix from struct command_context.
* target_t -> struct targetZachary T Welch2009-11-131-13/+13
| | | | Remove misleading typedef and redundant suffix from struct target.
* reg_t -> struct regZachary T Welch2009-11-131-9/+9
| | | | Remove misleading typedef and redundant suffix from struct reg.
* armv4_5_common_t -> struct armZachary T Welch2009-11-131-2/+2
| | | | Remove misleading typedef and just use struct arm.
* arm_instruction_t -> struct arm_instructionZachary T Welch2009-11-131-1/+1
| | | | Remove misleading typedef and redundant suffix from struct arm_instruction.
* reg_cache_t -> struct reg_cacheZachary T Welch2009-11-131-2/+2
| | | | Remove misleading typedef and redundant suffix from struct reg_cache.
* bitfield_desc_t -> struct bitfield_descZachary T Welch2009-11-131-1/+1
| | | | Remove misleading typedef and redundant suffix from struct bitfield_desc.
* armv4_5_core_reg_t -> struct armv4_5_core_regZachary T Welch2009-11-131-4/+4
| | | | Remove misleading typedef and redundant suffix from struct armv4_5_core_reg.
* armv4_5_algorithm_t -> struct armv4_5_algorithmZachary T Welch2009-11-131-1/+1
| | | | Remove misleading typedef and redundant suffix from struct armv4_5_algorithm.
* reg_param_t -> struct reg_paramZachary T Welch2009-11-131-2/+2
| | | | Remove misleading typedef and redundant suffix from struct reg_param.
* mem_param_t -> struct mem_paramZachary T Welch2009-11-131-2/+2
| | | | Remove misleading typedef and redundant suffix from struct mem_param.
* use COMMAND_HANDLER macro to define all commandsZachary T Welch2009-11-131-5/+3
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* ARM: other code uses the new inheritance/nesting schemeDavid Brownell2009-11-051-9/+9
| | | | | | | Remove most remaining uses of target->arch_info from ARM infrastructure, where it hasn't already been updated. Signed-off-by: David Brownell <dbrownell@users.sourceforge.net>
* Improve armv4_5 command argument parsing.Zachary T Welch2009-11-051-2/+2
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* David Brownell <david-b@pacbell.net> oharboe2009-09-091-4/+17
| | | | | | | | | | | | | | | | | Optionally shave time off the armv4_5 run_algorithm() code: let them terminate using software breakpoints, avoiding roundtrips to manage hardware ones. Enable this by using BKPT to terminate execution instead of "branch to here" loops. Then pass zero as the exit address, except when running on an ARMv4 core. ARM7TDMI, ARM9TDMI, and derived cores now set a flag saying they're ARMv4. Use that mechanism in arm_nandwrite(), for about 3% speedup on a DaVinci ARM926 core; not huge, but it helps. Some other algorithms could use this too (mostly flavors of flash operation). git-svn-id: svn://svn.berlios.de/openocd/trunk@2680 b42882b7-edfa-0310-969c-e2dbd0fdcd60
* David Brownell <david-b@pacbell.net> Tweak disassembly commands:oharboe2009-08-251-16/+39
| | | | | | | | | | | | | | | | | | For ARMv4/ARMv5: - better command parameter error checking - don't require an instruction count; default to one - recognize thumb function addresses - make function static - shorten some too-long lines For Cortex-M3: - don't require an instruction count; default to one With the relevant doc updates. --- Nyet done: invoke the thumb2 disassembler on v4/v5, to better handle branch instructions. git-svn-id: svn://svn.berlios.de/openocd/trunk@2624 b42882b7-edfa-0310-969c-e2dbd0fdcd60
* Remove whitespace at end of lines, step 1.zwelch2009-06-231-3/+3
| | | | | | | - Replace '\s*$' with ''. git-svn-id: svn://svn.berlios.de/openocd/trunk@2379 b42882b7-edfa-0310-969c-e2dbd0fdcd60
* Remove whitespace that occurs before ')'.zwelch2009-06-231-1/+1
| | | | | | | - Replace '[ \t]*[)]' with ')'. git-svn-id: svn://svn.berlios.de/openocd/trunk@2377 b42882b7-edfa-0310-969c-e2dbd0fdcd60
* Remove whitespace that occurs after '('.zwelch2009-06-231-1/+1
| | | | | | | - Replace '([ \t]*' with '('. git-svn-id: svn://svn.berlios.de/openocd/trunk@2376 b42882b7-edfa-0310-969c-e2dbd0fdcd60
* - Fixes '[|]' whitespacezwelch2009-06-231-1/+1
| | | | | | | | | | - Replace ')\([|]\)(' with ') \1 ('. - Replace ')\([|]\)\(\w\)' with ') \1 \2'. - Replace '\(\w\)\([|]\)(' with '\1 \2 ('. - Replace '\(\w\)\([|]\)\(\w\)' with '\1 \2 \3'. git-svn-id: svn://svn.berlios.de/openocd/trunk@2374 b42882b7-edfa-0310-969c-e2dbd0fdcd60
* - Fixes '+' whitespacezwelch2009-06-231-1/+1
| | | | | | | | | | - Replace ')\(+\)(' with ') \1 ('. - Replace ')\(+\)\(\w\)' with ') \1 \2'. - Replace '\(\w\)\(+\)(' with '\1 \2 ('. - Replace '\(\w\)\(+\)\(\w\)' with '\1 \2 \3'. git-svn-id: svn://svn.berlios.de/openocd/trunk@2373 b42882b7-edfa-0310-969c-e2dbd0fdcd60
* - Fixes '=' whitespacezwelch2009-06-231-3/+3
| | | | | | | | | - Replace ')\(=\)\(\w\)' with ') \1 \2'. - Replace '\(\w\)\(=\)(' with '\1 \2 ('. - Replace '\(\w\)\(=\)\(\w\)' with '\1 \2 \3'. git-svn-id: svn://svn.berlios.de/openocd/trunk@2372 b42882b7-edfa-0310-969c-e2dbd0fdcd60
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