summaryrefslogtreecommitdiff
path: root/src/target/armv7m.c
Commit message (Collapse)AuthorAgeFilesLines
* ARMv7-M: use command handler for "dap baseaddr".David Brownell2010-01-291-30/+1
| | | | | | | | | | Make the ARMv7-M DAP code reuse the command handler for "dap baseaddr". For some reason, this DAP command wasn't converted earlier. This is a code shrink and simplification; it also removes a needless transport dependency on JTAG. Signed-off-by: David Brownell <dbrownell@users.sourceforge.net>
* ARMV7M: handle bkpt instruction on resume/stepSpencer Oliver2010-01-201-0/+38
| | | | | | | | | | Skip over a bkpt instruction if found on resume/step. Only software breakpoints known to OpenOCD are currently handled. So this handles the special case of either a user added bkpt or library added, eg. semi-hosting support. Signed-off-by: Spencer Oliver <ntfreak@users.sourceforge.net>
* ARMv7: help/usage updatesDavid Brownell2010-01-071-13/+22
| | | | | | | | | | | | | | | | | | Provide helptext which was sometimes missing; update some of it to be more accurate. Usage syntax messages have the same EBNF as the User's Guide; there should be no angle brackets in either place. Don't use "&function"; functions are like arrays, their address is their name. Shrink some overlong lines, remove some empties. Add a couple comments about things that should change: those extra TCK cycles for MEM-AP reads are in the wrong place (that might explain some problems we've seen); the DAP command tables should be shared, not copied. Signed-off-by: David Brownell <dbrownell@users.sourceforge.net>
* ARMv7-M: use AP_REG_* symbolDavid Brownell2010-01-041-1/+6
| | | | Signed-off-by: David Brownell <dbrownell@users.sourceforge.net>
* streamline and document helptext mode displaysDavid Brownell2010-01-021-1/+1
| | | | | | | | | | | | | | | | | | | Most commands are usable only at runtime; so don't bother saying that, it's noise. Moreover, tokens like EXEC are cryptic. Be more clear: highlight only the commands which may (also) be used during the config stage, thus matching the docs more closely. There are - Configuration commands (per documentation) - And also some commands that valid at *any* time. Update the docs to note that "help" now shows this mode info. This also highlighted a few mistakes in command configuration, mostly commands listed as "valid at any time" which shouldn't have been. This just fixes ones I noted when sanity testing. Signed-off-by: David Brownell <dbrownell@users.sourceforge.net>
* target: add debug_reason_name()David Brownell2009-12-071-2/+1
| | | | | | | | Provide and use debug_reason_name() instead of expecting targets to call Jim_Nvp_value2name_simple(). Less dependency on Jim, and the code becomes more clear too. Signed-off-by: David Brownell <dbrownell@users.sourceforge.net>
* use ARRAY_SIZE macroZachary T Welch2009-11-251-2/+2
| | | | | Search and destroy lingering cases where the ARRAY_SIZE macro should be used to convey more intrinsic meaning in the OpenOCD code.
* remove target_type register_command callbackZachary T Welch2009-11-241-6/+1
| | | | | | Uses chaining of command_registration structures to eliminate all target_type register_callback routines. Exports the command_handler registration arrays for those target types that are used by others.
* armv7m: use register_commands()Zachary T Welch2009-11-241-28/+48
|
* use COMMAND_REGISTER macroZachary T Welch2009-11-241-6/+6
| | | | | Replaces direct calls to register_command() with a macro, to allow its parameters to be changed and callers updated in phases.
* target: create/use register_cache_invalidate()David Brownell2009-11-191-15/+0
| | | | | | | | | | | | | | | Create a generic register_cache_invalidate(), and use it to replace three all-but-identical core-specific routines: - armv4_5_invalidate_core_regs() - armv7m_invalidate_core_regs - mips32_invalidate_core_regs() too. Make cache->num_regs be unsigned, avoiding various errors. Net code shrink and simplification. Signed-off-by: David Brownell <dbrownell@users.sourceforge.net>
* ARM: only use one set of dummy FPA registersDavid Brownell2009-11-171-35/+2
| | | | | | | | | | | | | | | | All ARM cores need to provide obsolete FPA registers in their GDB register dumps. (Even though cores with floating point support now generally use some version of VFP...) Clean up that support a bit by sharing the same dummy registers, and removing the duplicate copies. Eventually we shouldn't need to export those dummies. (This makes the ARMv7-M support include the armv4_5 header, and cleans up related #includes, but doesn't yet use anything from there except those dummies.) Signed-off-by: David Brownell <dbrownell@users.sourceforge.net>
* command_handler: change 'cmd_ctx' to CMD_CTXZachary T Welch2009-11-171-7/+7
| | | | Convert all command handler 'cmd_ctx' parameter usage with CMD_CTX.
* command_handler: change 'args' to CMD_ARGVZachary T Welch2009-11-171-2/+2
| | | | | This patch converts all instances of 'args' in COMMAND_HANDLER routines to use CMD_ARGV macro.
* command_handler: change to 'argc' to CMD_ARGCZachary T Welch2009-11-171-2/+2
| | | | | This patch converts all instances of 'argc' in COMMAND_HANDLER routines to use CMD_ARGC.
* target: simplify register get/set opsDavid Brownell2009-11-171-11/+5
| | | | | | | | | | | No need to indirect from registered integers to pointers. Just stash the pointers directly in the register struct, and don't even bother registering. This is a small code shrink, speeds register access just a smidgeon, and gets rid of another rude exit() path. Signed-off-by: David Brownell <dbrownell@users.sourceforge.net>
* ARMv7-M: no exit() callsDavid Brownell2009-11-161-4/+4
| | | | Signed-off-by: David Brownell <dbrownell@users.sourceforge.net>
* move ARRAY_SIZE macro to types.hZachary T Welch2009-11-161-9/+6
| | | | | | | | The ARRAY_SIZE macro was defined in several target files, so move it to types.h. This patch also removes two other identical macros: DIM (from jtag.h) and asizeof (from arm11.h).
* armv7m: make core reg read/write use unsignedZachary T Welch2009-11-161-4/+4
| | | | | | Eliminate redundant check that gets covered by using unsigned type. Created to eliminate noise from subsequent patches, but this kind of conversion will be beneficial in similar ways throughout the tree.
* #include "target.h" less wildlyDavid Brownell2009-11-161-0/+1
| | | | | | | | | Don't include "target.h" from more headers than necessary. This avoids needless interdependencies and duplicated include paths. Don't needlessly include it in source files, either. Signed-off-by: David Brownell <dbrownell@users.sourceforge.net>
* target: no implicit #includes of "register.h"David Brownell2009-11-161-0/+1
| | | | | | | | | | | | Same deal: "register.h" got needlessly included all over the place because of being in a few widely included headers. So take it out of the header files which included it, and put it in files which use it ... reduce needless interdependencies. Also, don't need that extra "types.h" inclusion. Signed-off-by: David Brownell <dbrownell@users.sourceforge.net>
* target: don't implicitly include "algorithm.h"David Brownell2009-11-161-0/+1
| | | | | | | | | | | | | | Most files in the tree seem to have ended up including this, and *quite* needlessly ... only code implementing or using downloadable algorithms actually needs these declarations. So take it out of the header files which included it, and put it in files which use it ... reduce needless interdependencies. Also: "algorithm.h" doesn't need to include "types.h" again; it already comes from a different header. Signed-off-by: David Brownell <dbrownell@users.sourceforge.net>
* target: don't implicitly include "breakpoint.h"David Brownell2009-11-161-0/+1
| | | | | | | | | | | Most files in the tree seem to have ended up including this, and *quite* needlessly ... only code implementing or using breakpoints actually needs these declarations. So take it out of the header files which included it, and put it in files which use it ... reduce needless interdependencies. Signed-off-by: David Brownell <dbrownell@users.sourceforge.net>
* target: remove unused "bitfield" infrastructureDavid Brownell2009-11-131-9/+26
| | | | | | | | | | | | | | We have too many different registers, and too many version and context dependent interpretations, for this type of bitfield management to be scalable. (Anyone who really wants bitfield interpretation *can* do that in Tcl code...) There are ... quite a few copies of the same ARM dummy registers. There should eventually be one copy; this many is craziness. Signed-off-by: David Brownell <dbrownell@users.sourceforge.net>
* command_t -> struct commandZachary T Welch2009-11-131-1/+1
| | | | Remove misleading typedef and redundant suffix from struct command.
* command_context_t -> struct command_contextZachary T Welch2009-11-131-1/+1
| | | | Remove misleading typedef and redundant suffix from struct command_context.
* target_t -> struct targetZachary T Welch2009-11-131-19/+19
| | | | Remove misleading typedef and redundant suffix from struct target.
* reg_t -> struct regZachary T Welch2009-11-131-10/+10
| | | | Remove misleading typedef and redundant suffix from struct reg.
* working_area_t -> struct working_areaZachary T Welch2009-11-131-2/+2
| | | | Remove misleading typedef and redundant suffix from struct working_area.
* reg_cache_t -> struct reg_cacheZachary T Welch2009-11-131-3/+3
| | | | Remove misleading typedef and redundant suffix from struct reg_cache.
* armv7m_core_reg_t -> struct armv7m_core_regZachary T Welch2009-11-131-5/+5
| | | | Remove misleading typedef and redundant suffix from struct armv7m_core_reg.
* armv7m_algorithm_t -> struct armv7m_algorithmZachary T Welch2009-11-131-3/+3
| | | | Remove misleading typedef and redundant suffix from struct armv7m_algorithm.
* armv7m_common_t -> struct armv7m_commonZachary T Welch2009-11-131-16/+16
| | | | Remove misleading typedef and redundant suffix from struct armv7m_common.
* swjdp_common_t -> struct swjdp_commonZachary T Welch2009-11-131-5/+5
| | | | Remove misleading typedef and redundant suffix from struct swjdp_common.
* reg_param_t -> struct reg_paramZachary T Welch2009-11-131-3/+3
| | | | Remove misleading typedef and redundant suffix from struct reg_param.
* mem_param_t -> struct mem_paramZachary T Welch2009-11-131-1/+1
| | | | Remove misleading typedef and redundant suffix from struct mem_param.
* arm_adi,armv7[am]: use COMMAND_HELPER for helpersZachary T Welch2009-11-131-3/+3
| | | | | Rewrites the dap_* command helpers to use the COMMAND_HELPER paradigm. Uses CALL_COMMAND_HELPER to hide inherited calling conventions.
* use COMMAND_HANDLER macro to define all commandsZachary T Welch2009-11-131-10/+5
|
* Cortex-M3: use the new inheritance/nesting schemeDavid Brownell2009-11-051-27/+25
| | | | | | | | | | | | Use new target_to_cm3() and target_to_armv7m() inlines, instead of a series of x->arch_info conversions. Remove arch_info, since nothing uses it. Also fix an omission: the Cortex-M3 commands didn't verify that they were operating on that kind of target. Add comment about the ARMv7M version of that omission. Signed-off-by: David Brownell <dbrownell@users.sourceforge.net>
* Improve armv7m command argument parsing.Zachary T Welch2009-11-051-11/+20
|
* ARMv7M: add docs, remove exportsDavid Brownell2009-11-051-28/+62
| | | | | | | | | | | | Add Doxygen for the exported ARMv7-M interfaces. Make the non-exported stuff static. Remove functions and data which are now observably unused. Add comment about a small speedup that the run_algorithm() logic could use. Shrink a few too-long lines. Signed-off-by: David Brownell <dbrownell@users.sourceforge.net>
* David Brownell <david-b@pacbell.net> oharboe2009-09-121-4/+4
| | | | | | | | | | | | | | | Cleanup some the downloaded ARM target algorithm code: - Provide more complete disassembly of the DCC bulk write code - Make code blocks "static const", in case GCC doesn't - Fix some tabbing/layout issues - Make some arm7_9_common.h flags be "bool" not "int"; and compact the layout a bit (group most bools together) git-svn-id: svn://svn.berlios.de/openocd/trunk@2698 b42882b7-edfa-0310-969c-e2dbd0fdcd60
* David Brownell <david-b@pacbell.net> Several of the ARMv7M registers are 8 ↵oharboe2009-08-181-29/+30
| | | | | | | | | bits or less; don't display them as 32 bits unless that's their true size. (Removes some confusion. git-svn-id: svn://svn.berlios.de/openocd/trunk@2586 b42882b7-edfa-0310-969c-e2dbd0fdcd60
* - fix segfault introduced during cortex reg cleanupntfreak2009-08-071-2/+2
| | | | git-svn-id: svn://svn.berlios.de/openocd/trunk@2575 b42882b7-edfa-0310-969c-e2dbd0fdcd60
* David Brownell <david-b@pacbell.net>:ntfreak2009-07-211-3/+10
| | | | | | | | | | | Dump SP on poll, and show whether it's MSP or PSP. Thread mode can use either stack pointer, so this is part of the state that's not yet displayed. Shrink some lines. git-svn-id: svn://svn.berlios.de/openocd/trunk@2555 b42882b7-edfa-0310-969c-e2dbd0fdcd60
* David Brownell <david-b@pacbell.net>:ntfreak2009-07-211-56/+69
| | | | | | | | | | | | | | | | | | | | | | Clean up treatment of registers in ARMv7-M and Cortex-M3. - At the arch level: * Just list registers and names; don't impose core-specific policy about how they are accessed. * Each register has a symbol. * Remove the register mode field (irrelevant to debugger) - At the core/implementation level: * Just map the registers to their relevant access methods; don't require the arch level to say how that should work (cores other than Cortex-M3 could do it differently). * Don't use undefined bits from register 20. * Use register IDs that are part of the ARMv7-M interface. In short, there's now a real distinction between the arch and core layers. git-svn-id: svn://svn.berlios.de/openocd/trunk@2554 b42882b7-edfa-0310-969c-e2dbd0fdcd60
* David Brownell <david-b@pacbell.net>:ntfreak2009-07-211-20/+11
| | | | | | | | | Revert parts of the previous ARMv7-M register patch. It turns out that part of the issue is a documentation problem for the Cortex-M3 r1 parts. So for the rest, simpler fixes are possible (in followup patch). git-svn-id: svn://svn.berlios.de/openocd/trunk@2552 b42882b7-edfa-0310-969c-e2dbd0fdcd60
* Andreas Fritiofson <andreas.fritiofson@gmail.com> UTF8 fixesoharboe2009-07-171-1/+1
| | | | git-svn-id: svn://svn.berlios.de/openocd/trunk@2549 b42882b7-edfa-0310-969c-e2dbd0fdcd60
* Magnus Lundin <lundin@mlu.mine.nu>, Oyvind Harboe <oyvind.harboe@zylin.com>, ↵zwelch2009-07-161-79/+53
| | | | | | | | | | | | | | David Brownell <david-b@pacbell.net>: Move the dap command handler implementations to arm_adi_v5.c, leaving just thin wrappers in armv7m.c. There should be no change in functionality here. (From Magnus.) Minor style cleanup: whitespace, line length, etc. Update spec references to use docs which are currently available. (From Dave.) git-svn-id: svn://svn.berlios.de/openocd/trunk@2544 b42882b7-edfa-0310-969c-e2dbd0fdcd60
* Magnus Lundin <lundin@mlu.mine.nu>, Oyvind Harboe <oyvind.harboe@zylin.com>, ↵zwelch2009-07-161-13/+28
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | David Brownell <david-b@pacbell.net>: Some cleanup of the ARMv7-M support: - Reference the relevant ARMv7-M ARM doc (DDI 0405C to non-Vendors), and update the Cortex-M3 doc refs (DDI 0337C is no longer available). - Those registers aren't actually general, and some are incorrect (per all public docs anyway). Update comments and code accordingly. * What the Core Debug facility exposes is *implementation-specific* not architectural. These values aren't fully portable. They match Cortex-M3 ... so no current implementation will make trouble, but the next v7m implementation might. * Four of the registers are actually not exposed that way. Before Cortex-M3 r2p0 they are read/written through MRS/MSR instructions. In that newest silicon, they are four bytes in one register, not four separate registers. - Update the CM3 code to report when that one register is available, and not try to access it when it isn't. Also declare the register numbers that an eventual MRS/MSR solution will need to be using. - Stop line wrapping the exception labels. So for parts before r2p0 OpenOCD behavior is effectively unchanged, and still buggy; but for those newer parts a few things might now be correct. Most current Cortex-M3 parts use r1p1 (or earlier); this seems to include most LM3S parts and all STM32 parts. Parts using r2p0 are available, and include fourth generation LM3S parts ("Tempest") plus AT91SAM3 and LPC17xx parts which are now sampling. git-svn-id: svn://svn.berlios.de/openocd/trunk@2543 b42882b7-edfa-0310-969c-e2dbd0fdcd60
generated by cgit v1.2.3 (git 2.46.0) at 2024-11-19 04:11:08 +0000