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* Cortex-A8: avoid DSCR readsDavid Brownell2009-11-241-48/+103
| | | | | | | | | | | | | | | | | There was a lot of needless handshaking overhead in the current Cortex-A8 DCC/ITR operations, since the status read by each step was discarded rather than letting the next step know it. This shrinks the handshaking by: (a) passing status along from previous steps, avoiding re-fetching; which enables the big win (b) relying on a useful invariant: that the DSCR_INSTR_COMP bit is set after every call to a DPM method. A "reg sp_usr" call previously took 17 flushes; now it takes just 9. This visibly speeds common operations like entry to debug state and stepping, as well as "arm reg" and so on. Signed-off-by: David Brownell <dbrownell@users.sourceforge.net>
* Cortex-A8: hook up DPMDavid Brownell2009-11-241-323/+35
| | | | | | | | | This replaces two versions of register access functions. One was commented out, and seemed to have uncertain intent. The other was fairly new, and helped motivate the DPM framework once I observed that the ARM11 was doing the very same ops. Signed-off-by: David Brownell <dbrownell@users.sourceforge.net>
* Cortex-A8: implement DPMDavid Brownell2009-11-244-9/+176
| | | | | | | | This implements the DPM interface for Cortex-A8 cores. It also adds a synchronization operation to the DPM framework, which is needed by the Cortex-A8 after CPSR writes. Signed-off-by: David Brownell <dbrownell@users.sourceforge.net>
* Cortex-A8: minor cleanupDavid Brownell2009-11-242-26/+35
| | | | | | | | Make various functions static, add some comments, report vector catch as a flavor of DBG_REASON_BREAKPOINT, get rid of needless/undesirable ARMV4_5_CORE_REG_MODE, etc. Signed-off-by: David Brownell <dbrownell@users.sourceforge.net>
* ARM11: remove old R0..R15/CPSR codeDavid Brownell2009-11-242-196/+74
| | | | | | | | | | | | | | | | This finishes the basic switchover to the new register code, for everything except the debug registers. (And maybe we shouldn't have a cache for *those* which works this way...) The context save/restore code now uses the new code, but it's in a slightly different sequence. That should be fine since the R0/PC/CPSR stuff is all that really matters (and if we can update those, we can update the rest). Now there's no longer a way any code can be confused about which copy of "r1" (etc) to use. Signed-off-by: David Brownell <dbrownell@users.sourceforge.net>
* ARM11: use standard run_algorithm()David Brownell2009-11-241-172/+5
| | | | | | | | | | | | | | | | | | | | As with single stepping, the previous stuff was needed because the ARM11 code wasn't using the standard ARM base type and register access ... but now those mechanisms work, so we can switch out that special-purpose glue, in favor of the more thoroughly tested/capable "standard" code. Fixes a bug in the resume() implementation: it wasn't handling two of its arguments correctly, preventing the "flash erase_check" algorithm from working. (This code needs a *subsequent* update for correct register handling, though... removing the confusion about which "r2", for example, to use.) This should resolve some "FIXME" comments too, for Thumb and processor mode support. It also gets rid of a nasty exit() call; servers should only have *clean* shutdown paths. Signed-off-by: David Brownell <dbrownell@users.sourceforge.net>
* ARM11: use standard single step simulationDavid Brownell2009-11-241-97/+31
| | | | | | | | | | | | | | | | | | The previous stuff was needed because the ARM11 code wasn't using the standard ARM base type and register access ... but now those mechanisms work, so we can switch out that special-purpose glue. This should resolve all the "FIXME -- handle Thumb single stepping" comments too, and properly handle the processor's mode. (Modulo the issue that this code doesn't yet handle two-byte breakpoints.) Clarify the comments about the the hardware single stepping. When we eventually share breakpoint code with Cortex-A8, we can just make that be the default on cores which support it. We may still want an override command, not just to facilitate testing but to cope with "instruction address mismatch" not quite being true single-step. Signed-off-by: David Brownell <dbrownell@users.sourceforge.net>
* ARM11: partial support for standard ARM register interfaces.David Brownell2009-11-241-35/+31
| | | | | | | | | | | | | | | | | | | | | | | | | This provides "standard" ARM register support -- with twenty or more shadow registers on top of what this code now handles, but properly associated with the various core modes -- parallel to the current register code. That is, the current code is stilil managing the "current" registers; the new code shadows them. You can see all the registers with "arm reg", modify the shadows like "r8_fiq" or "sp_abt" with "reg", and see them get properly written back when you step. (Just don't do that with any of the registers managed by the "old" code ...) It also switches to using more standard code, relying on those standard registers, in two places: (a) the poll status display, which now shows core state (ARM/Thumb/...) and mode (Supervisor, IRQ, etc); and (b) GDB register access. So it's not a full migration, there are warts -- every place that touches the old register cache is a potential bug -- but it's a small more-or-less-comprehensible step that's even somewhat useful. Later patches complete the migration. Signed-off-by: David Brownell <dbrownell@users.sourceforge.net>
* ARM11: remove register "history" debug stuffDavid Brownell2009-11-242-59/+0
| | | | | | | | | | | | | | This was a private mechanism to snapshot registers before leaving debug state, and then on reentry to optionally display what changed. It was coupled to the private register cache, which won't be sticking around in that form for much longer. Remove (instead of teaching it how to handle *all* the registers). (The idea is interesting, but we ought to be able to implement this in a generic way. Ideally through Tcl scripts that can automatically be invoked following debug entry...) Signed-off-by: David Brownell <dbrownell@users.sourceforge.net>
* ARM11: implement provider for new DPM interfaceDavid Brownell2009-11-243-0/+80
| | | | | | | This is a very thin layer over some of the current ARM11 debug TAP utilities. The layer isn't yet hooked up. Signed-off-by: David Brownell <dbrownell@users.sourceforge.net>
* ARM: new DPM interfaceDavid Brownell2009-11-245-0/+625
| | | | | | | | | | | | | | | | | | | First version of interface for sharing code between ARMv6 and ARMv7a debug modules ... now the architecture includes debug support. (Not the same as for the trimmed-down v7m or v6m though!) This is a first version of an interface that will let the ARM11 and Cortex-A8 support share code, features, and bugfixes. Based on existing code from both of those cores. The ARM v7-AR architecture specification calls this commonality the "Debug Programmer's Model (DPM)", which seemed to be an appropriate acronym -- a TLA even! -- for use in our code. Made it so. :) The initial scope of this just supports register access, and is geared towards supporting top level "struct arm" mechanisms. Later, things like breakpoint and watchpoint support should be included. Signed-off-by: David Brownell <dbrownell@users.sourceforge.net>
* target: cope with *any* error setting a breakpointDavid Brownell2009-11-241-26/+24
| | | | | | It's wrong to map unrecognized failure codes to success. Signed-off-by: David Brownell <dbrownell@users.sourceforge.net>
* mips: fix gaffe when removing dynamic array allocationJerry Ling2009-11-241-3/+3
| | | | | | Classic sizeof() gaffe. Signed-off-by: Øyvind Harboe <oyvind.harboe@zylin.com>
* arm926ejs: retire cp15 commands, handled by mrc/mcr.Øyvind Harboe2009-11-231-66/+0
| | | | Signed-off-by: Øyvind Harboe <oyvind.harboe@zylin.com>
* ARM11: remove unused state and exportsDavid Brownell2009-11-224-32/+25
| | | | | | | | | For now there's no point in saving this stuff after examine() checks it out as OK. Ditto exporting symbols that aren't used outside of the module which defines them. In fact, those two things needlessly complicate the code... Signed-off-by: David Brownell <dbrownell@users.sourceforge.net>
* ARM11: macro cleanupDavid Brownell2009-11-222-72/+39
| | | | | | | | | | | | | | | | | Make this code look more like the rest of the OpenOCD code. - Use calloc() directly, not NEW() ... and fix some potential memory leaks while we're at it. - Remove FNC_INFO ... it's a NOP that just clutters things, and it's trivial for developers to add tracing as needed. - Replace FNC_INFO_NOTIMPLEMENTED with LOG_WARNING calls; ditto. And stop having those call sites wrongly succeed! - Waste less space with the CHECK_RETVAL() macro. Signed-off-by: David Brownell <dbrownell@users.sourceforge.net>
* mips: remove dynamic arrays - reduces stack usageØyvind Harboe2009-11-221-5/+15
| | | | | | Allocate working memory dynamically. Signed-off-by: Øyvind Harboe <oyvind.harboe@zylin.com>
* mips: use const for code sequencesØyvind Harboe2009-11-222-13/+13
| | | | | | | | This will allow data to be allocated in read only memory instead of on the stack. Speeds things up and reduces stack usage. Signed-off-by: Øyvind Harboe <oyvind.harboe@zylin.com>
* arm11: do not use dynamic arraysØyvind Harboe2009-11-221-3/+6
| | | | | | Allocate working memory dynamically, caught by checkstack.pl Signed-off-by: Øyvind Harboe <oyvind.harboe@zylin.com>
* arm926ejs: fix warningsØyvind Harboe2009-11-221-2/+2
| | | | | | | | buf_set_u32() operated on an uninitialized stack variable with non-byte boundaries, which led to warnings about reading uninitialized stack. Signed-off-by: Øyvind Harboe <oyvind.harboe@zylin.com>
* ARM: use arm_reg_current()David Brownell2009-11-223-61/+74
| | | | | | | | | | Start using the arm_reg_current() call. This shrinks and speeds the affected code. It can also prevent some coredumps coming from invalid CPSR values ... the ARMV4_5_CORE_REG_MODE() macro returns bogus registers if e.g. "Secure Monitor" mode isn't supported by the current CPU. Signed-off-by: David Brownell <dbrownell@users.sourceforge.net>
* ARM11: remove needless string format #ifdefferyDavid Brownell2009-11-223-21/+22
| | | | | | | | We don't need to use size_t in these places; so it's easy to be rid of the need for this #ifdef and its MS-derived portability problems. Signed-off-by: David Brownell <dbrownell@users.sourceforge.net>
* target: make register flags "bool"David Brownell2009-11-221-2/+2
| | | | | | Mostly for clarity, but it also saves code and data space. Signed-off-by: David Brownell <dbrownell@users.sourceforge.net>
* ARM: remove 'armv4_5_common_s' migration #defineDavid Brownell2009-11-2212-56/+53
| | | | | | Finish migrating from the old symbol to the new one. Signed-off-by: David Brownell <dbrownell@users.sourceforge.net>
* target: reduce stack usageØyvind Harboe2009-11-221-6/+20
| | | | | | | 4096 byte buffer allocated dynamically. Better for embedded OS's. Signed-off-by: Øyvind Harboe <oyvind.harboe@zylin.com>
* embedded: do not allocate large temporary structures on stackØyvind Harboe2009-11-221-6/+61
| | | | | | | With -O3 when inlining aggressively the total stack usage will be the sum of many fn's, which can easily get out of hand. Signed-off-by: Øyvind Harboe <oyvind.harboe@zylin.com>
* embedded: save stackØyvind Harboe2009-11-221-9/+15
| | | | | | | and also do not recaluate the crc32_table upon every invocation. Signed-off-by: Øyvind Harboe <oyvind.harboe@zylin.com>
* ARM: arm_set_cpsr() handles T and J bitsDavid Brownell2009-11-227-79/+52
| | | | | | | | | | | | | | Have arm_set_cpsr() handle the two core state flags, updating the CPU state. This eliminates code in various debug_entry() paths, and marginally improves handling of the J bit. Catch and comment a few holes in the handling of the J bit on ARM926ejs cores ... it's unlikely our users will care about Jazelle mode, but we can at least warn of Impending Doom. If anyone does use it, these breadcrumbs may help them to find the right path through the code. Signed-off-by: David Brownell <dbrownell@users.sourceforge.net>
* ARM: define two register utilitiesDavid Brownell2009-11-228-48/+122
| | | | | | | | | | | | | | Define arm_reg_current() ... returning handle to a given register, and encapsulating the current mode's register shadowing. It's got one current use, for reporting the current register set to GDB. This will let later patches clean up much ARMV4_5_CORE_REG_MODE() nastiness, saving a bit of code. Define and use arm_set_cpsr() ... initially it updates the cached CPSR and sets up state used by arm_reg_current(), plus any SPSR handle. (Later: can also set up for T and J bits.) Signed-off-by: David Brownell <dbrownell@users.sourceforge.net>
* ARM: simplify CPSR handlingDavid Brownell2009-11-2211-87/+103
| | | | | | | | | | | | | | Stash a pointer to the CPSR in the "struct arm", to help get rid of the (common) references to its index in the register cache. This removes almost all references to CPSR offsets outside of the toplevel ARM code ... except a pair related to the current ARM11 "simulator" logic (which should be removable soonish). This is a net minor code shrink of a few hundred bytes of object code, and also makes the code more readable. Signed-off-by: David Brownell <dbrownell@users.sourceforge.net>
* ARM11: remove disabled register hooksDavid Brownell2009-11-222-93/+3
| | | | | | | | Minor cleanup of ARM11 register handling: remove disabled register hooks. This should all be handled by shared code, and this stuff is just clutter. Signed-off-by: David Brownell <dbrownell@users.sourceforge.net>
* ARM: pass 'struct reg *' to register r/w routinesDavid Brownell2009-11-208-73/+83
| | | | | | | | | | | | | | | | Implementations need to access the register struct they modify; make it easier and less error-prone to identify the instance. (This removes over 10% of the ARMV4_5_CORE_REG_MODE nastiness...) Plus some minor fixes noted when making these updates: ARM7/ARM9 accessor methods should be static; don't leave CPSR wrongly marked "dirty"; note significant XScale omissions in register handling; and have armv4_5_build_reg_cache() record its result. Rename "struct armv4_5_core_reg" as "struct arm_reg"; it's used for more than those older architecture generations. Signed-off-by: David Brownell <dbrownell@users.sourceforge.net>
* ARM7/ARM9: remove old "debug commands"David Brownell2009-11-201-130/+0
| | | | | | | | | | | | | | | Remove two commands that were documented as "debug commands" and where "you probably don't want to use this". We never intended to support them, and at least one problem report boiled down to using this when it shouldn't have been used. Update the docs on the existing register commands to talk a bit more about register access and cache behavior. (Those debug commands existed largely to *bypass* the cache.) And fix some minor doc goofs that snuck in with recent changes, renaming "armv4_5" as "arm" and "arm9tdmi" as "arm9". Signed-off-by: David Brownell <dbrownell@users.sourceforge.net>
* Cortex-A8: better context restoreDavid Brownell2009-11-191-13/+67
| | | | | | | The previous version never wrote dirty registers for non-current CPU modes ... fix that. Signed-off-by: David Brownell <dbrownell@users.sourceforge.net>
* Cortex-A8: mode supportDavid Brownell2009-11-191-30/+116
| | | | | | | | | | | | | | | | We *should* be able to read and write registers in any core mode, instead of being stuck with whatever mode the core was when we entered debug state. This patch makes them work. Note that the current restore_context() only handles the current mode; writing to other-mode registers is a NOP without a followup patch fixing that. Also, that SPSR access needed some bugfixes; it was confused with CPSR. Secure monitor mode also seems dubious; there's probably more to be done before that's sufficiently understood by the debugger. Signed-off-by: David Brownell <dbrownell@users.sourceforge.net>
* target: create/use register_cache_invalidate()David Brownell2009-11-1914-77/+47
| | | | | | | | | | | | | | | Create a generic register_cache_invalidate(), and use it to replace three all-but-identical core-specific routines: - armv4_5_invalidate_core_regs() - armv7m_invalidate_core_regs - mips32_invalidate_core_regs() too. Make cache->num_regs be unsigned, avoiding various errors. Net code shrink and simplification. Signed-off-by: David Brownell <dbrownell@users.sourceforge.net>
* ARM: remove per-register mallocDavid Brownell2009-11-192-1/+2
| | | | | | | Just pre-allocate memory for the cached register value. Shrinks heap overhead; increases locality-of-reference. Signed-off-by: David Brownell <dbrownell@users.sourceforge.net>
* ARM: streamline register initDavid Brownell2009-11-191-74/+88
| | | | | | | | | Combine register names with other per-register data into a single template structure. This saves space, and makes it easier to change how registers get handled (by shrinking the number of places that care about cache indices). Signed-off-by: David Brownell <dbrownell@users.sourceforge.net>
* Cortex-A8: parts of examine() run just onceDavid Brownell2009-11-191-4/+15
| | | | | | | | | The examine() method has some conceptual breakage. Cope with it by manually splitting out the run-once parts from the after-each-reset parts ... this gets rid of memory leaks and speeds up resets after the first one. Signed-off-by: David Brownell <dbrownell@users.sourceforge.net>
* ARMv7-A: use standard ARM core statesDavid Brownell2009-11-195-31/+43
| | | | | | | | | | | | | | | We don't want an ARMv7-specific core state enumeration just to add ThumbEE state. Update the generic stuff to handle that, and replace the V7-specific bits with it. For Cortex-A8: on debug entry, check both the T and J bits instead of just the T bit. When the J bit is set, set the right state and warn appropriately. (And while we're at it, move the generic arm struct to the front of the v7a structure, for somewhat better code generation.) Signed-off-by: David Brownell <dbrownell@users.sourceforge.net>
* ARMv7-A: use standard ARM core_mode symbolsDavid Brownell2009-11-192-16/+3
| | | | | | | | | The only way ARMv7-A modes differ from ARMv4/ARMv5 flavors is that v7-A is allowed to include "Secure monitor" support. That's now handled by our standard top-level ARM code ... so phase out the stuff that's specific to ARMv7-A. Signed-off-by: David Brownell <dbrownell@users.sourceforge.net>
* remove fast command and jim_global_longZachary T Welch2009-11-181-2/+2
| | | | | | | | Removing the fast command eliminates the fast_and_dangerous global, which was used only by arm7_9_common as an initializer. The command is not called in the tree; instead, more explicit commands are used. The jim_global_long function was not used anywhere in the tree.
* add handle_command_parse_bool command helperZachary T Welch2009-11-181-45/+10
| | | | | | | | | Rewrite arm11_handle_bool to provide a generic on/off command helper. Refactors COMMAND_PARSE_BOOL to use new command_parse_bool helper, which gets reused by the new command_parse_bool_any helper. This later helper is called by the new command helper function to accepts any on/off, enable/disable, true/false, yes/no, or 0/1 parameter.
* use COMMAND_PARSE_ENABLE macro where appropriateZachary T Welch2009-11-183-96/+31
| | | | | | | | Updates all command parsing of simple "enable" and "disable" arguments. A few case in the tree use a tri-state or extended arguments, which cannot use this simple macro. Simlifies the xscale icache/dcache command handler logic.
* use COMMAND_PARSE_ON_OFF where appropriateZachary T Welch2009-11-182-26/+10
| | | | Updates all command parsing of "on" and "off" arguments.
* ARM: rework "arm reg" output for new modeDavid Brownell2009-11-181-35/+113
| | | | | | | | | | | | | | | | Change the layout to show the "Secure Monitor" registers too, when they're present. Instead of lining registers for each of six (or seven) modes up in adjacent vertical columns, display each mode's registers (or shadows) in a single block, avoiding duplicate value displays. This also lets us shrink the line length to fits in standard 80 character lines ... six or seven 18-character columns can't fit. Relabel "r13" as "sp", so it's more meaningful. Signed-off-by: David Brownell <dbrownell@users.sourceforge.net>
* Cortex-A8: xPSR handling updatesDavid Brownell2009-11-181-17/+20
| | | | | | | | | | When we read the CPSR on debug entry, update the CPSR cache in all cases, not just when the current processor state is User or System. Plus minor cleanup of how the (too-many) other registers' cache entries get updated. Signed-off-by: David Brownell <dbrownell@users.sourceforge.net>
* ARM: add a default full_context() methodDavid Brownell2009-11-182-12/+27
| | | | | | | | | | | | If the core doesn't provide an optimized version of this method, provide one without core-specific optimizations. Use this to make Cortex-A8 support the "arm reg" command. Related: make the two register access methods properly static, have the "set" log a "not halted" error too, and make sure that the "valid" flag is set on successful reads. Signed-off-by: David Brownell <dbrownell@users.sourceforge.net>
* ARM: simplify ARMv7-A register handlingDavid Brownell2009-11-183-188/+50
| | | | | | | | | | | | | | | | | | | ARMv7-A doesn't need to duplicate all the standard ARM code for register handling. - Switch Cortex-A8 to use the standard register code - Remove duplicated infrastructure from ARMv7-A - Have ARMv7-A arch_state() show CPSR, like other ARMs Add comments to show where the Cortex-A8 isn't actually doing the right thing for register reads/writes, unless core happens to be in the right mode to start with. (Looks like maybe there may be generic confusion between saved/current PSR values in all the ARM code ...) Make related ARMv7-A and Cortex-A8 symbols properly static. Signed-off-by: David Brownell <dbrownell@users.sourceforge.net>
* ARM: setup "secure monitor mode" shadow regsDavid Brownell2009-11-182-21/+53
| | | | | | | | | | | | | Teach the "armv4_5" register code to understand about the secure monitor mode: - Add the other three shadowed registers to the arrays - Support another internal mode number (sigh) in mappings - Catch malloc/calloc failures building that register cache This should kick in for Cortex-A8 and ARM1176. Signed-off-by: David Brownell <dbrownell@users.sourceforge.net>
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