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* NOR: invalidate cached state on target resumeDavid Brownell2010-03-031-0/+9
| | | | | | | | | | | | | | | | | | | | The NOR infrastructure caches some per-sector state, but it's not used much ... because the cache is not trustworthy. This patch addresses one part of that problem, by ensuring that state cached by NOR drivers gets invalidated once we resume the target -- since targets may then modify sectors. Now if we see sector protection or erase status marked as anything other than "unknown", we should be able to rely on that as being accurate. (That is ... if we assume the drivers initialize and update this state correctly.) Another part of that problem is that the cached state isn't much used (being unreliable, it would have been unsafe). Those issues can be addressed in later patches. Signed-off-by: David Brownell <dbrownell@users.sourceforge.net>
* ADIv5: use new DAP ops for AP read/writeDavid Brownell2010-03-023-106/+79
| | | | | | | | | | | | | | | | | | | Make ADIv5 internals use the two new transport-neutral calls for reading and writing DP registers; and do the same for external callers. Also, bugfix some of their call sites to handle the fault returns, instead of ignoring them. Remove most of the JTAG-specific calls, using their code as the bodies of the JTAG-specific implementation for the new methods. NOTE that there's a remaining issue: mem_ap_read_buf_u32() makes calls which are JTAG-specific. A later patch will need to remove those, so JTAG-specific operations can be removed from this file, and so that SWD support will be able to properly drop in as just a transport layer to the ADIv5 infrastructure. (The way read results are posted may need some more attention in the transport-neutrality interface.) Signed-off-by: David Brownell <dbrownell@users.sourceforge.net>
* ADIv5: use new DAP ops for DP read/writeDavid Brownell2010-03-021-32/+38
| | | | | | | | | | | Make ADIv5 internals use the two new transport-neutral calls for reading and writing DP registers. Also, bugfix some of their call sites to handle the fault returns, instead of ignoring them. Remove the old JTAG-specific calls, using their code as the bodies of the JTAG-specific implementation for the new methods. Signed-off-by: David Brownell <dbrownell@users.sourceforge.net>
* ADIv5: use new dap_run() operationDavid Brownell2010-03-023-37/+74
| | | | | | | | | | Make ADIv5 use one of the new transport-neutral interfaces: call dap_run(), not jtagdp_transaction_endcheck(). Also, make that old interface private; and bugfix some of its call sites to handle the fault returns, instead of ignoring them. Signed-off-by: David Brownell <dbrownell@users.sourceforge.net>
* ARM: start abstracting ADIv5 transports (JTAG/SWD)David Brownell2010-03-022-0/+278
| | | | | | | | | | | | | | | | | | | | | | | | | | | | To support both JTAG and SWD, ADIv5 needs DAP operations which are transport-neutral, instead being of JTAG-specific. This patch: - Defines such a transport-neutral interface, abstracting access to DP and AP registers through a conceptual queue of operations. - Builds the first implementation of such a transport with the existing JTAG-specific code. In contrast to the current JTAG-only interface, the interface adds support for two previously-missing (and unused) DAP operations: - aborting the current AP transaction (untested); - reading the IDCODE register (tested) ... required for SWD init. The choice of transports may be fixed at the chip, board, or JTAG/SWD adapter level. Or if all the relevant hardware supports both transport options, the choice may be made at runtime, This patch provides basic infrastructure to support whichever choice is made. The current "JTAG-only" transport choice policy will necessarily continue for now, until SWD support becomes available in OpenOCD. Later patches start phasing out JTAG-specific calls in favor of transport-neutral calls. Signed-off-by: David Brownell <dbrownell@users.sourceforge.net>
* target_resume() doxygenDavid Brownell2010-03-021-3/+33
| | | | | | | | | | | Add doxygen for target_resume() ... referencing the still-unresolved confusion about what the "debug_execution" parameter means (not all CPU support code acts the same). The 'handle_breakpoints" param seems to have resolved the main issue with its semantics, but it wasn't part of the function spec before. Signed-off-by: David Brownell <dbrownell@users.sourceforge.net>
* ADIv5: use right ID for Cortex-M3 ETMDavid Brownell2010-03-021-4/+4
| | | | | | | | | Correct a mistake made copying the ID of the Cortex-M3 ETM module from the TRM, so that "dap info" on a CM3 with an ETM will now correctly describe ROM table entries for such modules. (They are included on LPC17xx and some other cores.) Signed-off-by: David Brownell <dbrownell@users.sourceforge.net>
* arm_semihosting buildfixDavid Brownell2010-03-011-8/+14
| | | | | | | | | | | | | | The recent "add armv7m semihosting support" patch introduced two build errors: arm_semihosting.c: In function ‘do_semihosting’: arm_semihosting.c:71: error: ‘spsr’ may be used uninitialized in this function arm_semihosting.c:71: error: ‘lr’ may be used uninitialized in this function This fixes those build errors. The behavior is, however, untested. (Also, note the two new REVISIT comments.) Signed-off-by: David Brownell <dbrownell@users.sourceforge.net>
* armv4_5: remove core_type check in mcr/mrc cmdSpencer Oliver2010-02-281-7/+0
| | | | | | | core_type check is not required as the core function will be null for cores that do not support the mcr/mrc functions. Signed-off-by: Spencer Oliver <ntfreak@users.sourceforge.net>
* semihosting: add armv7m semihosting supportSpencer Oliver2010-02-283-76/+137
| | | | | | | do_semihosting and arm_semihosting now check the core type and use the generic arm structure. Signed-off-by: Spencer Oliver <ntfreak@users.sourceforge.net>
* semihosting: move semihosting cmd to arm cmd groupSpencer Oliver2010-02-283-44/+68
| | | | | | | | | Move semihosting cmd to the arm cmd group. Targets that support semihosting will setup the setup_semihosting callback function. Signed-off-by: Spencer Oliver <ntfreak@users.sourceforge.net>
* CortexM3: move disassemble cmd to arm cmd groupSpencer Oliver2010-02-281-51/+0
| | | | | | | Rather than using a Cortex disassemble cmd, we now use the arm generic version. Signed-off-by: Spencer Oliver <ntfreak@users.sourceforge.net>
* ARMv7M: add arm cmd groupSpencer Oliver2010-02-282-2/+31
| | | | | | | | - Add arm cmd group to armv7m cmd chain. - arm cmd's now check the core type before running a cmd. - todo: add support for armv7m registers for reg cmd. Signed-off-by: Spencer Oliver <ntfreak@users.sourceforge.net>
* MIPS: add mips algorithm supportSpencer Oliver2010-02-284-82/+392
| | | | | | | | - add mips support for target algorithms. - added handlers for target_checksum_memory and target_blank_check_memory. - clean up long lines Signed-off-by: Spencer Oliver <ntfreak@users.sourceforge.net>
* ARMv7M: use software breakpoints for algorithmsSpencer Oliver2010-02-281-18/+5
| | | | | | | | - armv7m_run_algorithm now requires all algorithms to use a software breakpoint at their exit address - updated all algorithms to support this Signed-off-by: Spencer Oliver <ntfreak@users.sourceforge.net>
* ADIv5 DAP ops switching to JTAG or SWD modesDavid Brownell2010-02-272-0/+121
| | | | | | | | | | | Define two new DAP operations which use the new jtag_add_tms_seq() calls to put the DAP's transport into either SWD or JTAG mode, when the hardware allows. Tested with the Stellaris 'Recovering a "Locked" Device' procedure, which loops five times over both of these. Signed-off-by: David Brownell <dbrownell@users.sourceforge.net>
* ARM ADIv5 doxygen and cleanupDavid Brownell2010-02-241-15/+42
| | | | | | | Add doxygen for mem_ap_read_buf_u{8,16,32}() calls, and shrink a few overlong lines. Signed-off-by: David Brownell <dbrownell@users.sourceforge.net>
* ARM ADIv5: rename more JTAG-specific routinesDavid Brownell2010-02-231-11/+11
| | | | | | | Highlight more of the internal JTAG-specific utilities, so it's easier to identify code needing changes to become transport-neutral. Signed-off-by: David Brownell <dbrownell@users.sourceforge.net>
* arm11: allow minidrivers to implement inner loop of memory writesØyvind Harboe2010-02-221-45/+92
| | | | | | | | | | | | | | | This allows minidrivers to e.g. hardware accelerate memory writes. Same trick as is used for arm7/9 dcc writes. Added error propagation for memory transfer failures in code rearrangement. Also the JTAG end state is not updated until after the memory write run is complete. Signed-off-by: Øyvind Harboe <oyvind.harboe@zylin.com>
* ADIv5: relocate memacess_tck cyclesDavid Brownell2010-02-211-12/+12
| | | | | | | | | | | | | When using an AP to access a memory (or a memory-mapped register), some extra TCK (assuming JTAG) cycles should be added to ensure the AP has enugh time to complete that access before trying to collect the response. The previous code was adding these cycles *before* trying to access (read or write) data to that address, not *after*. Fix by putting the delays in the right location. Signed-off-by: David Brownell <dbrownell@users.sourceforge.net>
* ADIv5: remove ATOMIC/COMPOSITE interface modeDavid Brownell2010-02-213-98/+29
| | | | | | | | | | | | | This removes context-sensitivity from the programming interface and makes it possible to know what a block of code does without needing to know the previous history (specifically, the DAP's "trans_mode" setting). The mode was only set to ATOMIC briefly after DAP initialization, making this patch be primarily cleanup; almost everything depends on COMPOSITE. The transactions which shouldn't have been queued were already properly flushing the queue. Signed-off-by: David Brownell <dbrownell@users.sourceforge.net>
* ARM: ADIv5, deadcode cleanupDavid Brownell2010-02-211-13/+13
| | | | | | | | | | | | I have no idea what the scan_inout_check() was *expecting* to achieve by issuing a read of the DP_RDBUFF register. But in any case, that code was clearly never being called ("invalue" always NULL) ... so remove it, and the associated comment. Also rename it as ap_write_check(), facilitating a cleanup of its single call site by removing constant parameters. Signed-off-by: David Brownell <dbrownell@users.sourceforge.net>
* ARM: ADIv5 code shrinkage, cleanupDavid Brownell2010-02-211-40/+16
| | | | | | | | | | adi_jtag_dp_scan_u32() now wraps adi_jtag_dp_scan(), removing code duplication. Include doxygen for the former. Comment some particularly relevant points. Minor fault handling fixes for both routines: don't register a callback that can't run, or return ERROR_OK after an error. Signed-off-by: David Brownell <dbrownell@users.sourceforge.net>
* ADIv5 clean up AP fault handlingDavid Brownell2010-02-211-32/+46
| | | | | | | | | | | | | | | | | Pass up fault codes from various routines, so their callers can clean up after failures, and remove the FIXME comments highlighting those previously goofy code paths. dap_ap_{read,write}_reg_u32() dap_ap_write_reg() mem_ap_{read,write}_u32() mem_ap_{read,write}_atomic_u32() dap_setup_accessport() Make dap_ap_write_reg_u32() just wrap dap_ap_write_reg(), instead of cloning its core code (and broken fault handling). Signed-off-by: David Brownell <dbrownell@users.sourceforge.net>
* ADIv5 clean up AP selection and register cachingDavid Brownell2010-02-214-34/+60
| | | | | | | | | | | | | | | | | | | Handling of AP (and AP register bank) selection, and cached AP registers, is pretty loose ... start tightening it: - It's "AP bank" select support ... there are no DP banks. Rename. + dap_dp_bankselect() becomes dap_ap_bankselect() + "dp_select_value" struct field becomes "ap_bank_value" - Remove duplicate AP cache init paths ... only use dap_ap_select(), and don't make Cortex (A8 or M3) cores roll their own code. - For dap_ap_bankselect(), pass up any fault code from writing the SELECT register. (Nothing yet checks those codes.) - Add various bits of Doxygen Signed-off-by: David Brownell <dbrownell@users.sourceforge.net>
* ARM: keep a handle to the PCDavid Brownell2010-02-2116-88/+106
| | | | | | | | | | | | | | | | Keep a handle to the PC in "struct arm", and use it. This register is used a fair amount, so this is a net minor code shrink (other than some line length fixes), but mostly it's to make things more readable. For XScale, fix a dodgy sequence while stepping. It was initializing a variable to a non-NULL value, then updating it to handle the step-over-active-breakpoint case, and then later testing for non-NULL to see if it should reverse that step-over-active logic. It should have done like ARM7/ARM9 does: init to NULL. Signed-off-by: David Brownell <dbrownell@users.sourceforge.net>
* ARM DPM: support adding/removing HW breakpointsDavid Brownell2010-02-211-38/+113
| | | | | | | | | | | | | | Generalize the core of watchpoint setup so that it can handle breakpoints too. Create breakpoint add/remove routines which will use that, and hook them up to target types which don't provide their own breakpoint support (nothing, yet). This suffices for hardware-only breakpoint support. The ARM11 code will be able to switch over to this without much trouble, since it doesn't yet handle software breakpoints. Switching Cortex-A8 will be a bit more involved. Signed-off-by: David Brownell <dbrownell@users.sourceforge.net>
* ARM11: per-core options should not be globalDavid Brownell2010-02-212-33/+44
| | | | | | | | | | Address some FIXME comments by getting rid of globals, moving per-core parameters in the existing per-core data structure. This will matter most whenever there are multiple ARM11 cores, e.g. ARM11 MPcore chips, but in general is just cleanup. Signed-off-by: David Brownell <dbrownell@users.sourceforge.net>
* ARMv7-M: start using "struct arm"David Brownell2010-02-215-9/+74
| | | | | | | | | | | | | | | | | | | | | | | | | | | This sets up a few of the core "struct arm" data structures so they can be used with ARMv7-M cores. Specifically, it: - defines new ARM core_modes to match the microcontroller modes (e.g. HANDLER not IRQ, and two types of thread mode); - Establishes a new microcontroller "core_type", which can be used to make sure v7-M (and v6-M) cores are handled right; - adds "struct arm" to "struct armv7m" and arranges for the target_to_armv7m() converter to use it; - sets up the arm.core_cache and arm.cpsr values - makes the Cortex-M3 code maintain arm.map and arm.core_mode. This is currently set up as a parallel data structure, primarily to minimize special cases for the semihosting support with microcontroller profile cores. Later patches can rip out the duplicative ARMv7-M support and start reusing core ARM code. Signed-off-by: David Brownell <dbrownell@users.sourceforge.net>
* arm920t line length cleanupDavid Brownell2010-02-201-115/+247
| | | | | | | | | | | | The recent patch to fixbreakpoints and dcache handling added a bunch of overlong lines (80+ chars) ... shrink them, and do the same to a few lines which were already overlong. Also add a few FIXME comments to nudge (a) replacement of some magic numbers with opcode macros, which will be much better at showing what's actually going on, and (b) correct return codes. Signed-off-by: David Brownell <dbrownell@users.sourceforge.net>
* atm920t : fix breakpoints and data cache handlingMarc Pignat2010-02-191-17/+103
| | | | | | | | | Breakpoints did not work because the data cache was not flushed properly. As a bonus add capability to write to memory marked as read only by the MMU, which allows software breakpoints in such memory regions.
* ARM920T scanchain 15 comments/cleanupDavid Brownell2010-02-161-51/+112
| | | | | | | | | | | | | | | | | For folk who don't know the ARM920 JTAG interface very well, the two modes of scan chain 15 access to CP15 are confusing. Make those parts of the ARM920 code less opaque, by: - Adding comments referencing the relevant parts of the TRM, catching up to similar updates in the User's Guide. - Replacing magic numbers in physical access clients with symbolic equivalents. No functional change. Signed-off-by: David Brownell <dbrownell@users.sourceforge.net>
* fix crash with DSP563XXMathias Kuester2010-02-141-0/+25
| | | | | | | | | | | When a DSP563xx-aware GDB asks OpenOCD for target registers, the result should be a GDB with register data ... not an OpenOCD crash. (Note that mainline GDB doesn't currently support this core, so for now, this requires a GDB with FreeScale patches.) Signed-off-by: David Brownell <dbrownell@users.sourceforge.net>
* arm720t: virt2phys callback addedØyvind Harboe2010-02-121-4/+14
| | | | | | | | This is a copy and paste of arm926ejs. Not tested, but ready for testing at least. There is a good chance that it will work if the generic armv4_5 fn's are robust enough... Signed-off-by: Øyvind Harboe <oyvind.harboe@zylin.com>
* arm920: add virt2phys fnMarc Pignat2010-02-121-3/+13
| | | | | | | Copy of the 926ejs function. I have tested it only using my rtems application (where virtual address mapping == physical). Signed-off-by: Øyvind Harboe <oyvind.harboe@zylin.com>
* arm11: fix another infinite loop bugØyvind Harboe2010-02-101-4/+23
| | | | | | | | | | | | | reset init would get stuck in an infinite loop when e.g. khz was too high. Added timeout. This is a copy of paste of a number of such bugfixes in the arm11 code. Arm11 code reviewed for further such infinite loop bugs and I couldn't find any more. Xing fingers it's the last one... Signed-off-by: Øyvind Harboe <oyvind.harboe@zylin.com>
* target: add todo in target_write_memory() about alignmentØyvind Harboe2010-02-091-2/+13
| | | | | | | target_write_buffer() does not align "buffer" in host memory passed to target_write_memory(). Signed-off-by: Øyvind Harboe <oyvind.harboe@zylin.com>
* ADIv5: doxygenDavid Brownell2010-02-062-32/+138
| | | | | | | | | | | | | | | | | Provide doxygen for many of the public ADIv5 interfaces (i.e. the ones called from Cortex core support code). Add FIXMEs (and a TODO) to help resolve implementation issues which became more apparent when trying to document this code: - Error-prone context-sensitivity (queued/nonqueued) in many procedures. - Procedures that lie by ignoring errors and wrongly claiming success. Also, there was no point in a return from dap_ap_select(); it can't fail, and no caller checks its return status. Clean that up, make it void. Signed-off-by: David Brownell <dbrownell@users.sourceforge.net>
* ARMv7-M: make DAP commands verify target is an ARMv7-MDavid Brownell2010-02-042-3/+31
| | | | | | | | Init the ARMv7-M magic number. Define predicate verifying it. Use it to resolve a lurking bug/FIXME: make sure the ARMv7-M specific DAP ops reject non-ARMv7-M targets. Signed-off-by: David Brownell <dbrownell@users.sourceforge.net>
* ARM semihosting: fix EOF handling with SYS_READNicolas Pitre2010-02-021-1/+1
| | | | | | | | The semihosting interface has a strange convention for read/write where the unused amount of buffer must be returned. We failed to return the total buffer size when the local read() call returned 0. Signed-off-by: Nicolas Pitre <nico@marvell.com>
* gdb: restore behavior from 0.3.1 for srst_asserted and power_restoreØyvind Harboe2010-02-011-13/+23
| | | | | | | | srst_asserted and power_restore can now be overriden to do nothing. By default they will "reset init" the targets and halt gdb. Signed-off-by: Øyvind Harboe <oyvind.harboe@zylin.com>
* ADIv5: more messaging cleanup, docsDavid Brownell2010-01-311-12/+20
| | | | | | | | | When the TAR cache was explicitly invalidated, don't bother printing it; the actual hardware status is more informative. Provide some doxygen for the MEM-AP setup routine. Signed-off-by: David Brownell <dbrownell@users.sourceforge.net>
* build: fix problems with "struct stat" not being defined under eCosØyvind Harboe2010-01-311-0/+1
| | | | | | | Include <sys/stat.h> according to http://www.opengroup.org/onlinepubs/000095399/functions/stat.html Signed-off-by: Øyvind Harboe <oyvind.harboe@zylin.com>
* Subject: ADIv5: fix more diagnosticsDavid Brownell2010-01-311-9/+16
| | | | | | | | | | | If the MEM-AP cache is invalid, don't display it; just report that invalidity as an error. (This bug has been observed with "mdw 0 32" after just a "reset halt". Some code is being wrongly bypassed...) If it's valid, display that cache at DEBUG level, not ERROR. Also, don't assume it's an AHB-AP; it could be another flavor of MEM-AP. Signed-off-by: David Brownell <dbrownell@users.sourceforge.net>
* ADIv5 error checking for Tcl commandsDavid Brownell2010-01-301-1/+17
| | | | | | | | | Reject invalid AP numbers (256+) as Tcl operation parameters. Shrink one of the overlong lines. Add my copyright to the ADIv5 code (multiple contributions). Signed-off-by: David Brownell <dbrownell@users.sourceforge.net>
* ARM ADIv5: fix diagnostics for block writesDavid Brownell2010-01-301-5/+14
| | | | | | They were reporting "read" errors, not "write" errors. Signed-off-by: David Brownell <dbrownell@users.sourceforge.net>
* ADIv5: cleanup, rename swjdp_transaction_endcheck()David Brownell2010-01-293-34/+43
| | | | | | | | | | | | | | | | Make messages reference "DAP" if they're actually transport-agnostic, or "JTAG-DP" when they're JTAG-specific. Saying SWJ-DP is often wrong (on most Cortex-A8 chips) and is confusing even if correct (since we don't yet support SWD). Rename a JTAG-specific routine to jtagdp_transaction_endcheck() to highlight that it's JTAG-specific, and that identify DAP clients undesirably depending on JTAG. (They will all need to change for SWD support.) Shrink a few overlong lines of code. Copy a comment from code removed in a previous patch (for the ARMv7-M "dap baseaddr" command). Signed-off-by: David Brownell <dbrownell@users.sourceforge.net>
* ARMv7-M: use command handler for "dap baseaddr".David Brownell2010-01-291-30/+1
| | | | | | | | | | Make the ARMv7-M DAP code reuse the command handler for "dap baseaddr". For some reason, this DAP command wasn't converted earlier. This is a code shrink and simplification; it also removes a needless transport dependency on JTAG. Signed-off-by: David Brownell <dbrownell@users.sourceforge.net>
* ARM: reference DPM defn from v6/v7 arch specDavid Brownell2010-01-281-0/+6
| | | | | | | | The term "DPM" is probably not well known ("Device Power Management"?), so identify its source in the current ARM architecture specification. It's relevant to ARMv6, ARMv7-A, and ARMv7-R ... but not "M" profiles. Signed-off-by: David Brownell <dbrownell@users.sourceforge.net>
* ARM semihosting: win32 and cygwin fixesSpencer Oliver2010-01-281-16/+26
| | | | | | | | | | | | Cygwin would fail to reopen a previously written file if the mode is not given. Simplified converting the open flags and made sure the win32 O_BINARY bit is set. Added define for systems that do not support O_BINARY. Signed-off-by: Spencer Oliver <ntfreak@users.sourceforge.net>
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