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* ARM: don't clone arm_arch_state() codeDavid Brownell2009-12-074-33/+8
| | | | | | | | | | | Have various ARM cores delegate to arm_arch_state() to display basic information, instead of duplicating that logic. This shrinks the code, makes them all report when semihosting is active, and highlights which data are specific to this core. (Like ARM720 not having separate instruction and data caches.) Signed-off-by: David Brownell <dbrownell@users.sourceforge.net>
* ARM: use <target/arm.h> not armv4_5.hDavid Brownell2009-12-0724-200/+231
| | | | | | | | | | | | | | Move most declarations in <target/armv4_5.h> to <target/arm.h> and update users. What's left in the older file is stuff that I think should be removed ... the old register cache access stuff, which makes it awkward to support microcontroller profile (Cortex-M) cores. The armv4_5_run_algorithm() declaration was moved too, even though it's not yet as generic as it probably ought to be. Signed-off-by: David Brownell <dbrownell@users.sourceforge.net>
* ARM: rename some generic routinesDavid Brownell2009-12-0715-32/+34
| | | | | | | | | | | | | | | | Rename some (mostly) generic ARM functions: armv4_5_arch_state() --> arm_arch_state() armv4_5_get_gdb_reg_list() --> arm_get_gdb_reg_list() armv4_5_init_arch_info() --> arm_init_arch_info() Cores using the microcontroller profile may want a different arch_state() routine though. (Also fix strange indentation in arm_arch_state: use tabs only! And update a call to it, removing assignment-in-conditional.) Signed-off-by: David Brownell <dbrownell@users.sourceforge.net>
* ARM: move opcode macros to <target/arm_opcodes.h>David Brownell2009-12-0718-249/+281
| | | | | | | | | | | | | | | Move the ARM opcode macros from <target/armv4_5.h>, and a few Thumb2 ones from <target/armv7m.h>, to more appropriate homes in a new <target/arm_opcodes.h> file. Removed duplicate opcodes from that v7m/Thumb2 set. Protected a few macro argument references by adding missing parentheses. Tightening up some of the line lengths turned up a curious artifact: the macros for the Thumb opcodes are all 32 bits wide, not 16 bits. There's currently no explanation for why it's done that way... Signed-off-by: David Brownell <dbrownell@users.sourceforge.net>
* ARM: remove mrc_opcode(), use MRC() or MCR()David Brownell2009-12-073-20/+32
| | | | | | | | | | | | Get rid of mrc_opcode() in favor of ARMV4_5_MRC() or, where arm*20t should have used it, ARMV4_5_MCR() instead. Basically, *writing* coprocessor registers shouldn't have used the *read* opcode ... and both should stick to standard opcode constructors, not rearranging parameter sequence any more than already needed. Signed-off-by: David Brownell <dbrownell@users.sourceforge.net>
* ARM: disassemble two more v6+ instructionsDavid Brownell2009-12-071-12/+71
| | | | | | | | | | | The SRS and RFE instructions speed exception entry/exit by making it easy to save and restore PC and SPSR. This handles both ARM and Thumb2 encodings. Fix minor PLD goofage; that "should never reach this point" can't happen, so remove it. Signed-off-by: David Brownell <dbrownell@users.sourceforge.net>
* ARM DPM: don't write low bits of watchpoint valueDavid Brownell2009-12-071-1/+1
| | | | | | | The low two bits are defined as should-be-zero-or-presereved. We'll take the zero option, it's easier to enforce. Signed-off-by: David Brownell <dbrownell@users.sourceforge.net>
* add 'flash list', rewrite 'flash banks'Zachary T Welch2009-12-062-20/+28
| | | | | | | Rename the existing 'flash banks' implementation as 'flash list', and replace the broken 'flash_banks' TCL wrapper with a new command handler. Adds documentation for the new 'flash list' command in the user guide.
* allow 'flash_banks' command to give GDB outputZachary T Welch2009-12-061-1/+1
| | | | | | | | | The 'flash banks' command produces a list that needs to be formatted properly for GDB's 'mem info' to work properly. The flash_banks TCL wrapper provided this formatting, but wrappers no longer work for second-level commands as they did in the past. With this patch, the 'flash_banks' command can be used with the new command syntax and display the required information.
* fix NOR flash regressionZachary T Welch2009-12-061-0/+2
| | | | | When factoring the bank setup command into flash_bank_add(), I forgot to include a call to the new helper.
* misc code review updatesDavid Brownell2009-12-054-14/+11
| | | | | | | | | More updates from the code review by Steve Grubb <sgrubb@redhat.com>. The Jim float-comparision bug just gets a comment not a fix, though. Cc: Steve Grubb <sgrubb@redhat.com>. Signed-off-by: David Brownell <dbrownell@users.sourceforge.net>
* NOR: add 29LV400BC flash deviceMathias Kuester2009-12-051-0/+17
| | | | Signed-off-by: David Brownell <dbrownell@users.sourceforge.net>
* ARM semihosting: use breakpoint on ARM7Nicolas Pitre2009-12-041-7/+9
| | | | | | | | | | | | Fall back to software breakpoint when vector catch isn't available. Possible enhancements: - add extra optional command parameter to select high vectors - add extra optional command parameter to select hardware breakpoint Signed-off-by: Nicolas Pitre <nico@marvell.com> Signed-off-by: David Brownell <dbrownell@users.sourceforge.net>
* ARM semihosting: work with both low and high vectorsNicolas Pitre2009-12-041-6/+4
| | | | | Signed-off-by: Nicolas Pitre <nico@marvell.com> Signed-off-by: David Brownell <dbrownell@users.sourceforge.net>
* rename nand.h to flash//nand/core.hZachary T Welch2009-12-0420-28/+33
| | | | | | | | | Rename nand.h as flash/nand/core.h, chase consumers. The public APIs need to be sorted out with imp.h, but this allows other changes to begin improving the separation between policy and mechanism. Moves #include <target/target.h> and #include "driver.h" into the internal headers or source files, removing it from <flash/nand/core.h>.
* move remaining nand helper filesZachary T Welch2009-12-048-11/+9
| | | | Move remaining NAND implementation files into src/flash/nand/.
* split nand.c into nand/{core,fileio,tcl}.cZachary T Welch2009-12-047-872/+1005
| | | | | | | Moves commands into nand/tcl.c and core implementation to 'nand/core.c' and 'nand/fileio.c'. Eliminates 'flash/nand.c'. Adds 'nand/imp.h' to share routines between TCL commands and core.
* split NAND driver handling into nand/driver.[ch]Zachary T Welch2009-12-045-104/+205
| | | | | | | This work parallels the NOR directory, encapsulating the NAND drivers into a separate file. This takes an extra step by encapsulating the type of data structure used to manage the drivers, allowing it to be changed from an array to a dynamic list in the future.
* ARM: doc updates for main headerDavid Brownell2009-12-041-3/+11
| | | | Signed-off-by: David Brownell <dbrownell@users.sourceforge.net>
* ARM: rename armv4_5_build_reg_cache() as arm_*()David Brownell2009-12-046-11/+10
| | | | Signed-off-by: David Brownell <dbrownell@users.sourceforge.net>
* ARM: rename armv4_5_algorithm as arm_algorithmDavid Brownell2009-12-0411-27/+27
| | | | Signed-off-by: David Brownell <dbrownell@users.sourceforge.net>
* ARM: misc generic cleanupDavid Brownell2009-12-044-13/+28
| | | | | | | | | | | Remove an undesirable use of the CPSR symbol ... it needs to vanish. Flag mode-to-number stuff as obsolete; say why ... should also vanish. Get rid of no-longer-used mode and state typedefs. Comment a few of the implicit ties to "classic ARM". Signed-off-by: David Brownell <dbrownell@users.sourceforge.net>
* ARM: ARMV4_5_COMMON_MAGIC --> ARM_COMMON_MAGICDavid Brownell2009-12-0412-19/+19
| | | | Signed-off-by: David Brownell <dbrownell@users.sourceforge.net>
* ARM: switch target_to_armv4_5() to target_to_arm()David Brownell2009-12-048-20/+18
| | | | | | And remove that old symbol. Signed-off-by: David Brownell <dbrownell@users.sourceforge.net>
* ARM: rename armv4_5_state_* as arm_state_*David Brownell2009-12-0412-23/+23
| | | | | | And make arm_state_strings[] be const. Signed-off-by: David Brownell <dbrownell@users.sourceforge.net>
* ARM: rename armv4_5_mode_* AS arm_mode_*David Brownell2009-12-048-39/+39
| | | | Signed-off-by: David Brownell <dbrownell@users.sourceforge.net>
* ARM: rename ARMV4_5_MODE_* as ARM_MODE_*David Brownell2009-12-0416-141/+141
| | | | Signed-off-by: David Brownell <dbrownell@users.sourceforge.net>
* ARM: rename ARMV4_5_STATE_* as ARM_STATE_*David Brownell2009-12-0418-77/+77
| | | | Signed-off-by: David Brownell <dbrownell@users.sourceforge.net>
* ARM11: report watchpoint trigger insnDavid Brownell2009-12-041-0/+18
| | | | | | | As with Cortex-A8, the WFAR register holds useful information that should be recorded and, where relevant, displayed. Signed-off-by: David Brownell <dbrownell@users.sourceforge.net>
* ARM11: basic watchpoint supportDavid Brownell2009-12-044-9/+100
| | | | | | Use the DPM watchpoint support; remove old incomplete stubs. Signed-off-by: David Brownell <dbrownell@users.sourceforge.net>
* ARM11: tweak TAP ops and debuggingDavid Brownell2009-12-042-23/+61
| | | | | | | | | | | | | | | | | | Tweak scanchain 7 debug messaging: - show register addresses in decimal, matching ARM docs; - remove some pointless noise Avoid some needless roundtrips: - skip SCAN_N when SCREG already holds that number (speeds up polling and other common operations) - avoid zeroing vcr twice on resume Show the IR opcode as a label ("RESTART") too; and in decimal, matching ARM docs. Signed-off-by: David Brownell <dbrownell@users.sourceforge.net>
* reorder build order of src directoryZachary T Welch2009-12-041-1/+9
| | | | Descend into the library modules in order, from bottom-to-top.
* remove flash.h from treeZachary T Welch2009-12-0418-63/+4
| | | | | Remove the now vestigial <flash/flash.h> header from the tree, replacing a few references with <flash/nor/core.h>
* split flash.h into into flash/nor/*.hZachary T Welch2009-12-046-326/+358
| | | | | | | | | Move the bulk of the flash.h file into flash/nor/core.h, leaving an empty husk that will be removed in the next patch. The NOR driver structure is an implementation detail, so move it into its own private header file <flash/nor/driver.h> along with helper declaration for finding them by name.
* remove target.h from flash.hZachary T Welch2009-12-0421-20/+31
| | | | | The flash.h header does not require the target.h header file, but its implementation source files do. Move it to flash/nor/imp.h.
* split NOR and NAND flash headersZachary T Welch2009-12-044-12/+15
| | | | | Moves common flash errors to <flash/common.h> to decouple these two mostly unrelated trees of code.
* eliminate src/flash/flash.cZachary T Welch2009-12-043-221/+187
| | | | | Move remaining NOR flash implemenation into flash/nor/core.c Removes flash.c from the build, leaving only its header to split.
* add flash/nor/drivers.cZachary T Welch2009-12-044-55/+79
| | | | | Encapsulates access to the flash_drivers array, providing a base of operations for future dynamic driver module loading features.
* move more nor flash implementation detailsZachary T Welch2009-12-045-999/+1011
| | | | | | | | Splits the exec mode commands out of flash.c into the flash/nor/ files. The routines used by these high-level commands are moved into nor/core.c, with their internal declarations placed in nor/imp.h. Fixes distribution of <flash/nor/core.h> header.
* ARM: semihosting entry cleanupDavid Brownell2009-12-041-8/+39
| | | | | | | | | Clean up arm_semihosting() entry a bit, comment some issues and just which SVC opcodes are getting intercepted. Microcontroller profile cores will need a new entry, since they use BKPT instead (and don't have either SVC mode or an SPSR register). Signed-off-by: David Brownell <dbrownell@users.sourceforge.net>
* ARM: remove semihosting globalsDavid Brownell2009-12-045-33/+48
| | | | | | | | Store a flag and errno in in "struct arm". Have "poll" output report when semihosting is active. Shrink some of the affected lines. Signed-off-by: David Brownell <dbrownell@users.sourceforge.net>
* add flash/nor/core.[ch]Zachary T Welch2009-12-045-62/+149
| | | | | | | | | | | | | | | The newly moved flash TCL routines access the internals of the module too much. Fix the layering issues by adding new core NOR flash APIs: <flash/nor/core.h>: - flash_driver_find_by_name() - self-descriptive <flash/nor/imp.h>: - flash_bank_add() - encapsulates adding banks to bank list - flash_bank_list() - encapsulates retreiving bank list This allows the externs in flash/nor/imp.h to be removed, and these mechanisms may now be re-used by other flash module code.
* add flash/nor/{tcl.c,imp.h} from flash/flash.cZachary T Welch2009-12-044-175/+235
| | | | | | Moves the top-level 'flash' command handlers into flash/nor/tcl.c, with flash/nor/imp.h providing an internal implementation header to share non-public API components.
* separate Jim from jtag/core.cZachary T Welch2009-12-042-11/+11
| | | | | | After previous efforts, only one Jim routine remained in jtag/core.c, and moving it to jtag/tcl.c painlessly finishes separating these layers. The headers need separating, but the implementation is clean.
* switch 'rm' command away from using JimZachary T Welch2009-12-041-18/+11
| | | | | Commands that do not need to use Jim should be registered as high-level command handlers.
* check top-level command registrationsZachary T Welch2009-12-041-16/+34
| | | | | | | When calling module_register_commands, the return value needs to be checked for failures. Instead of duplicating code, use an array of function pointers to the identical registration functions to iterate over during startup.
* allow 'jtag init' to be run in any modeZachary T Welch2009-12-041-1/+1
| | | | Help alleviate further potential problems with interactive startup.
* target: cygwin build fixesDavid Brownell2009-12-042-4/+10
| | | | Signed-off-by: David Brownell <dbrownell@users.sourceforge.net>
* zy1000: FPGA revC wipØyvind Harboe2009-12-041-5/+19
| | | | | | | The bug in revC register memory access is pretty much cornered now. Signed-off-by: Øyvind Harboe <oyvind.harboe@zylin.com>
* basic ARM semihosting supportNicolas Pitre2009-12-034-0/+516
| | | | | | | | | | | | | | | | | | | | Semihosting enables code running on an ARM target to use the I/O facilities on the host computer. The target application must be linked against a library that forwards operation requests by using the SVC instruction that is trapped at the Supervisor Call vector by the debugger. The "hosted" library version provided with CodeSourcery's Sourcery G++ Lite for ARM EABI is one example. This is currently available for ARM9 processors, but any ARM variant should be able to support this with little additional work. Tested using binaries compiled with Sourcery G++ Lite 2009q1-161 and ARM RVCT 3.0. [dbrownell@users.sourceforge.net: doc tweaks, NEWS] Signed-off-by: Nicolas Pitre <nico@marvell.com> Signed-off-by: David Brownell <dbrownell@users.sourceforge.net>
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