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* Report correct core instruction state for ARMv/A targetsmlu2009-09-081-1/+1
| | | | git-svn-id: svn://svn.berlios.de/openocd/trunk@2678 b42882b7-edfa-0310-969c-e2dbd0fdcd60
* Load PC with bit 0 set to 1 when resuming to say in Thumb instruction state.mlu2009-09-081-2/+7
| | | | git-svn-id: svn://svn.berlios.de/openocd/trunk@2677 b42882b7-edfa-0310-969c-e2dbd0fdcd60
* David Brownell <david-b@pacbell.net> oharboe2009-09-081-0/+86
| | | | | | | | Provide an "armv7a disassemble" command. Current omissions include VFP (except as coprocessor instructions), Neon, and various Thumb2 opcodes that are not available in ARMv7-M processors. git-svn-id: svn://svn.berlios.de/openocd/trunk@2676 b42882b7-edfa-0310-969c-e2dbd0fdcd60
* David Brownell <david-b@pacbell.net> oharboe2009-09-081-35/+137
| | | | | | | | | | | | | | | | | | | | | lean up some loose ends with the ARM disassembler - Add a header comment describing its current state and uses and referencing the now-generally-available V7 arch spec - Support some mode switch instructions: * Thumb to Jazelle (BXJ) * Thumb to ThumbEE (ENTERX) * ThumbEE to Thumb (LEAVEX) - Improve that recent warning fix (and associated whitespace goof) - Declare the rest of the internal code and data "static". A compiler may use this, and it helps clarify the scope of these routines (e.g. what changes to them could affect). git-svn-id: svn://svn.berlios.de/openocd/trunk@2675 b42882b7-edfa-0310-969c-e2dbd0fdcd60
* Improved handling of instruction set state, helps for debugging Thumb state.mlu2009-09-071-7/+5
| | | | git-svn-id: svn://svn.berlios.de/openocd/trunk@2674 b42882b7-edfa-0310-969c-e2dbd0fdcd60
* Mahr, Stefan <Stefan.Mahr@sphairon.com> removes the endianness swapping in ↵oharboe2009-09-041-44/+0
| | | | | | mips_m4k.c Swapping is already done in target.c git-svn-id: svn://svn.berlios.de/openocd/trunk@2673 b42882b7-edfa-0310-969c-e2dbd0fdcd60
* Matt Hsu <matt@0xlab.org> This patch simply enables the halting debug mode.oharboe2009-09-041-0/+7
| | | | | | | By enabling this bit, the processor halts when a debug event such as breakpoint occurs. git-svn-id: svn://svn.berlios.de/openocd/trunk@2668 b42882b7-edfa-0310-969c-e2dbd0fdcd60
* more debug output for breakpointsoharboe2009-09-041-2/+10
| | | | git-svn-id: svn://svn.berlios.de/openocd/trunk@2667 b42882b7-edfa-0310-969c-e2dbd0fdcd60
* Matt Hsu <matt@0xlab.org> Tidy up the bit-offset operation for DSCR registeroharboe2009-09-042-6/+15
| | | | git-svn-id: svn://svn.berlios.de/openocd/trunk@2666 b42882b7-edfa-0310-969c-e2dbd0fdcd60
* David Brownelloharboe2009-09-036-74/+191
| | | | | | | | | | | | | | | | Abstract the orion_nand_fast_block_write() routine into a separate routine -- arm_nandwrite() -- so that other ARM cores can reuse it. Have davinci_nand do so. This faster than byte-at-a-time ops by a factor of three (!), even given the slowish interactions to support hardware ECC (1-bit flavor in that test) each 512 bytes; those could be read more efficiently by on-chip code. NOTE that until there's a generic "ARM algorithm" structure, this can't work on newer ARMv6 (like ARM1136) or ARMv7A (like Cortex-A8) cores, though the downloaded code itself would work just fine there. git-svn-id: svn://svn.berlios.de/openocd/trunk@2663 b42882b7-edfa-0310-969c-e2dbd0fdcd60
* - fixes the incorrect info msg displayed during stellaris flash programming.ntfreak2009-09-011-2/+2
| | | | git-svn-id: svn://svn.berlios.de/openocd/trunk@2660 b42882b7-edfa-0310-969c-e2dbd0fdcd60
* - fix a regression when using cortex_m3 emulated dcc channelntfreak2009-09-011-10/+19
| | | | git-svn-id: svn://svn.berlios.de/openocd/trunk@2659 b42882b7-edfa-0310-969c-e2dbd0fdcd60
* Warning fixduane2009-08-311-0/+3
| | | | git-svn-id: svn://svn.berlios.de/openocd/trunk@2658 b42882b7-edfa-0310-969c-e2dbd0fdcd60
* David Brownell <david-b@pacbell.net> Minor code bugfix: check right variable.oharboe2009-08-301-1/+1
| | | | | | | | | Via code review by Steve Grubb <sgrubb@redhat.com>  Almost innocuous; this is value is checked later, this check being wrong would make it check stack garbage. git-svn-id: svn://svn.berlios.de/openocd/trunk@2655 b42882b7-edfa-0310-969c-e2dbd0fdcd60
* Dirk Behme <dirk.behme@googlemail.com> Fix typo in help text. It has to be ↵oharboe2009-08-301-1/+1
| | | | | | 'production_test' instead of 'production' here. git-svn-id: svn://svn.berlios.de/openocd/trunk@2654 b42882b7-edfa-0310-969c-e2dbd0fdcd60
* David Brownell <david-b@pacbell.net> Fix Sandstorm revision checking: right ↵oharboe2009-08-301-1/+1
| | | | | | bits, right value! git-svn-id: svn://svn.berlios.de/openocd/trunk@2653 b42882b7-edfa-0310-969c-e2dbd0fdcd60
* David Brownell <david-b@pacbell.net> Remove duplicate check for flash write ↵oharboe2009-08-301-21/+19
| | | | | | | | | | | | status. Via code review by Steve Grubb <sgrubb@redhat.com>  Also minor fixes for the message from "fill": the byte count is unsigned, not signed; and more importantly, print the real number of bytes written git-svn-id: svn://svn.berlios.de/openocd/trunk@2652 b42882b7-edfa-0310-969c-e2dbd0fdcd60
* David Brownell <david-b@pacbell.net> start phasing out integers as target IDsoharboe2009-08-306-59/+54
| | | | git-svn-id: svn://svn.berlios.de/openocd/trunk@2650 b42882b7-edfa-0310-969c-e2dbd0fdcd60
* David Brownell <david-b@pacbell.net> Be sure the built-in search paths ↵oharboe2009-08-304-7/+8
| | | | | | | | | | | | always go *after* ones provided on the command line ... matching comment in add_default_dirs(). Without this it's impossible to use a private config file which happens to have the same name as an installed one. Say, because you're bugfixing a private copy... git-svn-id: svn://svn.berlios.de/openocd/trunk@2649 b42882b7-edfa-0310-969c-e2dbd0fdcd60
* David Brownell <david-b@pacbell.net> fix warningsoharboe2009-08-281-4/+8
| | | | git-svn-id: svn://svn.berlios.de/openocd/trunk@2648 b42882b7-edfa-0310-969c-e2dbd0fdcd60
* added arm11 timeout error messagesoharboe2009-08-283-11/+94
| | | | git-svn-id: svn://svn.berlios.de/openocd/trunk@2647 b42882b7-edfa-0310-969c-e2dbd0fdcd60
* restore ICE watchpoint registers when the *last* software breakpoint is removedoharboe2009-08-282-3/+23
| | | | git-svn-id: svn://svn.berlios.de/openocd/trunk@2646 b42882b7-edfa-0310-969c-e2dbd0fdcd60
* David Brownell <david-b@pacbell.net> ARM disassembly support for about five ↵oharboe2009-08-281-6/+345
| | | | | | | | | | | | | | | | | | dozen non-Thumb instructions that were added after ARMv5TE was defined: - ARMv5J "BXJ" (for Java/Jazelle) - ARMv6 "media" instructions (for OMAP2420, i.MX31, etc) Compile-tested. This might not set up the simulator right for the ARMv6 single step support; only BXJ branches though, and docs to support Jazelle branching are non-public (still, sigh). ARMv6 instructions known to be mis-handled by this disassembler include: UMAAL, LDREX, STREX, CPS, SETEND, RFE, SRS, MCRR2, MRRC2 git-svn-id: svn://svn.berlios.de/openocd/trunk@2644 b42882b7-edfa-0310-969c-e2dbd0fdcd60
* arm11 hardware step using simulation + breakpoint. Use "hardware_step ↵oharboe2009-08-271-19/+28
| | | | | | enable" command to revert to hardware stepping. Ideally we could retire the "hardware_step enable" command once we no longer believe it to be necessary. git-svn-id: svn://svn.berlios.de/openocd/trunk@2643 b42882b7-edfa-0310-969c-e2dbd0fdcd60
* arm11 single stepping wip - at least we know the next PC nowoharboe2009-08-271-0/+4
| | | | git-svn-id: svn://svn.berlios.de/openocd/trunk@2642 b42882b7-edfa-0310-969c-e2dbd0fdcd60
* arm11 single stepping wipoharboe2009-08-271-0/+101
| | | | git-svn-id: svn://svn.berlios.de/openocd/trunk@2641 b42882b7-edfa-0310-969c-e2dbd0fdcd60
* refactor arm simulator to allow arm11 code to use it as well - no observable ↵oharboe2009-08-272-49/+147
| | | | | | changes otherwise. git-svn-id: svn://svn.berlios.de/openocd/trunk@2640 b42882b7-edfa-0310-969c-e2dbd0fdcd60
* Matt Hsu <matt@0xlab.org> and Holger Hans Peter Freyther <zecke@selfish.org> ↵oharboe2009-08-261-5/+23
| | | | | | | | | cortex-a8: Wait for the CPU to be halted/started With DCCR we are asking the CPU to halt, we should wait until the CPU has halted before proceeding with the operation. git-svn-id: svn://svn.berlios.de/openocd/trunk@2638 b42882b7-edfa-0310-969c-e2dbd0fdcd60
* Matt Hsu <matt@0xlab.org> and Holger Hans Peter Freyther <zecke@selfish.org> ↵oharboe2009-08-261-1/+1
| | | | | | Print the value that the method didn't like git-svn-id: svn://svn.berlios.de/openocd/trunk@2637 b42882b7-edfa-0310-969c-e2dbd0fdcd60
* Matt Hsu <matt@0xlab.org> and Holger Hans Peter Freyther <zecke@selfish.org> ↵oharboe2009-08-261-1/+1
| | | | | | | | Only dap_ap_select when we are going to do a memory access in the fast reg case. git-svn-id: svn://svn.berlios.de/openocd/trunk@2636 b42882b7-edfa-0310-969c-e2dbd0fdcd60
* Matt Hsu <matt@0xlab.org> cortex-a8: Copy some more registers from the ↵oharboe2009-08-261-0/+8
| | | | | | documentation git-svn-id: svn://svn.berlios.de/openocd/trunk@2635 b42882b7-edfa-0310-969c-e2dbd0fdcd60
* Matt Hsu <matt@0xlab.org> cortex_a8_exec_opcode is writing the ARM ↵oharboe2009-08-261-1/+9
| | | | | | | | | | | instruction into the ITR register but it will only be executed when the DSCR[13] bit is set. The documentation is a bit weird as it classifies the DSCR as read-only but the pseudo code is writing to it as well. This is working on a beagleboard. git-svn-id: svn://svn.berlios.de/openocd/trunk@2634 b42882b7-edfa-0310-969c-e2dbd0fdcd60
* Matt Hsu <matt@0xlab.org> Wait for the DTRRX to be full before reading it. ↵oharboe2009-08-261-4/+9
| | | | | | Remove the trans_mode change as it is done in the mem_ap_read_atomic_u32 function. git-svn-id: svn://svn.berlios.de/openocd/trunk@2633 b42882b7-edfa-0310-969c-e2dbd0fdcd60
* Matt Hsu <matt@0xlab.org> and Holger Hans Peter Freyther <zecke@selfish.org> ↵oharboe2009-08-261-0/+8
| | | | | | | | | | Before executing a new instruction wait for the previous instruction to be finished. This comes from the pseudo code of the cortex a8 trm. git-svn-id: svn://svn.berlios.de/openocd/trunk@2632 b42882b7-edfa-0310-969c-e2dbd0fdcd60
* David Brownell <david-b@pacbell.net> Fix segv in jtag_examine_chain(): exit ↵oharboe2009-08-261-6/+8
| | | | | | | | | | | loop on no-tap. Keep "next iteration" step with the rest of the loop overhead. Cleanup: remove spurious whitespace, and an overlong line; only assign "tap->hasidcode" once. git-svn-id: svn://svn.berlios.de/openocd/trunk@2631 b42882b7-edfa-0310-969c-e2dbd0fdcd60
* added missing check on jtag_executeoharboe2009-08-261-1/+4
| | | | git-svn-id: svn://svn.berlios.de/openocd/trunk@2630 b42882b7-edfa-0310-969c-e2dbd0fdcd60
* Remove bogus "BUG:". If the PC is pointing to an invalid instruction, then ↵oharboe2009-08-261-2/+2
| | | | | | simulation will fail. This is expected. git-svn-id: svn://svn.berlios.de/openocd/trunk@2629 b42882b7-edfa-0310-969c-e2dbd0fdcd60
* reduce arm11 output noiseoharboe2009-08-262-3/+7
| | | | git-svn-id: svn://svn.berlios.de/openocd/trunk@2628 b42882b7-edfa-0310-969c-e2dbd0fdcd60
* David Brownell <david-b@pacbell.net> Clock updates/fixes for the Stellaris ↵oharboe2009-08-262-19/+143
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | flash driver: - Bugfixes: * internal osc: it's *12* MHz (not 15 MHz) on _current_ chips + except new Tempest parts where it's 16 MHz (and calibrated!) + or some old Sandstorm ones, where 15 MHz was valid * crystal config: + read and use the crystal config, don't assume 6 MHz + know when that field is 4 bits vs 5 * an RCC2 register may be overriding the original RCC + more clock source options + bigger dividers + fractional dividers on Tempest (NYET handled) * there's a 30 KHz osc on newer chips (for deep sleep) * there's a 32768 Hz osc on newer chips (for hibernation) - Cosmetic * say "rev A0" not "vA.0", to match vendor docs * don't always report master clock as an "estimate": + give the error bound if it's approximate, like "±30%" + else don't say anything * fix whitespace and caps in some messages * these are not AT91SAM chips!! Those clock issues might explain problems sometimes reported when writing to Stellaris flash banks; they affect write timings. That 12-vs-15 MHz issue is problematic; there's no consolidated doc showing which chips (and revs!) have which internal oscillator speed. It's clear that only older silicon had the faster-and-less-accurate flavor. What's less clear is which chips are "old" like that. Lightly tested, on a DustDevil part. git-svn-id: svn://svn.berlios.de/openocd/trunk@2626 b42882b7-edfa-0310-969c-e2dbd0fdcd60
* David Brownell <david-b@pacbell.net> Tweak disassembly commands:oharboe2009-08-252-28/+55
| | | | | | | | | | | | | | | | | | For ARMv4/ARMv5: - better command parameter error checking - don't require an instruction count; default to one - recognize thumb function addresses - make function static - shorten some too-long lines For Cortex-M3: - don't require an instruction count; default to one With the relevant doc updates. --- Nyet done: invoke the thumb2 disassembler on v4/v5, to better handle branch instructions. git-svn-id: svn://svn.berlios.de/openocd/trunk@2624 b42882b7-edfa-0310-969c-e2dbd0fdcd60
* David Brownell <david-b@pacbell.net> More jtag_add_reset() cleanup:oharboe2009-08-251-36/+23
| | | | | | | | | Unify the handling of the req_srst parameter, and rip out a large NOP branch and its associated FIXME. (There didn't seem to be anything that needs fixing; but that was unclear since the constraints were scattered all over the place not unified.) git-svn-id: svn://svn.berlios.de/openocd/trunk@2623 b42882b7-edfa-0310-969c-e2dbd0fdcd60
* David Brownell <david-b@pacbell.net> More jtag_add_reset() cleanup:oharboe2009-08-251-17/+18
| | | | | | | | Unify the handling of the req_tlr_or_trst parameter. Basically, JTAG TMS+TCK ops ("TLR") is always used ... unless TRST is a safe option in this system configuration. git-svn-id: svn://svn.berlios.de/openocd/trunk@2622 b42882b7-edfa-0310-969c-e2dbd0fdcd60
* David Brownell <david-b@pacbell.net> Some jtag_add_reset() cleanup:oharboe2009-08-251-42/+62
| | | | | | | | | | | | | | | | | | | | | | | - Track whether TRST and/or SRST actually change: * If they're not changing, don't ask the JTAG adapter to do anything! (JTAG TCK/TMS ops might still be used to enter TAP_RESET though.) * Don't change their recorded values until after the adapter says it did so ... so fault paths can't leave corrupt state. * Detect and report jtag_execute_queue() failure mode * Only emit messages saying what really changed; this includes adding an omitted "deasserted TRST" message. * Only apply delays after deasserting SRST/TRST if we *DID* deassert! - Messages say "TLR" not "RESET", to be less confusing; there are many kinds of reset. (Though "TLR" isn't quite ideal either, since it's the name of the TAP state being entered by TMS+TCK or TRST; it's at least non-ambiguous in context.) So the main effect is to do only the work this routine was told to do; and to have debug messaging make more sense. git-svn-id: svn://svn.berlios.de/openocd/trunk@2621 b42882b7-edfa-0310-969c-e2dbd0fdcd60
* David Brownell <david-b@pacbell.net> Accomodate targets which don't support ↵oharboe2009-08-251-0/+12
| | | | | | | | | | | | various target-specific reset operations. Maybe they can't; or it's a "not yet" thing. Note that the assert/deassert operations can't yet trigger for OMAP3 because resets currently include JTAG reset in all cases, resetting the ICEpick and thus disabling the TAP for Cortex-A8. git-svn-id: svn://svn.berlios.de/openocd/trunk@2620 b42882b7-edfa-0310-969c-e2dbd0fdcd60
* - fix build warningsntfreak2009-08-253-19/+19
| | | | | | - add svn props to recently added files armv7a.[ch] git-svn-id: svn://svn.berlios.de/openocd/trunk@2618 b42882b7-edfa-0310-969c-e2dbd0fdcd60
* Michael Schwingen <rincewind@discworld.dascon.de> a small CFI cleanupoharboe2009-08-253-6/+5
| | | | git-svn-id: svn://svn.berlios.de/openocd/trunk@2617 b42882b7-edfa-0310-969c-e2dbd0fdcd60
* strange.... the code build and links w/Linux GCC target but fails w/arm-elf. ↵oharboe2009-08-251-3/+3
| | | | | | The code was clearly broken as it was missing two extern's in the .h file... git-svn-id: svn://svn.berlios.de/openocd/trunk@2616 b42882b7-edfa-0310-969c-e2dbd0fdcd60
* Ferdinand Postema <ferdinand@postema.eu> fix warningsoharboe2009-08-251-2/+2
| | | | git-svn-id: svn://svn.berlios.de/openocd/trunk@2615 b42882b7-edfa-0310-969c-e2dbd0fdcd60
* Michael Schwingen <rincewind@discworld.dascon.de> The attached patch adds a ↵oharboe2009-08-251-0/+63
| | | | | | | | | "xscale vector_table" command that allows to set the values that are written in the mini-IC (plus documentation updates that describe why this is needed). git-svn-id: svn://svn.berlios.de/openocd/trunk@2613 b42882b7-edfa-0310-969c-e2dbd0fdcd60
* Audrius Urmanavičius <didele.deze@gmail.com> Latest source (R2606) does not ↵oharboe2009-08-251-1/+1
| | | | | | compile under Windows+Cygwin - fails with error about possibly uninitialized use of variable 'ch'. git-svn-id: svn://svn.berlios.de/openocd/trunk@2612 b42882b7-edfa-0310-969c-e2dbd0fdcd60
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