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* David Brownell <david-b@pacbell.net> Minor code bugfix: check right variable.oharboe2009-08-301-1/+1
| | | | | | | | | Via code review by Steve Grubb <sgrubb@redhat.com>  Almost innocuous; this is value is checked later, this check being wrong would make it check stack garbage. git-svn-id: svn://svn.berlios.de/openocd/trunk@2655 b42882b7-edfa-0310-969c-e2dbd0fdcd60
* Dirk Behme <dirk.behme@googlemail.com> Fix typo in help text. It has to be ↵oharboe2009-08-301-1/+1
| | | | | | 'production_test' instead of 'production' here. git-svn-id: svn://svn.berlios.de/openocd/trunk@2654 b42882b7-edfa-0310-969c-e2dbd0fdcd60
* David Brownell <david-b@pacbell.net> Fix Sandstorm revision checking: right ↵oharboe2009-08-301-1/+1
| | | | | | bits, right value! git-svn-id: svn://svn.berlios.de/openocd/trunk@2653 b42882b7-edfa-0310-969c-e2dbd0fdcd60
* David Brownell <david-b@pacbell.net> Remove duplicate check for flash write ↵oharboe2009-08-301-21/+19
| | | | | | | | | | | | status. Via code review by Steve Grubb <sgrubb@redhat.com>  Also minor fixes for the message from "fill": the byte count is unsigned, not signed; and more importantly, print the real number of bytes written git-svn-id: svn://svn.berlios.de/openocd/trunk@2652 b42882b7-edfa-0310-969c-e2dbd0fdcd60
* David Brownell <david-b@pacbell.net> start phasing out integers as target IDsoharboe2009-08-306-59/+54
| | | | git-svn-id: svn://svn.berlios.de/openocd/trunk@2650 b42882b7-edfa-0310-969c-e2dbd0fdcd60
* David Brownell <david-b@pacbell.net> Be sure the built-in search paths ↵oharboe2009-08-304-7/+8
| | | | | | | | | | | | always go *after* ones provided on the command line ... matching comment in add_default_dirs(). Without this it's impossible to use a private config file which happens to have the same name as an installed one. Say, because you're bugfixing a private copy... git-svn-id: svn://svn.berlios.de/openocd/trunk@2649 b42882b7-edfa-0310-969c-e2dbd0fdcd60
* David Brownell <david-b@pacbell.net> fix warningsoharboe2009-08-281-4/+8
| | | | git-svn-id: svn://svn.berlios.de/openocd/trunk@2648 b42882b7-edfa-0310-969c-e2dbd0fdcd60
* added arm11 timeout error messagesoharboe2009-08-283-11/+94
| | | | git-svn-id: svn://svn.berlios.de/openocd/trunk@2647 b42882b7-edfa-0310-969c-e2dbd0fdcd60
* restore ICE watchpoint registers when the *last* software breakpoint is removedoharboe2009-08-282-3/+23
| | | | git-svn-id: svn://svn.berlios.de/openocd/trunk@2646 b42882b7-edfa-0310-969c-e2dbd0fdcd60
* David Brownell <david-b@pacbell.net> ARM disassembly support for about five ↵oharboe2009-08-281-6/+345
| | | | | | | | | | | | | | | | | | dozen non-Thumb instructions that were added after ARMv5TE was defined: - ARMv5J "BXJ" (for Java/Jazelle) - ARMv6 "media" instructions (for OMAP2420, i.MX31, etc) Compile-tested. This might not set up the simulator right for the ARMv6 single step support; only BXJ branches though, and docs to support Jazelle branching are non-public (still, sigh). ARMv6 instructions known to be mis-handled by this disassembler include: UMAAL, LDREX, STREX, CPS, SETEND, RFE, SRS, MCRR2, MRRC2 git-svn-id: svn://svn.berlios.de/openocd/trunk@2644 b42882b7-edfa-0310-969c-e2dbd0fdcd60
* arm11 hardware step using simulation + breakpoint. Use "hardware_step ↵oharboe2009-08-271-19/+28
| | | | | | enable" command to revert to hardware stepping. Ideally we could retire the "hardware_step enable" command once we no longer believe it to be necessary. git-svn-id: svn://svn.berlios.de/openocd/trunk@2643 b42882b7-edfa-0310-969c-e2dbd0fdcd60
* arm11 single stepping wip - at least we know the next PC nowoharboe2009-08-271-0/+4
| | | | git-svn-id: svn://svn.berlios.de/openocd/trunk@2642 b42882b7-edfa-0310-969c-e2dbd0fdcd60
* arm11 single stepping wipoharboe2009-08-271-0/+101
| | | | git-svn-id: svn://svn.berlios.de/openocd/trunk@2641 b42882b7-edfa-0310-969c-e2dbd0fdcd60
* refactor arm simulator to allow arm11 code to use it as well - no observable ↵oharboe2009-08-272-49/+147
| | | | | | changes otherwise. git-svn-id: svn://svn.berlios.de/openocd/trunk@2640 b42882b7-edfa-0310-969c-e2dbd0fdcd60
* Matt Hsu <matt@0xlab.org> and Holger Hans Peter Freyther <zecke@selfish.org> ↵oharboe2009-08-261-5/+23
| | | | | | | | | cortex-a8: Wait for the CPU to be halted/started With DCCR we are asking the CPU to halt, we should wait until the CPU has halted before proceeding with the operation. git-svn-id: svn://svn.berlios.de/openocd/trunk@2638 b42882b7-edfa-0310-969c-e2dbd0fdcd60
* Matt Hsu <matt@0xlab.org> and Holger Hans Peter Freyther <zecke@selfish.org> ↵oharboe2009-08-261-1/+1
| | | | | | Print the value that the method didn't like git-svn-id: svn://svn.berlios.de/openocd/trunk@2637 b42882b7-edfa-0310-969c-e2dbd0fdcd60
* Matt Hsu <matt@0xlab.org> and Holger Hans Peter Freyther <zecke@selfish.org> ↵oharboe2009-08-261-1/+1
| | | | | | | | Only dap_ap_select when we are going to do a memory access in the fast reg case. git-svn-id: svn://svn.berlios.de/openocd/trunk@2636 b42882b7-edfa-0310-969c-e2dbd0fdcd60
* Matt Hsu <matt@0xlab.org> cortex-a8: Copy some more registers from the ↵oharboe2009-08-261-0/+8
| | | | | | documentation git-svn-id: svn://svn.berlios.de/openocd/trunk@2635 b42882b7-edfa-0310-969c-e2dbd0fdcd60
* Matt Hsu <matt@0xlab.org> cortex_a8_exec_opcode is writing the ARM ↵oharboe2009-08-261-1/+9
| | | | | | | | | | | instruction into the ITR register but it will only be executed when the DSCR[13] bit is set. The documentation is a bit weird as it classifies the DSCR as read-only but the pseudo code is writing to it as well. This is working on a beagleboard. git-svn-id: svn://svn.berlios.de/openocd/trunk@2634 b42882b7-edfa-0310-969c-e2dbd0fdcd60
* Matt Hsu <matt@0xlab.org> Wait for the DTRRX to be full before reading it. ↵oharboe2009-08-261-4/+9
| | | | | | Remove the trans_mode change as it is done in the mem_ap_read_atomic_u32 function. git-svn-id: svn://svn.berlios.de/openocd/trunk@2633 b42882b7-edfa-0310-969c-e2dbd0fdcd60
* Matt Hsu <matt@0xlab.org> and Holger Hans Peter Freyther <zecke@selfish.org> ↵oharboe2009-08-261-0/+8
| | | | | | | | | | Before executing a new instruction wait for the previous instruction to be finished. This comes from the pseudo code of the cortex a8 trm. git-svn-id: svn://svn.berlios.de/openocd/trunk@2632 b42882b7-edfa-0310-969c-e2dbd0fdcd60
* David Brownell <david-b@pacbell.net> Fix segv in jtag_examine_chain(): exit ↵oharboe2009-08-261-6/+8
| | | | | | | | | | | loop on no-tap. Keep "next iteration" step with the rest of the loop overhead. Cleanup: remove spurious whitespace, and an overlong line; only assign "tap->hasidcode" once. git-svn-id: svn://svn.berlios.de/openocd/trunk@2631 b42882b7-edfa-0310-969c-e2dbd0fdcd60
* added missing check on jtag_executeoharboe2009-08-261-1/+4
| | | | git-svn-id: svn://svn.berlios.de/openocd/trunk@2630 b42882b7-edfa-0310-969c-e2dbd0fdcd60
* Remove bogus "BUG:". If the PC is pointing to an invalid instruction, then ↵oharboe2009-08-261-2/+2
| | | | | | simulation will fail. This is expected. git-svn-id: svn://svn.berlios.de/openocd/trunk@2629 b42882b7-edfa-0310-969c-e2dbd0fdcd60
* reduce arm11 output noiseoharboe2009-08-262-3/+7
| | | | git-svn-id: svn://svn.berlios.de/openocd/trunk@2628 b42882b7-edfa-0310-969c-e2dbd0fdcd60
* David Brownell <david-b@pacbell.net> Clock updates/fixes for the Stellaris ↵oharboe2009-08-262-19/+143
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | flash driver: - Bugfixes: * internal osc: it's *12* MHz (not 15 MHz) on _current_ chips + except new Tempest parts where it's 16 MHz (and calibrated!) + or some old Sandstorm ones, where 15 MHz was valid * crystal config: + read and use the crystal config, don't assume 6 MHz + know when that field is 4 bits vs 5 * an RCC2 register may be overriding the original RCC + more clock source options + bigger dividers + fractional dividers on Tempest (NYET handled) * there's a 30 KHz osc on newer chips (for deep sleep) * there's a 32768 Hz osc on newer chips (for hibernation) - Cosmetic * say "rev A0" not "vA.0", to match vendor docs * don't always report master clock as an "estimate": + give the error bound if it's approximate, like "±30%" + else don't say anything * fix whitespace and caps in some messages * these are not AT91SAM chips!! Those clock issues might explain problems sometimes reported when writing to Stellaris flash banks; they affect write timings. That 12-vs-15 MHz issue is problematic; there's no consolidated doc showing which chips (and revs!) have which internal oscillator speed. It's clear that only older silicon had the faster-and-less-accurate flavor. What's less clear is which chips are "old" like that. Lightly tested, on a DustDevil part. git-svn-id: svn://svn.berlios.de/openocd/trunk@2626 b42882b7-edfa-0310-969c-e2dbd0fdcd60
* David Brownell <david-b@pacbell.net> Tweak disassembly commands:oharboe2009-08-252-28/+55
| | | | | | | | | | | | | | | | | | For ARMv4/ARMv5: - better command parameter error checking - don't require an instruction count; default to one - recognize thumb function addresses - make function static - shorten some too-long lines For Cortex-M3: - don't require an instruction count; default to one With the relevant doc updates. --- Nyet done: invoke the thumb2 disassembler on v4/v5, to better handle branch instructions. git-svn-id: svn://svn.berlios.de/openocd/trunk@2624 b42882b7-edfa-0310-969c-e2dbd0fdcd60
* David Brownell <david-b@pacbell.net> More jtag_add_reset() cleanup:oharboe2009-08-251-36/+23
| | | | | | | | | Unify the handling of the req_srst parameter, and rip out a large NOP branch and its associated FIXME. (There didn't seem to be anything that needs fixing; but that was unclear since the constraints were scattered all over the place not unified.) git-svn-id: svn://svn.berlios.de/openocd/trunk@2623 b42882b7-edfa-0310-969c-e2dbd0fdcd60
* David Brownell <david-b@pacbell.net> More jtag_add_reset() cleanup:oharboe2009-08-251-17/+18
| | | | | | | | Unify the handling of the req_tlr_or_trst parameter. Basically, JTAG TMS+TCK ops ("TLR") is always used ... unless TRST is a safe option in this system configuration. git-svn-id: svn://svn.berlios.de/openocd/trunk@2622 b42882b7-edfa-0310-969c-e2dbd0fdcd60
* David Brownell <david-b@pacbell.net> Some jtag_add_reset() cleanup:oharboe2009-08-251-42/+62
| | | | | | | | | | | | | | | | | | | | | | | - Track whether TRST and/or SRST actually change: * If they're not changing, don't ask the JTAG adapter to do anything! (JTAG TCK/TMS ops might still be used to enter TAP_RESET though.) * Don't change their recorded values until after the adapter says it did so ... so fault paths can't leave corrupt state. * Detect and report jtag_execute_queue() failure mode * Only emit messages saying what really changed; this includes adding an omitted "deasserted TRST" message. * Only apply delays after deasserting SRST/TRST if we *DID* deassert! - Messages say "TLR" not "RESET", to be less confusing; there are many kinds of reset. (Though "TLR" isn't quite ideal either, since it's the name of the TAP state being entered by TMS+TCK or TRST; it's at least non-ambiguous in context.) So the main effect is to do only the work this routine was told to do; and to have debug messaging make more sense. git-svn-id: svn://svn.berlios.de/openocd/trunk@2621 b42882b7-edfa-0310-969c-e2dbd0fdcd60
* David Brownell <david-b@pacbell.net> Accomodate targets which don't support ↵oharboe2009-08-251-0/+12
| | | | | | | | | | | | various target-specific reset operations. Maybe they can't; or it's a "not yet" thing. Note that the assert/deassert operations can't yet trigger for OMAP3 because resets currently include JTAG reset in all cases, resetting the ICEpick and thus disabling the TAP for Cortex-A8. git-svn-id: svn://svn.berlios.de/openocd/trunk@2620 b42882b7-edfa-0310-969c-e2dbd0fdcd60
* - fix build warningsntfreak2009-08-253-19/+19
| | | | | | - add svn props to recently added files armv7a.[ch] git-svn-id: svn://svn.berlios.de/openocd/trunk@2618 b42882b7-edfa-0310-969c-e2dbd0fdcd60
* Michael Schwingen <rincewind@discworld.dascon.de> a small CFI cleanupoharboe2009-08-253-6/+5
| | | | git-svn-id: svn://svn.berlios.de/openocd/trunk@2617 b42882b7-edfa-0310-969c-e2dbd0fdcd60
* strange.... the code build and links w/Linux GCC target but fails w/arm-elf. ↵oharboe2009-08-251-3/+3
| | | | | | The code was clearly broken as it was missing two extern's in the .h file... git-svn-id: svn://svn.berlios.de/openocd/trunk@2616 b42882b7-edfa-0310-969c-e2dbd0fdcd60
* Ferdinand Postema <ferdinand@postema.eu> fix warningsoharboe2009-08-251-2/+2
| | | | git-svn-id: svn://svn.berlios.de/openocd/trunk@2615 b42882b7-edfa-0310-969c-e2dbd0fdcd60
* Michael Schwingen <rincewind@discworld.dascon.de> The attached patch adds a ↵oharboe2009-08-251-0/+63
| | | | | | | | | "xscale vector_table" command that allows to set the values that are written in the mini-IC (plus documentation updates that describe why this is needed). git-svn-id: svn://svn.berlios.de/openocd/trunk@2613 b42882b7-edfa-0310-969c-e2dbd0fdcd60
* Audrius Urmanavičius <didele.deze@gmail.com> Latest source (R2606) does not ↵oharboe2009-08-251-1/+1
| | | | | | compile under Windows+Cygwin - fails with error about possibly uninitialized use of variable 'ch'. git-svn-id: svn://svn.berlios.de/openocd/trunk@2612 b42882b7-edfa-0310-969c-e2dbd0fdcd60
* David Brownell The rest of the Cortex-A8 support from Magnus: replace the ↵oharboe2009-08-252-88/+1358
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | previous nonfunctional cortex_a8 code with something that at least basically works (for halt/step/resume, without MMU) even if it is incomplete. (With tweaks from Øyvind, and cleanup from Dave.) This code has mainly been developed and tested against R1606, it has been built and tested against R2294 where it runs but step and resume commands are broken due to regression (which should be fixed now). This code is really written for OMAP3530. It doesn't identify debug resources using generic DAP calls to scan the ROM table, or perform topology detection. The OMAP3530 DAP exposes two memory access ports: - Port #0 is connected to L3 interconnect (the main bus) with passthrough to the L4 EMU bus ... so it will be used for most memory accesses. - Port #1 is connected to a dedicated debug bus (L4 EMU), with access to L4 Wakeup, and holds the ROM table ... so it must be used for most debug and control operations. The are some defines to handle this in cortex_a8.c, which should be replaced with more general code. Having access to another Cortex-A8 implementation would help get that right. git-svn-id: svn://svn.berlios.de/openocd/trunk@2609 b42882b7-edfa-0310-969c-e2dbd0fdcd60
* David Brownell Subset of Cortex-A8 support from Magnus: create an armv7a fileoharboe2009-08-253-0/+479
| | | | | | | | | | | | | | | | | | | and seed it with DAP access support using the current ADIv5 code. (With tweaks and cleanup from Øyvind and Dave.) The ARMv7-AR architecture manual is not publicly available (even in subset form like the ARMv7-M spec), so it's hard to distinguish between the Cortex-A8 implementation and the ARMv7-A architecture. The register set presumably is architectural, and so it's stored here; it's like earlier ARMs, with small additions. Ditto the instruction set, though Thumb2 support is used (extending Thumb support from ARMv6 with more 32-bit instructions) and there's this ThumbEE thing too. There is a new "debug monitor" mode, not yet fully addressed here, to support debugging in environments (like motor control) where halting debug mode is inadvisable. git-svn-id: svn://svn.berlios.de/openocd/trunk@2608 b42882b7-edfa-0310-969c-e2dbd0fdcd60
* add missing isblank() for eCosoharboe2009-08-251-0/+2
| | | | git-svn-id: svn://svn.berlios.de/openocd/trunk@2607 b42882b7-edfa-0310-969c-e2dbd0fdcd60
* Steve Grubb <sgrubb@redhat.com> fix various and sundry leaksoharboe2009-08-247-0/+39
| | | | git-svn-id: svn://svn.berlios.de/openocd/trunk@2606 b42882b7-edfa-0310-969c-e2dbd0fdcd60
* Jonas Horberg <jhorberg@sauer-danfoss.com> oharboe2009-08-241-3/+2
| | | | | | | | The trunk is currently broken for interfaces without the speed_div function (interface specific clock speed value to kHz conversion). Example: parport. git-svn-id: svn://svn.berlios.de/openocd/trunk@2605 b42882b7-edfa-0310-969c-e2dbd0fdcd60
* Florian Boor <florian.boor@kernelconcepts.de> fixes a segfault executing ↵oharboe2009-08-211-1/+1
| | | | | | | | | commands from the web interface using the "Run Command" tab. git-svn-id: svn://svn.berlios.de/openocd/trunk@2601 b42882b7-edfa-0310-969c-e2dbd0fdcd60
* Piotr Ziecik <kosmo@semihalf.com> This patch adds handling blank characters ↵oharboe2009-08-201-59/+38
| | | | | | | | | between hex digits in SVF file, making OpenOCD compatible with files generated by Altera Quatrus II 9.0. git-svn-id: svn://svn.berlios.de/openocd/trunk@2600 b42882b7-edfa-0310-969c-e2dbd0fdcd60
* - remove enable-ft2232-highspeed configure option, high speed ftdi support ↵ntfreak2009-08-201-12/+19
| | | | | | | | is now detected during the configure stage - warning now issued if high speed ftdi device found and openocd was built using an old driver git-svn-id: svn://svn.berlios.de/openocd/trunk@2599 b42882b7-edfa-0310-969c-e2dbd0fdcd60
* David Brownell <david-b@pacbell.net>More Thumb2 disassembly:oharboe2009-08-201-2/+136
| | | | | | | | | | | | | | | ARMv7-M: A5.3.6 Load/store dual or exclusive, table branch GCC will generate the table branch instructions, usually with inlined tables that will confuse this disassembler. LDREX and STREX are not issued by GCC without inline assembly. This means all Thumb2 instructions implemented by Cortex-M3 can now be disassembled. Cortex-A8 cores support more Thumb2 instructions, but most of those aren't yet publicly documented. git-svn-id: svn://svn.berlios.de/openocd/trunk@2598 b42882b7-edfa-0310-969c-e2dbd0fdcd60
* Jonas Horberg [jhorberg@sauer-danfoss.com]:ntfreak2009-08-191-1/+1
| | | | | | Fix small typo in ftd2xx type detection git-svn-id: svn://svn.berlios.de/openocd/trunk@2597 b42882b7-edfa-0310-969c-e2dbd0fdcd60
* David Brownell <david-b@pacbell.net>Fix some command helptext:oharboe2009-08-191-4/+13
| | | | | | | | | - spell "address" right - list bp/wp params as optional And make those source lines wrap at sane margins. git-svn-id: svn://svn.berlios.de/openocd/trunk@2596 b42882b7-edfa-0310-969c-e2dbd0fdcd60
* David Brownell <david-b@pacbell.net> Clean up some Cortex-M3 reset handling.oharboe2009-08-191-17/+39
| | | | | | | | | | | | | | - AIRCR_SYSRESETREQ is generic; use it on any system where SRST won't fly, not just on Stellaris-based ones. - Reformat and improve comments about the Stellaris quirk; and xref the only public docs (an email) about the issue. It seems that *most* Stellaris chips have this problem. Tempest parts aren't yet in general sampling; and if rev B silicon for earlier chips exists, it's not very visible yet. git-svn-id: svn://svn.berlios.de/openocd/trunk@2595 b42882b7-edfa-0310-969c-e2dbd0fdcd60
* David Brownell [david-b@pacbell.net]:ntfreak2009-08-181-10/+21
| | | | | | | | | | | | | Simplify dumping of register lists by only printing cached values if they are marked as valid. Most of the time, they are invalid; so printing *any* value is just misleading. Note that for ARM7 and ARM9 most EmbeddedICE registers (except for debug status) could be cached most of the time; and their register cache isn't maintained properly (many accesses seem to bypass that cache code). git-svn-id: svn://svn.berlios.de/openocd/trunk@2594 b42882b7-edfa-0310-969c-e2dbd0fdcd60
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