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* Matt Hsu <matt@0xlab.org> and Holger Hans Peter Freyther <zecke@selfish.org> ↵oharboe2009-08-261-0/+8
| | | | | | | | | | Before executing a new instruction wait for the previous instruction to be finished. This comes from the pseudo code of the cortex a8 trm. git-svn-id: svn://svn.berlios.de/openocd/trunk@2632 b42882b7-edfa-0310-969c-e2dbd0fdcd60
* David Brownell <david-b@pacbell.net> Fix segv in jtag_examine_chain(): exit ↵oharboe2009-08-261-6/+8
| | | | | | | | | | | loop on no-tap. Keep "next iteration" step with the rest of the loop overhead. Cleanup: remove spurious whitespace, and an overlong line; only assign "tap->hasidcode" once. git-svn-id: svn://svn.berlios.de/openocd/trunk@2631 b42882b7-edfa-0310-969c-e2dbd0fdcd60
* added missing check on jtag_executeoharboe2009-08-261-1/+4
| | | | git-svn-id: svn://svn.berlios.de/openocd/trunk@2630 b42882b7-edfa-0310-969c-e2dbd0fdcd60
* Remove bogus "BUG:". If the PC is pointing to an invalid instruction, then ↵oharboe2009-08-261-2/+2
| | | | | | simulation will fail. This is expected. git-svn-id: svn://svn.berlios.de/openocd/trunk@2629 b42882b7-edfa-0310-969c-e2dbd0fdcd60
* reduce arm11 output noiseoharboe2009-08-262-3/+7
| | | | git-svn-id: svn://svn.berlios.de/openocd/trunk@2628 b42882b7-edfa-0310-969c-e2dbd0fdcd60
* David Brownell <david-b@pacbell.net> Clock updates/fixes for the Stellaris ↵oharboe2009-08-262-19/+143
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | flash driver: - Bugfixes: * internal osc: it's *12* MHz (not 15 MHz) on _current_ chips + except new Tempest parts where it's 16 MHz (and calibrated!) + or some old Sandstorm ones, where 15 MHz was valid * crystal config: + read and use the crystal config, don't assume 6 MHz + know when that field is 4 bits vs 5 * an RCC2 register may be overriding the original RCC + more clock source options + bigger dividers + fractional dividers on Tempest (NYET handled) * there's a 30 KHz osc on newer chips (for deep sleep) * there's a 32768 Hz osc on newer chips (for hibernation) - Cosmetic * say "rev A0" not "vA.0", to match vendor docs * don't always report master clock as an "estimate": + give the error bound if it's approximate, like "±30%" + else don't say anything * fix whitespace and caps in some messages * these are not AT91SAM chips!! Those clock issues might explain problems sometimes reported when writing to Stellaris flash banks; they affect write timings. That 12-vs-15 MHz issue is problematic; there's no consolidated doc showing which chips (and revs!) have which internal oscillator speed. It's clear that only older silicon had the faster-and-less-accurate flavor. What's less clear is which chips are "old" like that. Lightly tested, on a DustDevil part. git-svn-id: svn://svn.berlios.de/openocd/trunk@2626 b42882b7-edfa-0310-969c-e2dbd0fdcd60
* David Brownell <david-b@pacbell.net> Tweak disassembly commands:oharboe2009-08-252-28/+55
| | | | | | | | | | | | | | | | | | For ARMv4/ARMv5: - better command parameter error checking - don't require an instruction count; default to one - recognize thumb function addresses - make function static - shorten some too-long lines For Cortex-M3: - don't require an instruction count; default to one With the relevant doc updates. --- Nyet done: invoke the thumb2 disassembler on v4/v5, to better handle branch instructions. git-svn-id: svn://svn.berlios.de/openocd/trunk@2624 b42882b7-edfa-0310-969c-e2dbd0fdcd60
* David Brownell <david-b@pacbell.net> More jtag_add_reset() cleanup:oharboe2009-08-251-36/+23
| | | | | | | | | Unify the handling of the req_srst parameter, and rip out a large NOP branch and its associated FIXME. (There didn't seem to be anything that needs fixing; but that was unclear since the constraints were scattered all over the place not unified.) git-svn-id: svn://svn.berlios.de/openocd/trunk@2623 b42882b7-edfa-0310-969c-e2dbd0fdcd60
* David Brownell <david-b@pacbell.net> More jtag_add_reset() cleanup:oharboe2009-08-251-17/+18
| | | | | | | | Unify the handling of the req_tlr_or_trst parameter. Basically, JTAG TMS+TCK ops ("TLR") is always used ... unless TRST is a safe option in this system configuration. git-svn-id: svn://svn.berlios.de/openocd/trunk@2622 b42882b7-edfa-0310-969c-e2dbd0fdcd60
* David Brownell <david-b@pacbell.net> Some jtag_add_reset() cleanup:oharboe2009-08-251-42/+62
| | | | | | | | | | | | | | | | | | | | | | | - Track whether TRST and/or SRST actually change: * If they're not changing, don't ask the JTAG adapter to do anything! (JTAG TCK/TMS ops might still be used to enter TAP_RESET though.) * Don't change their recorded values until after the adapter says it did so ... so fault paths can't leave corrupt state. * Detect and report jtag_execute_queue() failure mode * Only emit messages saying what really changed; this includes adding an omitted "deasserted TRST" message. * Only apply delays after deasserting SRST/TRST if we *DID* deassert! - Messages say "TLR" not "RESET", to be less confusing; there are many kinds of reset. (Though "TLR" isn't quite ideal either, since it's the name of the TAP state being entered by TMS+TCK or TRST; it's at least non-ambiguous in context.) So the main effect is to do only the work this routine was told to do; and to have debug messaging make more sense. git-svn-id: svn://svn.berlios.de/openocd/trunk@2621 b42882b7-edfa-0310-969c-e2dbd0fdcd60
* David Brownell <david-b@pacbell.net> Accomodate targets which don't support ↵oharboe2009-08-251-0/+12
| | | | | | | | | | | | various target-specific reset operations. Maybe they can't; or it's a "not yet" thing. Note that the assert/deassert operations can't yet trigger for OMAP3 because resets currently include JTAG reset in all cases, resetting the ICEpick and thus disabling the TAP for Cortex-A8. git-svn-id: svn://svn.berlios.de/openocd/trunk@2620 b42882b7-edfa-0310-969c-e2dbd0fdcd60
* - fix build warningsntfreak2009-08-253-19/+19
| | | | | | - add svn props to recently added files armv7a.[ch] git-svn-id: svn://svn.berlios.de/openocd/trunk@2618 b42882b7-edfa-0310-969c-e2dbd0fdcd60
* Michael Schwingen <rincewind@discworld.dascon.de> a small CFI cleanupoharboe2009-08-253-6/+5
| | | | git-svn-id: svn://svn.berlios.de/openocd/trunk@2617 b42882b7-edfa-0310-969c-e2dbd0fdcd60
* strange.... the code build and links w/Linux GCC target but fails w/arm-elf. ↵oharboe2009-08-251-3/+3
| | | | | | The code was clearly broken as it was missing two extern's in the .h file... git-svn-id: svn://svn.berlios.de/openocd/trunk@2616 b42882b7-edfa-0310-969c-e2dbd0fdcd60
* Ferdinand Postema <ferdinand@postema.eu> fix warningsoharboe2009-08-251-2/+2
| | | | git-svn-id: svn://svn.berlios.de/openocd/trunk@2615 b42882b7-edfa-0310-969c-e2dbd0fdcd60
* Michael Schwingen <rincewind@discworld.dascon.de> The attached patch adds a ↵oharboe2009-08-251-0/+63
| | | | | | | | | "xscale vector_table" command that allows to set the values that are written in the mini-IC (plus documentation updates that describe why this is needed). git-svn-id: svn://svn.berlios.de/openocd/trunk@2613 b42882b7-edfa-0310-969c-e2dbd0fdcd60
* Audrius Urmanavičius <didele.deze@gmail.com> Latest source (R2606) does not ↵oharboe2009-08-251-1/+1
| | | | | | compile under Windows+Cygwin - fails with error about possibly uninitialized use of variable 'ch'. git-svn-id: svn://svn.berlios.de/openocd/trunk@2612 b42882b7-edfa-0310-969c-e2dbd0fdcd60
* David Brownell The rest of the Cortex-A8 support from Magnus: replace the ↵oharboe2009-08-252-88/+1358
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | previous nonfunctional cortex_a8 code with something that at least basically works (for halt/step/resume, without MMU) even if it is incomplete. (With tweaks from Øyvind, and cleanup from Dave.) This code has mainly been developed and tested against R1606, it has been built and tested against R2294 where it runs but step and resume commands are broken due to regression (which should be fixed now). This code is really written for OMAP3530. It doesn't identify debug resources using generic DAP calls to scan the ROM table, or perform topology detection. The OMAP3530 DAP exposes two memory access ports: - Port #0 is connected to L3 interconnect (the main bus) with passthrough to the L4 EMU bus ... so it will be used for most memory accesses. - Port #1 is connected to a dedicated debug bus (L4 EMU), with access to L4 Wakeup, and holds the ROM table ... so it must be used for most debug and control operations. The are some defines to handle this in cortex_a8.c, which should be replaced with more general code. Having access to another Cortex-A8 implementation would help get that right. git-svn-id: svn://svn.berlios.de/openocd/trunk@2609 b42882b7-edfa-0310-969c-e2dbd0fdcd60
* David Brownell Subset of Cortex-A8 support from Magnus: create an armv7a fileoharboe2009-08-253-0/+479
| | | | | | | | | | | | | | | | | | | and seed it with DAP access support using the current ADIv5 code. (With tweaks and cleanup from Øyvind and Dave.) The ARMv7-AR architecture manual is not publicly available (even in subset form like the ARMv7-M spec), so it's hard to distinguish between the Cortex-A8 implementation and the ARMv7-A architecture. The register set presumably is architectural, and so it's stored here; it's like earlier ARMs, with small additions. Ditto the instruction set, though Thumb2 support is used (extending Thumb support from ARMv6 with more 32-bit instructions) and there's this ThumbEE thing too. There is a new "debug monitor" mode, not yet fully addressed here, to support debugging in environments (like motor control) where halting debug mode is inadvisable. git-svn-id: svn://svn.berlios.de/openocd/trunk@2608 b42882b7-edfa-0310-969c-e2dbd0fdcd60
* add missing isblank() for eCosoharboe2009-08-251-0/+2
| | | | git-svn-id: svn://svn.berlios.de/openocd/trunk@2607 b42882b7-edfa-0310-969c-e2dbd0fdcd60
* Steve Grubb <sgrubb@redhat.com> fix various and sundry leaksoharboe2009-08-247-0/+39
| | | | git-svn-id: svn://svn.berlios.de/openocd/trunk@2606 b42882b7-edfa-0310-969c-e2dbd0fdcd60
* Jonas Horberg <jhorberg@sauer-danfoss.com> oharboe2009-08-241-3/+2
| | | | | | | | The trunk is currently broken for interfaces without the speed_div function (interface specific clock speed value to kHz conversion). Example: parport. git-svn-id: svn://svn.berlios.de/openocd/trunk@2605 b42882b7-edfa-0310-969c-e2dbd0fdcd60
* Florian Boor <florian.boor@kernelconcepts.de> fixes a segfault executing ↵oharboe2009-08-211-1/+1
| | | | | | | | | commands from the web interface using the "Run Command" tab. git-svn-id: svn://svn.berlios.de/openocd/trunk@2601 b42882b7-edfa-0310-969c-e2dbd0fdcd60
* Piotr Ziecik <kosmo@semihalf.com> This patch adds handling blank characters ↵oharboe2009-08-201-59/+38
| | | | | | | | | between hex digits in SVF file, making OpenOCD compatible with files generated by Altera Quatrus II 9.0. git-svn-id: svn://svn.berlios.de/openocd/trunk@2600 b42882b7-edfa-0310-969c-e2dbd0fdcd60
* - remove enable-ft2232-highspeed configure option, high speed ftdi support ↵ntfreak2009-08-201-12/+19
| | | | | | | | is now detected during the configure stage - warning now issued if high speed ftdi device found and openocd was built using an old driver git-svn-id: svn://svn.berlios.de/openocd/trunk@2599 b42882b7-edfa-0310-969c-e2dbd0fdcd60
* David Brownell <david-b@pacbell.net>More Thumb2 disassembly:oharboe2009-08-201-2/+136
| | | | | | | | | | | | | | | ARMv7-M: A5.3.6 Load/store dual or exclusive, table branch GCC will generate the table branch instructions, usually with inlined tables that will confuse this disassembler. LDREX and STREX are not issued by GCC without inline assembly. This means all Thumb2 instructions implemented by Cortex-M3 can now be disassembled. Cortex-A8 cores support more Thumb2 instructions, but most of those aren't yet publicly documented. git-svn-id: svn://svn.berlios.de/openocd/trunk@2598 b42882b7-edfa-0310-969c-e2dbd0fdcd60
* Jonas Horberg [jhorberg@sauer-danfoss.com]:ntfreak2009-08-191-1/+1
| | | | | | Fix small typo in ftd2xx type detection git-svn-id: svn://svn.berlios.de/openocd/trunk@2597 b42882b7-edfa-0310-969c-e2dbd0fdcd60
* David Brownell <david-b@pacbell.net>Fix some command helptext:oharboe2009-08-191-4/+13
| | | | | | | | | - spell "address" right - list bp/wp params as optional And make those source lines wrap at sane margins. git-svn-id: svn://svn.berlios.de/openocd/trunk@2596 b42882b7-edfa-0310-969c-e2dbd0fdcd60
* David Brownell <david-b@pacbell.net> Clean up some Cortex-M3 reset handling.oharboe2009-08-191-17/+39
| | | | | | | | | | | | | | - AIRCR_SYSRESETREQ is generic; use it on any system where SRST won't fly, not just on Stellaris-based ones. - Reformat and improve comments about the Stellaris quirk; and xref the only public docs (an email) about the issue. It seems that *most* Stellaris chips have this problem. Tempest parts aren't yet in general sampling; and if rev B silicon for earlier chips exists, it's not very visible yet. git-svn-id: svn://svn.berlios.de/openocd/trunk@2595 b42882b7-edfa-0310-969c-e2dbd0fdcd60
* David Brownell [david-b@pacbell.net]:ntfreak2009-08-181-10/+21
| | | | | | | | | | | | | Simplify dumping of register lists by only printing cached values if they are marked as valid. Most of the time, they are invalid; so printing *any* value is just misleading. Note that for ARM7 and ARM9 most EmbeddedICE registers (except for debug status) could be cached most of the time; and their register cache isn't maintained properly (many accesses seem to bypass that cache code). git-svn-id: svn://svn.berlios.de/openocd/trunk@2594 b42882b7-edfa-0310-969c-e2dbd0fdcd60
* Jonas Horberg [jhorberg@sauer-danfoss.com]ntfreak2009-08-181-159/+148
| | | | | | | | | | | | | | | | | | | | | | | | | https://lists.berlios.de/pipermail/openocd-development/2009-August/009939.html 1. It can only be built with the FTD2XX driver. libftdi supports FT2232H/FT4232H since version 0.16 2. A speed value of 0 is used as a RTCK request indicator. This clashes with the valid clock division value 0 that provide the highest fixed clock frequency. 3. The ft2232_speed_div function return the maximum selectable frequency (30MHz) when RTCK is activated. It should return 0. 4. The ft2232_khz function return ERROR_OK when RTCK is requested even for devices lacking RTCK support. It should return ERROR_FAIL so the upper driver layers can detect this and try to fallback to a fixed frequency. 5. FT2232H/FT4232H have a backward compatibility function that divide the clock by 5 to get the same frequency range as FT2232D. There is no code that disable this functionality. I can not find anything about if this is enabled or disabled by default. I think it is safest to actively disable it. git-svn-id: svn://svn.berlios.de/openocd/trunk@2591 b42882b7-edfa-0310-969c-e2dbd0fdcd60
* Jonas Horberg [jhorberg@sauer-danfoss.com]ntfreak2009-08-184-39/+131
| | | | | | Change jtag_rclk behaviour so it can be called before the interface init function git-svn-id: svn://svn.berlios.de/openocd/trunk@2590 b42882b7-edfa-0310-969c-e2dbd0fdcd60
* David Brownell <david-b@pacbell.net> Add "cortex_m3 vector_catch" command ↵oharboe2009-08-182-3/+83
| | | | | | | | | | | | | | | | and docs. One minor issue with this is that the core debug support uses this mechanism, then trashes its state over reset. Users can Work around that (for now) by re-assigning the desired config after reset. Also fixes "target halted due to target-not-halted" goof. When we can't describe the reason using OpenOCD's limited vocabulary, say "reason undefined" instead of saying it's not halted. git-svn-id: svn://svn.berlios.de/openocd/trunk@2588 b42882b7-edfa-0310-969c-e2dbd0fdcd60
* David Brownell <david-b@pacbell.net> Clean up ARM7/ARM9 EmbeddedICE register ↵oharboe2009-08-182-49/+131
| | | | | | | | | | | | | | handling ... don't use parallel arrays (error prone) or assume all registers are 32-bits wide (they can have fewer bits); don't use spaces in register names, so they can be passed more easily to the "reg" command. Minor updates for ARM9 vector_catch support: it's an 8-bit value. This seems to help this core's vector_catch command work a bit better; but its behavior wih the register cache is still goofy. git-svn-id: svn://svn.berlios.de/openocd/trunk@2587 b42882b7-edfa-0310-969c-e2dbd0fdcd60
* David Brownell <david-b@pacbell.net> Several of the ARMv7M registers are 8 ↵oharboe2009-08-181-29/+30
| | | | | | | | | bits or less; don't display them as 32 bits unless that's their true size. (Removes some confusion. git-svn-id: svn://svn.berlios.de/openocd/trunk@2586 b42882b7-edfa-0310-969c-e2dbd0fdcd60
* Piotr Ziecik <kosmo@semihalf.com> Due to errors in chipselect management in ↵oharboe2009-08-181-3/+3
| | | | | | | | | | davinci_nand driver OpenOCD was able to access only to chips attached to first EMIF chipselect. This patch fixes chipselect management code and allows OpenOCD to access to NAND devices attached to any EMIF CS line. git-svn-id: svn://svn.berlios.de/openocd/trunk@2585 b42882b7-edfa-0310-969c-e2dbd0fdcd60
* Ferdinand Postema <ferdinand@postema.eu> cygwin 32 bit warningoharboe2009-08-161-1/+1
| | | | git-svn-id: svn://svn.berlios.de/openocd/trunk@2581 b42882b7-edfa-0310-969c-e2dbd0fdcd60
* added note w/reference to discussion on whether or not arm11 code is broken ↵oharboe2009-08-161-0/+4
| | | | | | or not. git-svn-id: svn://svn.berlios.de/openocd/trunk@2580 b42882b7-edfa-0310-969c-e2dbd0fdcd60
* Audrius Urmanavičius [didele.deze@gmail.com]:ntfreak2009-08-132-80/+202
| | | | | | | Add flash programming support for NXP LPC1700 cortex_m3 based family git-svn-id: svn://svn.berlios.de/openocd/trunk@2579 b42882b7-edfa-0310-969c-e2dbd0fdcd60
* David Brownell <david-b@pacbell.net>:ntfreak2009-08-071-0/+3
| | | | | | Warn about anyone using "jtag_speed" commands; that command is obsolete, and will someday be removed. git-svn-id: svn://svn.berlios.de/openocd/trunk@2578 b42882b7-edfa-0310-969c-e2dbd0fdcd60
* Ferdinand Postema [ferdinand@postema.eu]ntfreak2009-08-071-0/+3
| | | | | | - fix vector catch issues with certain ARM9 cores - AT91SAM9260 and STR9 git-svn-id: svn://svn.berlios.de/openocd/trunk@2576 b42882b7-edfa-0310-969c-e2dbd0fdcd60
* - fix segfault introduced during cortex reg cleanupntfreak2009-08-071-2/+2
| | | | git-svn-id: svn://svn.berlios.de/openocd/trunk@2575 b42882b7-edfa-0310-969c-e2dbd0fdcd60
* Gary Carlson [gcarlson@carlson-minot.com]:ntfreak2009-08-061-3/+1
| | | | | | - revert patch from rev1507 as it was causing reset issues with arm9 cores git-svn-id: svn://svn.berlios.de/openocd/trunk@2574 b42882b7-edfa-0310-969c-e2dbd0fdcd60
* michal smulski <michal.smulski@ooma.com>:zwelch2009-08-061-2/+2
| | | | | | | Fix ARM11 half-word bulk memory read and write. git-svn-id: svn://svn.berlios.de/openocd/trunk@2572 b42882b7-edfa-0310-969c-e2dbd0fdcd60
* Fix NPE in GDB_EVENT_END as logforwarding was not disabled early enoughoharboe2009-07-271-1/+7
| | | | git-svn-id: svn://svn.berlios.de/openocd/trunk@2570 b42882b7-edfa-0310-969c-e2dbd0fdcd60
* David Brownell <david-b@pacbell.net> More testcase work:oharboe2009-07-261-7/+16
| | | | | | | | | | | | | | | | A5.3.11 Data processing (shifted register) The usual kinds of problems; the most noteworthy were that the "S"et flags bit was mis-handled in these instructions. --- This is the last patch from a quickie set of tests covering all encodings of the instructions with 32-bit opcodes. There may be some corner cases left, plus the instructions that aren't yet handled, but the Thumb2 disassembler is no longer just "lightly" tested with GCC output ... the new code paths have mostly been verified. git-svn-id: svn://svn.berlios.de/openocd/trunk@2568 b42882b7-edfa-0310-969c-e2dbd0fdcd60
* More instruction decoding fixes:oharboe2009-07-261-16/+32
| | | | | | | | | | | A5.3.5 Load/store multiple A5.3.7 Load word There was a longstanding bug in Thumb-1 LDM; the rest of the LDM/STM fixes are just using width specs to match UAL syntax, except for two opcode name typos. Load word had two bitmask goofs. git-svn-id: svn://svn.berlios.de/openocd/trunk@2567 b42882b7-edfa-0310-969c-e2dbd0fdcd60
* David Brownell <david-b@pacbell.net> More fixes from test cases:oharboe2009-07-261-7/+11
| | | | | | | | | | A5.3.8 Load halfword, unallocated memory hints It's mostly the usual sort of bitmasking goofage and getting the width specs right. In one case an older x86 GCC generated bad code unless I structred a conditional differently (sigh). git-svn-id: svn://svn.berlios.de/openocd/trunk@2566 b42882b7-edfa-0310-969c-e2dbd0fdcd60
* David Brownell <david-b@pacbell.net> More instruction decoding fixes:oharboe2009-07-261-8/+12
| | | | | | | | | | | A5.3.5 Load/store multiple A5.3.7 Load word There was a longstanding bug in Thumb-1 LDM; the rest of the LDM/STM fixes are just using width specs to match UAL syntax, except for two opcode name typos. Load word had two bitmask goofs. git-svn-id: svn://svn.berlios.de/openocd/trunk@2565 b42882b7-edfa-0310-969c-e2dbd0fdcd60
* David Brownell <david-b@pacbell.net> More instruction decoding fixes based ↵oharboe2009-07-241-9/+10
| | | | | | | | | | | | | | | | on test cases, covering ARMv7-M arch manual: A5.3.1 Data processing (modified immediate) A5.3.3 Data processing (plain binary immediate) A5.3.4 Branches and miscellaneous control and other (immediate) encodings referenced there. Several of these just tweak the new syntax ("Unified" ARM/Thumb: UAL) but there were a few bugs too. git-svn-id: svn://svn.berlios.de/openocd/trunk@2564 b42882b7-edfa-0310-969c-e2dbd0fdcd60
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