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* target: Only register mrc mcr commands when one of the targets support them.Øyvind Harboe2009-11-051-3/+11
| | | | | | This avoids polluting help for targets that can never support mrc/mcr Signed-off-by: Øyvind Harboe <oyvind.harboe@zylin.com>
* cortex_a8: add mrc mcr interface.Øyvind Harboe2009-11-051-0/+29
| | | | Signed-off-by: Øyvind Harboe <oyvind.harboe@zylin.com>
* watchpoint_add() cleanupDavid Brownell2009-11-054-32/+40
| | | | | | | | | | | | Fail watchpoint_add() if it's the same address but the parameters are different ... don't just assume having the same address means the same watchpoint! (Note that overlapping watchpoints aren't detected...) Handle unrecognized return codes more sanely; don't exit()! And describe command params right. Signed-off-by: David Brownell <dbrownell@users.sourceforge.net>
* Cortex-M3: expose most DWT registersDavid Brownell2009-11-052-21/+144
| | | | | | | | | | | | | | | | | | | | | | | Expose most DWT registers via Tcl; there are a few more, but those are mostly for profiling along with the ITM. Having this set available enables operations which aren't possible with just the standard watchpoint operations. The cycle counter may be interesting. Turn it on after reset by setting the LSB of the dwt_ctrl register, and it counts CPU clocks. You can program the comparator 0 watchpoint to trigger on a given cycle count, rather than a data address. Likewise, comparator 1 may be able to match data values given address matches from one or two other comparators. (Not all hardware supports this capability though; try it. That is something the standard watchpoint methods should eventually handle, for the single address case.) Minor cleanup: remove needless functional indirection for exposing the v7m architctural registers. Signed-off-by: David Brownell <dbrownell@users.sourceforge.net>
* Cortex-M3: minor cleanupDavid Brownell2009-11-052-16/+4
| | | | | | | | | | | There's no reason to read which interrupts are enabled from the NVIC; that state isn't used. Plus, it's highly dynamic since firmware can change it at any time; remove the support for those state records. Remove duplicate definition of DWT_CTRL address; shrink a line. Signed-off-by: David Brownell <dbrownell@users.sourceforge.net>
* Cortex-M3: DWT cleanup/fixesDavid Brownell2009-11-051-56/+115
| | | | | | | | | | | | | Fix the watchpoint error checks, and do them in add(), not later in set() when it's mostly too late. Support the full range of watchpoint sizes (1 to 32K bytes each), and check alignments. Minor cleanup of DWT access: shrink lines, use "+" for address calculations, comment a few issues. Add debug message reporting DWT capabilities, matching the message for FBP, and some minor code and spec review comments. Signed-off-by: David Brownell <dbrownell@users.sourceforge.net>
* ARMv7M: add docs, remove exportsDavid Brownell2009-11-052-29/+63
| | | | | | | | | | | | Add Doxygen for the exported ARMv7-M interfaces. Make the non-exported stuff static. Remove functions and data which are now observably unused. Add comment about a small speedup that the run_algorithm() logic could use. Shrink a few too-long lines. Signed-off-by: David Brownell <dbrownell@users.sourceforge.net>
* target: add target->type->has_mmu fn.Øyvind Harboe2009-11-053-5/+48
| | | | | | | | | improve default target->read/write_phys_memory, produce more sensible error messages if the mmu interface functions have not been implemented yet vs. will not be implemented(e.g. cortex m3). Signed-off-by: Øyvind Harboe <oyvind.harboe@zylin.com>
* Make default implementation of mdw/mmw phys return error 'not implemented'Øyvind Harboe2009-11-051-2/+14
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* target: remove unused interface fn that clutters codeØyvind Harboe2009-11-0516-92/+0
| | | | | | | | | The quit entry point was not being invoked. Just a source of confusion at this point. XScale ran 100x reset upon quit, but that code made no sense, wasn't commented and never invoke. Signed-off-by: Øyvind Harboe <oyvind.harboe@zylin.com>
* debug interface: get rid of unused pre_debug fnØyvind Harboe2009-11-059-16/+0
| | | | | | Removing unused code makes it much less mysterius. Signed-off-by: Øyvind Harboe <oyvind.harboe@zylin.com>
* warnings: removeØyvind Harboe2009-11-051-3/+2
| | | | Signed-off-by: Øyvind Harboe <oyvind.harboe@zylin.com>
* ft2232: cleanupDavid Brownell2009-11-041-110/+97
| | | | | | | | | Previous patch somehow made GCC lose some of its cookies; work around, zero-init that struct. Clean up code from the previous patch. Signed-off-by: David Brownell <dbrownell@users.sourceforge.net>
* JTAG: support KT-LINK adapterKrzysztof Kajstura2009-11-041-0/+131
| | | | Signed-off-by: David Brownell <dbrownell@users.sourceforge.net>
* target: 20 second timeout/megabyte for CRC checkØyvind Harboe2009-11-031-1/+4
| | | | | | | There was a fixed 20 second timeout which is too little for large, slow timeout checks. Signed-off-by: Øyvind Harboe <oyvind.harboe@zylin.com>
* arm920t: memory writes were broken when MMU was disabledØyvind Harboe2009-11-031-11/+10
| | | | | | | | | | | To support breakpoints, flush data cache line and invalidate instruction cache when 4 and 2 byte words are written. The previous code was trying to write directly to the physical memory, which was buggy and had a number of other situations that were not handled. Signed-off-by: Øyvind Harboe <oyvind.harboe@zylin.com>
* target: require working area for physical/virtual addresses to be specifiedØyvind Harboe2009-11-032-9/+29
| | | | | | | | | | | | | | | | Fixed bug: if virtual address for working memory was not specified and MMU was enabled, then address 0 would be used. Require working address to be specified for both MMU enabled and disabled case. For some completely inexplicable reason this fixes the regression in svn 2646 for flash write in arm926ejs target. The logs showed that MMU was disabled in the case below: https://lists.berlios.de/pipermail/openocd-development/2009-November/011882.html Signed-off-by: Øyvind Harboe <oyvind.harboe@zylin.com>
* FT2232: increase read retry countsDimitar Dimitrov2009-11-011-8/+26
| | | | | | | | This change is necessary to debug AT91SAM9260 on my PC with a FT2232H dongle. Signed-off-by: Dimitar Dimitrov <dinuxbg@gmail.com> Signed-off-by: David Brownell <dbrownell@users.sourceforge.net>
* arm9tdmi: more correct fix for vector_catchDavid Brownell2009-10-311-8/+5
| | | | | | | Just use the array of names we're given, ignoring indices. The "reserved means don't use" patch missed that change. Signed-off-by: David Brownell <dbrownell@users.sourceforge.net>
* ARM926: fix arm926ejs_mmu() reading from bad pointerDavid Brownell2009-10-301-1/+3
| | | | | | | | | I'm suspecting this code can never have worked, since the original commit (svn #335) in early 2008. Fix is just copy/paste from another (working) function. Signed-off-by: David Brownell <dbrownell@users.sourceforge.net>
* bin2char: for win32 set stdin/stdout to binary modeSpencer Oliver2009-10-301-0/+10
| | | | Signed-off-by: Spencer Oliver <ntfreak@users.sourceforge.net>
* SVF: fix checking bit pattern against lengthMichael Roth2009-10-291-2/+2
| | | | | | | | | | | | | | | | | | | | | | | | The code works like follow (N = bit_len): N -1 %4 2<< -1 ~ (binary) -------------------------------------------------- 1 0 0 2 1 1111 1110 2 1 1 4 3 1111 1100 3 2 2 8 7 1111 1000 4 3 3 16 15 1111 0000 5 4 0 2 1 1111 1110 6 5 1 4 3 1111 1100 7 6 2 8 7 1111 1000 8 7 3 16 15 1111 0000 ... ... ... ... ... ... Addresses a bug reported by FangfangLi <ffli@syntest.com.cn>. [dbrownell@users.sourceforge.net: fix spelling bug too] Signed-off-by: Michael Roth <mroth@nessie.de> Cc: FangfangLi <ffli@syntest.com.cn> Signed-off-by: David Brownell <dbrownell@users.sourceforge.net>
* XSVF: bugfix handling state pathsDavid Brownell2009-10-291-15/+100
| | | | | | | | | | | | | | | | | | | | | | | Implement XSVF support for detailed state path transitions, by collecting sequences of XSTATE transitions into paths and then calling pathmove(). It seems that the Xilinx tools want to force state-by-state transitions instead of relying on the standardized SVF paths. Like maybe there are XSVF tools not implementing SVF paths, which are all that we support using svf_statemove(). So from IRPAUSE, instead of just issuing "XSTATE DRPAUSE" they will issue XSTATES for each intermediate state: first IREXIT2, then IRUPDATE, DRSELECT, DRCAPTURE, DREXIT1, and finally DRPAUSE. This works now. Handling of paths that go *through* reset is a trifle dodgey, but it should be safe. Tested-by: Wookey <wookey@wookware.org> Signed-off-by: David Brownell <dbrownell@users.sourceforge.net>
* Cortex-M3: remove exports and forward declsDavid Brownell2009-10-282-189/+144
| | | | | | | | | | | Unneeded exports cause confusion about the module interfaces. Make most functions static, and fix some line-too-long issues. Delete some now-obviously-unused code. The forward decls are just code clutter; move their references later, after the normal declarations. (Or vice versa.) Signed-off-by: David Brownell <dbrownell@users.sourceforge.net>
* ARM926: remove exports and forward declsDavid Brownell2009-10-281-122/+127
| | | | | | | | | | | | | Unneeded exports cause confusion about the module interfaces. Only the Feroceon code builds on this, so only routines it reuses should be public.. Make most remaining functions static, and fix some of the line-too-long issues. The forward decls are just code clutter; move their references later, after the normal declarations. Turns out we don't need even one forward declaration in this file. Signed-off-by: David Brownell <dbrownell@users.sourceforge.net>
* bugfix: stack corruption loading IHex imagesFranck HÉRÉSON2009-10-282-1/+22
| | | | | | | | | | | | The Hex parser uses a fixed number of sections. When the number of sections in the file is greater than that, the stack get corrupted and a CHECKSUM ERROR is detected which is very confusing. This checks the number of sections read, and increases IMAGE_MAX_SECTIONS so it works on my file. Signed-off-by: David Brownell <dbrownell@users.sourceforge.net>
* ARM: fix single-step of Thumb unconditional branchNicolas Pitre2009-10-271-2/+2
| | | | | | | | | Only type 1 branch instruction has a condition code, not type 2. Currently they're both tagged with ARM_B which doesn't allow for the distinction. Signed-off-by: Nicolas Pitre <nico@marvell.com> Signed-off-by: David Brownell <dbrownell@users.sourceforge.net>
* ARM: fix target address when disassembling Thumb BLXNicolas Pitre2009-10-271-0/+1
| | | | | | | | A Thumb BLX instruction is branching to ARM code, and therefore the first 2 bits of the target address must be cleared. Signed-off-by: Nicolas Pitre <nico@marvell.com> Signed-off-by: David Brownell <dbrownell@users.sourceforge.net>
* Signalyzer: H2 and H4 supportOleg Seiljus2009-10-271-0/+809
| | | | | | | | | | This patch includes partial support for these new JTAG adapters. More complete support will require updates to the libftdi code, for EEPROM access. [dbrownell@users.sourceforge.net: fix whitespace, linelen, etc ] Signed-off-by: David Brownell <dbrownell@users.sourceforge.net>
* ARM: fix Thumb mode handling when single-stepping register based branch insnsNicolas Pitre2009-10-261-22/+33
| | | | | | | | | | | | | | | | | | | Currently, OpenOCD is always caching the PC value without the T bit. This means that assignment to the PC register must clear that bit and set the processor state to Thumb when it is set. And when the PC register value is transferred to another register or stored into memory then the T bit must be restored. Discussion: It is arguable if OpenOCd should have preserved the original PC value which would have greatly simplified this code. The processor state could then be obtained simply by getting at bit 0 of the PC. This however would require special handling elsewhere instead since the T bit is not always relevant (like when PC is used with ALU insns or as an index with some addressing modes). It is unclear which way would be simpler in the end. Signed-off-by: Nicolas Pitre <nico@marvell.com> Signed-off-by: David Brownell <dbrownell@users.sourceforge.net>
* ARM: allow proper single stepping of Thumb BL and BLX instructionsNicolas Pitre2009-10-261-0/+12
| | | | | | | | | | | | | | Whenever an unconditional branch with the H bits set to 0b10 is met, the offset must be combined with the offset from the following opcode and not ignored like it is now. A comment in evaluate_b_bl_blx_thumb() suggests that the Thumb2 decoder would be a simpler solution. That might be true when single-stepping of Thumb2 code is implemented. But for now this appears to be the simplest solution to fix Thumb1 support. Signed-off-by: Nicolas Pitre <nico@marvell.com> Signed-off-by: David Brownell <dbrownell@users.sourceforge.net>
* ARM: call thumb_pass_branch_condition() only for actual branch opcodesNicolas Pitre2009-10-261-8/+6
| | | | | | | | | | | | | | Calling it first with every opcodes and then testing if the opcode was indeed a branch instruction is wasteful and rather strange. If ever thumb_pass_branch_condition() has side effects (say, like printing a debugging traces) then the result would be garbage for most Thumb instructions which have no condition code. While at it, let's make the nearby code more readable by reducing some of the redundant brace noise and reworking the error handling construct. Signed-off-by: Nicolas Pitre <nico@marvell.com> Signed-off-by: David Brownell <dbrownell@users.sourceforge.net>
* ft2232: less noise with _DEBUG_JTAG_IO_David Brownell2009-10-261-1/+0
| | | | Don't log "Yes, I'm *still* in TAP_IDLE" every seven runtest clocks.
* JTAG: "jtag newtap ..." cleanupDavid Brownell2009-10-261-7/+2
| | | | | | Get rid of needless variable, improve and shrink diagnostic. Signed-off-by: David Brownell <dbrownell@users.sourceforge.net>
* ARM ADIv5: "dap info" gets more readableDavid Brownell2009-10-261-33/+268
| | | | | | | | | | | | | | Make the "dap info" output more comprehensible: - Don't show CIDs unless they're incorrect (only four bits matter) - For CoreSight parts, interpret the part type - Interpret the part number - Show all five PID bytes together - Other minor cleanups Also some whitespace fixes, and shrink a few overlong source lines. Signed-off-by: David Brownell <dbrownell@users.sourceforge.net>
* SVF: fix parsing hex strings containing leading '0' charactersMichael Roth2009-10-261-0/+4
| | | | | | | | | Ignore leading '0' characters on hex strings. For example a bit pattern consisting of 6 bits could be written as 3f, 03f or 003f and so on. Signed-off-by: Michael Roth <mroth@nessie.de> Signed-off-by: David Brownell <dbrownell@users.sourceforge.net>
* JTAG: simple autoprobingDavid Brownell2009-10-261-12/+102
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This patch adds basic autoprobing support for the JTAG scan chains which cooperate. To use, you can invoke OpenOCD with just: - interface spec: "-f interface/...cfg" - possibly with "-c 'reset_config ...'" for SRST/TRST - possibly with "-c 'jtag_khz ...'" for the JTAG clock Then set up config files matching the reported TAPs. It doesn't declare targets ... just TAPs. So facilities above the JTAG and SVF/XSVF levels won't be available without a real config; this is almost purely a way to generate diagnostics. Autoprobe was successful with most boards I tested, except ones incorporating C55x DSPs (which don't cooperate with this scheme for IR length autodetection). Here's what one multi-TAP chip reported, with the "Warn:" prefixes removed: clock speed 500 kHz There are no enabled taps. AUTO PROBING MIGHT NOT WORK!! AUTO auto0.tap - use "jtag newtap auto0 tap -expected-id 0x2b900f0f ..." AUTO auto1.tap - use "jtag newtap auto1 tap -expected-id 0x07926001 ..." AUTO auto2.tap - use "jtag newtap auto2 tap -expected-id 0x0b73b02f ..." AUTO auto0.tap - use "... -irlen 4" AUTO auto1.tap - use "... -irlen 4" AUTO auto2.tap - use "... -irlen 6" no gdb ports allocated as no target has been specified The patch tweaks IR setup a bit, so we can represent TAPs with undeclared IR length. Signed-off-by: David Brownell <dbrownell@users.sourceforge.net>
* check if mmu is enabled before using mmu code pathØyvind Harboe2009-10-251-1/+1
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* ARM: rename "arm9tdmi vector_catch" to "arm9 ..."David Brownell2009-10-251-5/+3
| | | | | | And update doc accordingly. That EmbeddedICE register was introduced for ARM9TDMI and then carried forward into most new chips that use EmbeddedICE.
* JTAG: jtag_tap_init() bugfixesDavid Brownell2009-10-251-9/+18
| | | | | | | Stop allocating three bytes per IR bit, and cope somewhat better with IR lengths over 32 bits. Signed-off-by: David Brownell <dbrownell@users.sourceforge.net>
* xscale: always reload handler after resetDavid Brownell2009-10-252-19/+11
| | | | | | | | | | | | | | | | | | | | Remove needless debug handler state. - "handler_installed" became wrong as soon as the second TRST+SRST reset was issued ... so the handler was never reloaded after the reset removed it from the mini-icache. This fixes the bug where subsequent resets fail on PXA255 (if the first one even worked, which is uncommon). Other XScale chips would have problems too; PXA270 seems to have, IXP425 maybe not. - "handler_running" was never tested; it's pointless. Plus a related bugfix: invalidate OpenOCD's ARM register cache on reset. It was no more valid than the XScale's mini-icache. (Though ... such invalidations might be better done in "SRST asserted" callbacks.) Signed-off-by: David Brownell <dbrownell@users.sourceforge.net>
* arm9tdmi vector_catch: reserved means "don't use"David Brownell2009-10-232-3/+2
| | | | | | | Bit 5 shouldn't be used. Remove all support for modifying it. Matches the exception vector table, of course ... more than one bootloader uses that non-vector to help distinguish valid boot images from random garbage in flash.
* Improve help for arm9 vector_catch.Øyvind Harboe2009-10-231-1/+3
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* Remove debug output that could cause compile warnings.Øyvind Harboe2009-10-231-2/+0
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* mcr/mrc interface work. Implemented for arm926ejs and arm720t. mcr/mrc ↵Øyvind Harboe2009-10-236-12/+241
| | | | commands added.
* Embedded ICE version is now dumped with debug_level 1Øyvind Harboe2009-10-231-2/+2
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* jtag: clean up TAP state name handlingDavid Brownell2009-10-233-68/+63
| | | | | | | | | | | | Some cosmetic cleanup, and switch to a single table mapping between state names and symbols (vs two routines which only share that state with difficulty). Get rid of TAP_NUM_STATES, and some related knowledge about how TAP numbers are assigned. Later on, this will help us get rid of more such hardwired knowlege. Signed-off-by: David Brownell <dbrownell@users.sourceforge.net>
* SVF: clean up, mostly for TAP state name handlingDavid Brownell2009-10-234-79/+68
| | | | | | | | | | | | | | | | | | | | | - Use the name mappings all the other code uses: + name-to-state ... needed to add one special case + state-to-name - Improve various diagnostics: + don't complain about a "valid" state when the issue is actually that it must be "stable" + say which command was affected - Misc: + make more private data and code be static + use public DIM() not private dimof() + shorten the affected lines Re the mappings, this means we're more generous in inputs we accept, since case won't matter. Also our output diagnostics will be a smidgeon more informative, saying "RUN/IDLE" not just "IDLE" (emphasizing that there can be side effects). Signed-off-by: David Brownell <dbrownell@users.sourceforge.net>
* Ferocion: fix corruption of r0 when resuming Thumb modeNicolas Pitre2009-10-221-2/+1
| | | | | | | | The wrong variable (pc instead of r0) was used. Furthermore, someone did cover this error by stupidly silencing the compiler warning that occurred before a dummy void reference to r0 was added to the code. Signed-off-by: David Brownell <dbrownell@users.sourceforge.net>
* have "reg" command print cache names tooDavid Brownell2009-10-221-0/+2
| | | | | | | When dumping over 100 registers (as on most ARM9 + ETM cores), aid readability by splitting them into logical groups. Signed-off-by: David Brownell <dbrownell@users.sourceforge.net>
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