From 53b3d4dd53eebbf03f481dc59e4bc0259911864a Mon Sep 17 00:00:00 2001 From: David Brownell Date: Tue, 2 Mar 2010 15:00:14 -0800 Subject: LPC1768 updates, IAR board support Fix some issues with the generic LPC1768 config file: - Handle the post-reset clock config: 4 MHz internal RC, no PLL. This affects flash and JTAG clocking. - Remove JTAG adapter config; they don't all support trst_and_srst - Remove the rest of the bogus "reset-init" event handler. - Allow explicit CCLK configuration, instead of assuming 12 MHz; some boards will use 100 Mhz (or the post-reset 4 MHz). - Simplify: rely on defaults for endianness and IR-Capture value - Update some comments too Build on those fixes to make a trivial config for the IAR LPC1768 kickstart board (by Olimex) start working. Also, add doxygen to the lpc2000 flash driver, primarily to note a configuration problem with driver: it wrongly assumes the core clock rate never changes. Configs that are safe for updating flash after "reset halt" will thus often be unsafe later ... e.g. for LPC1768, after switching to use PLL0 at 100 MHz. Signed-off-by: David Brownell --- NEWS | 1 + 1 file changed, 1 insertion(+) (limited to 'NEWS') diff --git a/NEWS b/NEWS index 56c697ff..4fef5b2a 100644 --- a/NEWS +++ b/NEWS @@ -18,6 +18,7 @@ Flash Layer: Board, Target, and Interface Configuration Scripts: + Support IAR LPC1768 kickstart board (by Olimex) Core Jim/TCL Scripting: -- cgit v1.2.3