From 309870e414548e3cd6634819490239a2efb85a0e Mon Sep 17 00:00:00 2001 From: zwelch Date: Wed, 15 Jul 2009 23:39:37 +0000 Subject: David Brownell : Initial support for disassembling Thumb2 code. This works only for Cortex-M3 cores so far. Eventually other cores will also need Thumb2 support ... but they don't yet support any kind of disassembly. - Update the 16-bit Thumb decoder: * Understand CPS, REV*, SETEND, {U,S}XT{B,H} opcodes added by ARMv6. (It already seems to treat CPY as MOV.) * Understand CB, CBNZ, WFI, IT, and other opcodes added by in Thumb2. - A new Thumb2 instruction decode routine is provided. * This has a different signature: pass the target, not the instruction, so it can fetch a second halfword when needed. The instruction size is likewise returned to the caller. * 32-bit instructions are recognized but not yet decoded. - Start using the current "UAL" syntax in some cases. "SWI" is renamed as "SVC"; "LDMIA" as "LDM"; "STMIA" as "STM". - Define a new "cortex_m3 disassemble addr count" command to give access to this disassembly. Sanity checked against "objdump -d" output; a bunch of the new instructions checked out fine. git-svn-id: svn://svn.berlios.de/openocd/trunk@2530 b42882b7-edfa-0310-969c-e2dbd0fdcd60 --- doc/openocd.texi | 5 +++++ 1 file changed, 5 insertions(+) (limited to 'doc/openocd.texi') diff --git a/doc/openocd.texi b/doc/openocd.texi index f9703731..18077ccd 100644 --- a/doc/openocd.texi +++ b/doc/openocd.texi @@ -5003,6 +5003,11 @@ If @var{value} is defined, first assigns that. @subsection Cortex-M3 specific commands @cindex Cortex-M3 +@deffn Command {cortex_m3 disassemble} address count +@cindex disassemble +Disassembles @var{count} Thumb2 instructions starting at @var{address}. +@end deffn + @deffn Command {cortex_m3 maskisr} (@option{on}|@option{off}) Control masking (disabling) interrupts during target step/resume. @end deffn -- cgit v1.2.3