From 6d4cdddbe27d1b70528d9a70279a2a9b91c1f242 Mon Sep 17 00:00:00 2001 From: dbrownell Date: Tue, 29 Sep 2009 18:30:06 +0000 Subject: ARM11 command handling fixes - Commands were supposed to have been "arm11 memwrite ..." not "memwrite ..." - Get rid of obfuscatory macros - Re-alphabetize - Add docs for "arm11 vcr" git-svn-id: svn://svn.berlios.de/openocd/trunk@2776 b42882b7-edfa-0310-969c-e2dbd0fdcd60 --- doc/openocd.texi | 15 ++++++++++++++- 1 file changed, 14 insertions(+), 1 deletion(-) (limited to 'doc') diff --git a/doc/openocd.texi b/doc/openocd.texi index d80ef492..28ec4a5d 100644 --- a/doc/openocd.texi +++ b/doc/openocd.texi @@ -5496,10 +5496,23 @@ If @var{value} is defined, first assigns that. @deffn Command {arm11 step_irq_enable} [value] Displays the value of the flag controlling whether IRQs are enabled during single stepping; -they is disabled by default. +they are disabled by default. If @var{value} is defined, first assigns that. @end deffn +@deffn Command {arm11 vcr} [value] +@cindex vector_catch +Displays the value of the @emph{Vector Catch Register (VCR)}, +coprocessor 14 register 7. +If @var{value} is defined, first assigns that. + +Vector Catch hardware provides dedicated breakpoints +for certain hardware events. +The specific bit values are core-specific (as in fact is using +coprocessor 14 register 7 itself) but all current ARM11 +cores @emph{except the ARM1176} use the same six bits. +@end deffn + @section ARMv7 Architecture @cindex ARMv7 -- cgit v1.2.3