From 3d6bcf07921753141a3905ee5619724573460cb3 Mon Sep 17 00:00:00 2001 From: drath Date: Mon, 25 Feb 2008 17:48:04 +0000 Subject: - convert all files to unix line-ending git-svn-id: svn://svn.berlios.de/openocd/trunk@347 b42882b7-edfa-0310-969c-e2dbd0fdcd60 --- src/flash/at91sam7.h | 200 +- src/flash/cfi.c | 4710 +++++++++++++++++++++++----------------------- src/flash/s3c2440_nand.c | 358 ++-- src/flash/str9xpec.c | 2696 +++++++++++++------------- 4 files changed, 3982 insertions(+), 3982 deletions(-) (limited to 'src/flash') diff --git a/src/flash/at91sam7.h b/src/flash/at91sam7.h index 4ef154c9..eb0213c0 100644 --- a/src/flash/at91sam7.h +++ b/src/flash/at91sam7.h @@ -1,100 +1,100 @@ -/*************************************************************************** - * Copyright (C) 2006 by Magnus Lundin * - * lundin@mlu.mine.nu * - * * - * This program is free software; you can redistribute it and/or modify * - * it under the terms of the GNU General Public License as published by * - * the Free Software Foundation; either version 2 of the License, or * - * (at your option) any later version. * - * * - * This program is distributed in the hope that it will be useful, * - * but WITHOUT ANY WARRANTY; without even the implied warranty of * - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * - * GNU General Public License for more details. * - * * - * You should have received a copy of the GNU General Public License * - * along with this program; if not, write to the * - * Free Software Foundation, Inc., * - * 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. * - ***************************************************************************/ -#ifndef AT91SAM7_H -#define AT91SAM7_H - -#include "flash.h" -#include "target.h" - -typedef struct at91sam7_flash_bank_s -{ - u32 working_area; - u32 working_area_size; - - /* chip id register */ - u32 cidr; - u16 cidr_ext; - u16 cidr_nvptyp; - u16 cidr_arch; - u16 cidr_sramsiz; - u16 cidr_nvpsiz; - u16 cidr_nvpsiz2; - u16 cidr_eproc; - u16 cidr_version; - char * target_name; - - /* flash geometry */ - u16 num_pages; - u16 pagesize; - u16 pages_in_lockregion; - u8 num_erase_regions; - u8 num_planes; - u32 *erase_region_info; - - /* nv memory bits */ - u16 num_lockbits; - u16 lockbits[4]; - u16 num_nvmbits; - u16 nvmbits; - u8 securitybit; - u8 flashmode[4]; /* 0: not init, 1: fmcn for nvbits (1uS), 2: fmcn for flash (1.5uS) */ - - /* main clock status */ - u8 mck_valid; - u32 mck_freq; - - int probed; - -} at91sam7_flash_bank_t; - -/* AT91SAM7 control registers */ -#define DBGU_CIDR 0xFFFFF240 -#define CKGR_MCFR 0xFFFFFC24 -#define CKGR_MCFR_MAINRDY 0x10000 -#define CKGR_PLLR 0xFFFFFC2c -#define CKGR_PLLR_DIV 0xff -#define CKGR_PLLR_MUL 0x07ff0000 -#define PMC_MCKR 0xFFFFFC30 -#define PMC_MCKR_CSS 0x03 -#define PMC_MCKR_PRES 0x1c - -/* Flash Controller Commands */ -#define WP 0x01 -#define SLB 0x02 -#define WPL 0x03 -#define CLB 0x04 -#define EA 0x08 -#define SGPB 0x0B -#define CGPB 0x0D -#define SSB 0x0F - -/* MC_FSR bit definitions */ -#define MC_FSR_FRDY 1 -#define MC_FSR_EOL 2 - -/* AT91SAM7 constants */ -#define RC_FREQ 32000 - -/* FLASH_TIMING_MODES */ -#define FMR_TIMING_NONE 0 -#define FMR_TIMING_NVBITS 1 -#define FMR_TIMING_FLASH 2 - -#endif /* AT91SAM7_H */ +/*************************************************************************** + * Copyright (C) 2006 by Magnus Lundin * + * lundin@mlu.mine.nu * + * * + * This program is free software; you can redistribute it and/or modify * + * it under the terms of the GNU General Public License as published by * + * the Free Software Foundation; either version 2 of the License, or * + * (at your option) any later version. * + * * + * This program is distributed in the hope that it will be useful, * + * but WITHOUT ANY WARRANTY; without even the implied warranty of * + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * + * GNU General Public License for more details. * + * * + * You should have received a copy of the GNU General Public License * + * along with this program; if not, write to the * + * Free Software Foundation, Inc., * + * 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. * + ***************************************************************************/ +#ifndef AT91SAM7_H +#define AT91SAM7_H + +#include "flash.h" +#include "target.h" + +typedef struct at91sam7_flash_bank_s +{ + u32 working_area; + u32 working_area_size; + + /* chip id register */ + u32 cidr; + u16 cidr_ext; + u16 cidr_nvptyp; + u16 cidr_arch; + u16 cidr_sramsiz; + u16 cidr_nvpsiz; + u16 cidr_nvpsiz2; + u16 cidr_eproc; + u16 cidr_version; + char * target_name; + + /* flash geometry */ + u16 num_pages; + u16 pagesize; + u16 pages_in_lockregion; + u8 num_erase_regions; + u8 num_planes; + u32 *erase_region_info; + + /* nv memory bits */ + u16 num_lockbits; + u16 lockbits[4]; + u16 num_nvmbits; + u16 nvmbits; + u8 securitybit; + u8 flashmode[4]; /* 0: not init, 1: fmcn for nvbits (1uS), 2: fmcn for flash (1.5uS) */ + + /* main clock status */ + u8 mck_valid; + u32 mck_freq; + + int probed; + +} at91sam7_flash_bank_t; + +/* AT91SAM7 control registers */ +#define DBGU_CIDR 0xFFFFF240 +#define CKGR_MCFR 0xFFFFFC24 +#define CKGR_MCFR_MAINRDY 0x10000 +#define CKGR_PLLR 0xFFFFFC2c +#define CKGR_PLLR_DIV 0xff +#define CKGR_PLLR_MUL 0x07ff0000 +#define PMC_MCKR 0xFFFFFC30 +#define PMC_MCKR_CSS 0x03 +#define PMC_MCKR_PRES 0x1c + +/* Flash Controller Commands */ +#define WP 0x01 +#define SLB 0x02 +#define WPL 0x03 +#define CLB 0x04 +#define EA 0x08 +#define SGPB 0x0B +#define CGPB 0x0D +#define SSB 0x0F + +/* MC_FSR bit definitions */ +#define MC_FSR_FRDY 1 +#define MC_FSR_EOL 2 + +/* AT91SAM7 constants */ +#define RC_FREQ 32000 + +/* FLASH_TIMING_MODES */ +#define FMR_TIMING_NONE 0 +#define FMR_TIMING_NVBITS 1 +#define FMR_TIMING_FLASH 2 + +#endif /* AT91SAM7_H */ diff --git a/src/flash/cfi.c b/src/flash/cfi.c index 82120d8d..88e8e63d 100644 --- a/src/flash/cfi.c +++ b/src/flash/cfi.c @@ -1,2355 +1,2355 @@ -/*************************************************************************** - * Copyright (C) 2005, 2007 by Dominic Rath * - * Dominic.Rath@gmx.de * - * * - * This program is free software; you can redistribute it and/or modify * - * it under the terms of the GNU General Public License as published by * - * the Free Software Foundation; either version 2 of the License, or * - * (at your option) any later version. * - * * - * This program is distributed in the hope that it will be useful, * - * but WITHOUT ANY WARRANTY; without even the implied warranty of * - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * - * GNU General Public License for more details. * - * * - * You should have received a copy of the GNU General Public License * - * along with this program; if not, write to the * - * Free Software Foundation, Inc., * - * 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. * - ***************************************************************************/ -#ifdef HAVE_CONFIG_H -#include "config.h" -#endif - -#include "replacements.h" - -#include "cfi.h" - -#include "flash.h" -#include "target.h" -#include "log.h" -#include "armv4_5.h" -#include "algorithm.h" -#include "binarybuffer.h" -#include "types.h" - -#include -#include -#include - -int cfi_register_commands(struct command_context_s *cmd_ctx); -int cfi_flash_bank_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc, struct flash_bank_s *bank); -int cfi_erase(struct flash_bank_s *bank, int first, int last); -int cfi_protect(struct flash_bank_s *bank, int set, int first, int last); -int cfi_write(struct flash_bank_s *bank, u8 *buffer, u32 offset, u32 count); -int cfi_probe(struct flash_bank_s *bank); -int cfi_auto_probe(struct flash_bank_s *bank); -int cfi_erase_check(struct flash_bank_s *bank); -int cfi_protect_check(struct flash_bank_s *bank); -int cfi_info(struct flash_bank_s *bank, char *buf, int buf_size); - -int cfi_handle_part_id_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc); - -#define CFI_MAX_BUS_WIDTH 4 -#define CFI_MAX_CHIP_WIDTH 4 - -/* defines internal maximum size for code fragment in cfi_intel_write_block() */ -#define CFI_MAX_INTEL_CODESIZE 256 - -flash_driver_t cfi_flash = -{ - .name = "cfi", - .register_commands = cfi_register_commands, - .flash_bank_command = cfi_flash_bank_command, - .erase = cfi_erase, - .protect = cfi_protect, - .write = cfi_write, - .probe = cfi_probe, - .auto_probe = cfi_auto_probe, - .erase_check = cfi_erase_check, - .protect_check = cfi_protect_check, - .info = cfi_info -}; - -cfi_unlock_addresses_t cfi_unlock_addresses[] = -{ - [CFI_UNLOCK_555_2AA] = { .unlock1 = 0x555, .unlock2 = 0x2aa }, - [CFI_UNLOCK_5555_2AAA] = { .unlock1 = 0x5555, .unlock2 = 0x2aaa }, -}; - -/* CFI fixups foward declarations */ -void cfi_fixup_non_cfi(flash_bank_t *flash, void *param); -void cfi_fixup_0002_erase_regions(flash_bank_t *flash, void *param); -void cfi_fixup_0002_unlock_addresses(flash_bank_t *flash, void *param); -void cfi_fixup_atmel_reversed_erase_regions(flash_bank_t *flash, void *param); - -/* fixup after identifying JEDEC manufactuer and ID */ -cfi_fixup_t cfi_jedec_fixups[] = { - {CFI_MFR_SST, 0x00D4, cfi_fixup_non_cfi, NULL}, - {CFI_MFR_SST, 0x00D5, cfi_fixup_non_cfi, NULL}, - {CFI_MFR_SST, 0x00D6, cfi_fixup_non_cfi, NULL}, - {CFI_MFR_SST, 0x00D7, cfi_fixup_non_cfi, NULL}, - {CFI_MFR_SST, 0x2780, cfi_fixup_non_cfi, NULL}, - {CFI_MFR_ST, 0x00D5, cfi_fixup_non_cfi, NULL}, - {CFI_MFR_ST, 0x00D6, cfi_fixup_non_cfi, NULL}, - {CFI_MFR_AMD, 0x2223, cfi_fixup_non_cfi, NULL}, - {CFI_MFR_AMD, 0x22ab, cfi_fixup_non_cfi, NULL}, - {0, 0, NULL, NULL} -}; - -/* fixup after reading cmdset 0002 primary query table */ -cfi_fixup_t cfi_0002_fixups[] = { - {CFI_MFR_SST, 0x00D4, cfi_fixup_0002_unlock_addresses, &cfi_unlock_addresses[CFI_UNLOCK_5555_2AAA]}, - {CFI_MFR_SST, 0x00D5, cfi_fixup_0002_unlock_addresses, &cfi_unlock_addresses[CFI_UNLOCK_5555_2AAA]}, - {CFI_MFR_SST, 0x00D6, cfi_fixup_0002_unlock_addresses, &cfi_unlock_addresses[CFI_UNLOCK_5555_2AAA]}, - {CFI_MFR_SST, 0x00D7, cfi_fixup_0002_unlock_addresses, &cfi_unlock_addresses[CFI_UNLOCK_5555_2AAA]}, - {CFI_MFR_SST, 0x2780, cfi_fixup_0002_unlock_addresses, &cfi_unlock_addresses[CFI_UNLOCK_5555_2AAA]}, - {CFI_MFR_ATMEL, 0x00C8, cfi_fixup_atmel_reversed_erase_regions, NULL}, - {CFI_MFR_ANY, CFI_ID_ANY, cfi_fixup_0002_erase_regions, NULL}, - {0, 0, NULL, NULL} -}; - -/* fixup after reading cmdset 0001 primary query table */ -cfi_fixup_t cfi_0001_fixups[] = { - {0, 0, NULL, NULL} -}; - -void cfi_fixup(flash_bank_t *bank, cfi_fixup_t *fixups) -{ - cfi_flash_bank_t *cfi_info = bank->driver_priv; - cfi_fixup_t *f; - - for (f = fixups; f->fixup; f++) - { - if (((f->mfr == CFI_MFR_ANY) || (f->mfr == cfi_info->manufacturer)) && - ((f->id == CFI_ID_ANY) || (f->id == cfi_info->device_id))) - { - f->fixup(bank, f->param); - } - } -} - -inline u32 flash_address(flash_bank_t *bank, int sector, u32 offset) -{ - /* while the sector list isn't built, only accesses to sector 0 work */ - if (sector == 0) - return bank->base + offset * bank->bus_width; - else - { - if (!bank->sectors) - { - ERROR("BUG: sector list not yet built"); - exit(-1); - } - return bank->base + bank->sectors[sector].offset + offset * bank->bus_width; - } - -} - -void cfi_command(flash_bank_t *bank, u8 cmd, u8 *cmd_buf) -{ - int i; - - /* clear whole buffer, to ensure bits that exceed the bus_width - * are set to zero - */ - for (i = 0; i < CFI_MAX_BUS_WIDTH; i++) - cmd_buf[i] = 0; - - if (bank->target->endianness == TARGET_LITTLE_ENDIAN) - { - for (i = bank->bus_width; i > 0; i--) - { - *cmd_buf++ = (i & (bank->chip_width - 1)) ? 0x0 : cmd; - } - } - else - { - for (i = 1; i <= bank->bus_width; i++) - { - *cmd_buf++ = (i & (bank->chip_width - 1)) ? 0x0 : cmd; - } - } -} - -/* read unsigned 8-bit value from the bank - * flash banks are expected to be made of similar chips - * the query result should be the same for all - */ -u8 cfi_query_u8(flash_bank_t *bank, int sector, u32 offset) -{ - target_t *target = bank->target; - u8 data[CFI_MAX_BUS_WIDTH]; - - target->type->read_memory(target, flash_address(bank, sector, offset), bank->bus_width, 1, data); - - if (bank->target->endianness == TARGET_LITTLE_ENDIAN) - return data[0]; - else - return data[bank->bus_width - 1]; -} - -/* read unsigned 8-bit value from the bank - * in case of a bank made of multiple chips, - * the individual values are ORed - */ -u8 cfi_get_u8(flash_bank_t *bank, int sector, u32 offset) -{ - target_t *target = bank->target; - u8 data[CFI_MAX_BUS_WIDTH]; - int i; - - target->type->read_memory(target, flash_address(bank, sector, offset), bank->bus_width, 1, data); - - if (bank->target->endianness == TARGET_LITTLE_ENDIAN) - { - for (i = 0; i < bank->bus_width / bank->chip_width; i++) - data[0] |= data[i]; - - return data[0]; - } - else - { - u8 value = 0; - for (i = 0; i < bank->bus_width / bank->chip_width; i++) - value |= data[bank->bus_width - 1 - i]; - - return value; - } -} - -u16 cfi_query_u16(flash_bank_t *bank, int sector, u32 offset) -{ - target_t *target = bank->target; - u8 data[CFI_MAX_BUS_WIDTH * 2]; - - target->type->read_memory(target, flash_address(bank, sector, offset), bank->bus_width, 2, data); - - if (bank->target->endianness == TARGET_LITTLE_ENDIAN) - return data[0] | data[bank->bus_width] << 8; - else - return data[bank->bus_width - 1] | data[(2 * bank->bus_width) - 1] << 8; -} - -u32 cfi_query_u32(flash_bank_t *bank, int sector, u32 offset) -{ - target_t *target = bank->target; - u8 data[CFI_MAX_BUS_WIDTH * 4]; - - target->type->read_memory(target, flash_address(bank, sector, offset), bank->bus_width, 4, data); - - if (bank->target->endianness == TARGET_LITTLE_ENDIAN) - return data[0] | data[bank->bus_width] << 8 | data[bank->bus_width * 2] << 16 | data[bank->bus_width * 3] << 24; - else - return data[bank->bus_width - 1] | data[(2* bank->bus_width) - 1] << 8 | - data[(3 * bank->bus_width) - 1] << 16 | data[(4 * bank->bus_width) - 1] << 24; -} - -void cfi_intel_clear_status_register(flash_bank_t *bank) -{ - target_t *target = bank->target; - u8 command[8]; - - if (target->state != TARGET_HALTED) - { - ERROR("BUG: attempted to clear status register while target wasn't halted"); - exit(-1); - } - - cfi_command(bank, 0x50, command); - target->type->write_memory(target, flash_address(bank, 0, 0x0), bank->bus_width, 1, command); -} - -u8 cfi_intel_wait_status_busy(flash_bank_t *bank, int timeout) -{ - u8 status; - - while ((!((status = cfi_get_u8(bank, 0, 0x0)) & 0x80)) && (timeout-- > 0)) - { - DEBUG("status: 0x%x", status); - usleep(1000); - } - - /* mask out bit 0 (reserved) */ - status = status & 0xfe; - - DEBUG("status: 0x%x", status); - - if ((status & 0x80) != 0x80) - { - ERROR("timeout while waiting for WSM to become ready"); - } - else if (status != 0x80) - { - ERROR("status register: 0x%x", status); - if (status & 0x2) - ERROR("Block Lock-Bit Detected, Operation Abort"); - if (status & 0x4) - ERROR("Program suspended"); - if (status & 0x8) - ERROR("Low Programming Voltage Detected, Operation Aborted"); - if (status & 0x10) - ERROR("Program Error / Error in Setting Lock-Bit"); - if (status & 0x20) - ERROR("Error in Block Erasure or Clear Lock-Bits"); - if (status & 0x40) - ERROR("Block Erase Suspended"); - - cfi_intel_clear_status_register(bank); - } - - return status; -} - -int cfi_spansion_wait_status_busy(flash_bank_t *bank, int timeout) -{ - u8 status, oldstatus; - - oldstatus = cfi_get_u8(bank, 0, 0x0); - - do { - status = cfi_get_u8(bank, 0, 0x0); - if ((status ^ oldstatus) & 0x40) { - if (status & 0x20) { - oldstatus = cfi_get_u8(bank, 0, 0x0); - status = cfi_get_u8(bank, 0, 0x0); - if ((status ^ oldstatus) & 0x40) { - ERROR("dq5 timeout, status: 0x%x", status); - return(ERROR_FLASH_OPERATION_FAILED); - } else { - DEBUG("status: 0x%x", status); - return(ERROR_OK); - } - } - } else { - DEBUG("status: 0x%x", status); - return(ERROR_OK); - } - - oldstatus = status; - usleep(1000); - } while (timeout-- > 0); - - ERROR("timeout, status: 0x%x", status); - - return(ERROR_FLASH_BUSY); -} - -int cfi_read_intel_pri_ext(flash_bank_t *bank) -{ - cfi_flash_bank_t *cfi_info = bank->driver_priv; - cfi_intel_pri_ext_t *pri_ext = malloc(sizeof(cfi_intel_pri_ext_t)); - target_t *target = bank->target; - u8 command[8]; - - cfi_info->pri_ext = pri_ext; - - pri_ext->pri[0] = cfi_query_u8(bank, 0, cfi_info->pri_addr + 0); - pri_ext->pri[1] = cfi_query_u8(bank, 0, cfi_info->pri_addr + 1); - pri_ext->pri[2] = cfi_query_u8(bank, 0, cfi_info->pri_addr + 2); - - if ((pri_ext->pri[0] != 'P') || (pri_ext->pri[1] != 'R') || (pri_ext->pri[2] != 'I')) - { - cfi_command(bank, 0xf0, command); - target->type->write_memory(target, flash_address(bank, 0, 0x0), bank->bus_width, 1, command); - cfi_command(bank, 0xff, command); - target->type->write_memory(target, flash_address(bank, 0, 0x0), bank->bus_width, 1, command); - return ERROR_FLASH_BANK_INVALID; - } - - pri_ext->major_version = cfi_query_u8(bank, 0, cfi_info->pri_addr + 3); - pri_ext->minor_version = cfi_query_u8(bank, 0, cfi_info->pri_addr + 4); - - DEBUG("pri: '%c%c%c', version: %c.%c", pri_ext->pri[0], pri_ext->pri[1], pri_ext->pri[2], pri_ext->major_version, pri_ext->minor_version); - - pri_ext->feature_support = cfi_query_u32(bank, 0, cfi_info->pri_addr + 5); - pri_ext->suspend_cmd_support = cfi_query_u8(bank, 0, cfi_info->pri_addr + 9); - pri_ext->blk_status_reg_mask = cfi_query_u16(bank, 0, cfi_info->pri_addr + 0xa); - - DEBUG("feature_support: 0x%x, suspend_cmd_support: 0x%x, blk_status_reg_mask: 0x%x", pri_ext->feature_support, pri_ext->suspend_cmd_support, pri_ext->blk_status_reg_mask); - - pri_ext->vcc_optimal = cfi_query_u8(bank, 0, cfi_info->pri_addr + 0xc); - pri_ext->vpp_optimal = cfi_query_u8(bank, 0, cfi_info->pri_addr + 0xd); - - DEBUG("Vcc opt: %1.1x.%1.1x, Vpp opt: %1.1x.%1.1x", - (pri_ext->vcc_optimal & 0xf0) >> 4, pri_ext->vcc_optimal & 0x0f, - (pri_ext->vpp_optimal & 0xf0) >> 4, pri_ext->vpp_optimal & 0x0f); - - pri_ext->num_protection_fields = cfi_query_u8(bank, 0, cfi_info->pri_addr + 0xe); - if (pri_ext->num_protection_fields != 1) - { - WARNING("expected one protection register field, but found %i", pri_ext->num_protection_fields); - } - - pri_ext->prot_reg_addr = cfi_query_u16(bank, 0, cfi_info->pri_addr + 0xf); - pri_ext->fact_prot_reg_size = cfi_query_u8(bank, 0, cfi_info->pri_addr + 0x11); - pri_ext->user_prot_reg_size = cfi_query_u8(bank, 0, cfi_info->pri_addr + 0x12); - - DEBUG("protection_fields: %i, prot_reg_addr: 0x%x, factory pre-programmed: %i, user programmable: %i", pri_ext->num_protection_fields, pri_ext->prot_reg_addr, 1 << pri_ext->fact_prot_reg_size, 1 << pri_ext->user_prot_reg_size); - - return ERROR_OK; -} - -int cfi_read_spansion_pri_ext(flash_bank_t *bank) -{ - cfi_flash_bank_t *cfi_info = bank->driver_priv; - cfi_spansion_pri_ext_t *pri_ext = malloc(sizeof(cfi_spansion_pri_ext_t)); - target_t *target = bank->target; - u8 command[8]; - - cfi_info->pri_ext = pri_ext; - - pri_ext->pri[0] = cfi_query_u8(bank, 0, cfi_info->pri_addr + 0); - pri_ext->pri[1] = cfi_query_u8(bank, 0, cfi_info->pri_addr + 1); - pri_ext->pri[2] = cfi_query_u8(bank, 0, cfi_info->pri_addr + 2); - - if ((pri_ext->pri[0] != 'P') || (pri_ext->pri[1] != 'R') || (pri_ext->pri[2] != 'I')) - { - cfi_command(bank, 0xf0, command); - target->type->write_memory(target, flash_address(bank, 0, 0x0), bank->bus_width, 1, command); - return ERROR_FLASH_BANK_INVALID; - } - - pri_ext->major_version = cfi_query_u8(bank, 0, cfi_info->pri_addr + 3); - pri_ext->minor_version = cfi_query_u8(bank, 0, cfi_info->pri_addr + 4); - - DEBUG("pri: '%c%c%c', version: %c.%c", pri_ext->pri[0], pri_ext->pri[1], pri_ext->pri[2], pri_ext->major_version, pri_ext->minor_version); - - pri_ext->SiliconRevision = cfi_query_u8(bank, 0, cfi_info->pri_addr + 5); - pri_ext->EraseSuspend = cfi_query_u8(bank, 0, cfi_info->pri_addr + 6); - pri_ext->BlkProt = cfi_query_u8(bank, 0, cfi_info->pri_addr + 7); - pri_ext->TmpBlkUnprotect = cfi_query_u8(bank, 0, cfi_info->pri_addr + 8); - pri_ext->BlkProtUnprot = cfi_query_u8(bank, 0, cfi_info->pri_addr + 9); - pri_ext->SimultaneousOps = cfi_query_u8(bank, 0, cfi_info->pri_addr + 10); - pri_ext->BurstMode = cfi_query_u8(bank, 0, cfi_info->pri_addr + 11); - pri_ext->PageMode = cfi_query_u8(bank, 0, cfi_info->pri_addr + 12); - pri_ext->VppMin = cfi_query_u8(bank, 0, cfi_info->pri_addr + 13); - pri_ext->VppMax = cfi_query_u8(bank, 0, cfi_info->pri_addr + 14); - pri_ext->TopBottom = cfi_query_u8(bank, 0, cfi_info->pri_addr + 15); - - DEBUG("Silicon Revision: 0x%x, Erase Suspend: 0x%x, Block protect: 0x%x", pri_ext->SiliconRevision, - pri_ext->EraseSuspend, pri_ext->BlkProt); - - DEBUG("Temporary Unprotect: 0x%x, Block Protect Scheme: 0x%x, Simultaneous Ops: 0x%x", pri_ext->TmpBlkUnprotect, - pri_ext->BlkProtUnprot, pri_ext->SimultaneousOps); - - DEBUG("Burst Mode: 0x%x, Page Mode: 0x%x, ", pri_ext->BurstMode, pri_ext->PageMode); - - - DEBUG("Vpp min: %2.2d.%1.1d, Vpp max: %2.2d.%1.1x", - (pri_ext->VppMin & 0xf0) >> 4, pri_ext->VppMin & 0x0f, - (pri_ext->VppMax & 0xf0) >> 4, pri_ext->VppMax & 0x0f); - - DEBUG("WP# protection 0x%x", pri_ext->TopBottom); - - /* default values for implementation specific workarounds */ - pri_ext->_unlock1 = cfi_unlock_addresses[CFI_UNLOCK_555_2AA].unlock1; - pri_ext->_unlock2 = cfi_unlock_addresses[CFI_UNLOCK_555_2AA].unlock2; - pri_ext->_reversed_geometry = 0; - - return ERROR_OK; -} - -int cfi_read_atmel_pri_ext(flash_bank_t *bank) -{ - cfi_atmel_pri_ext_t atmel_pri_ext; - cfi_flash_bank_t *cfi_info = bank->driver_priv; - cfi_spansion_pri_ext_t *pri_ext = malloc(sizeof(cfi_spansion_pri_ext_t)); - target_t *target = bank->target; - u8 command[8]; - - /* ATMEL devices use the same CFI primary command set (0x2) as AMD/Spansion, - * but a different primary extended query table. - * We read the atmel table, and prepare a valid AMD/Spansion query table. - */ - - memset(pri_ext, 0, sizeof(cfi_spansion_pri_ext_t)); - - cfi_info->pri_ext = pri_ext; - - atmel_pri_ext.pri[0] = cfi_query_u8(bank, 0, cfi_info->pri_addr + 0); - atmel_pri_ext.pri[1] = cfi_query_u8(bank, 0, cfi_info->pri_addr + 1); - atmel_pri_ext.pri[2] = cfi_query_u8(bank, 0, cfi_info->pri_addr + 2); - - if ((atmel_pri_ext.pri[0] != 'P') || (atmel_pri_ext.pri[1] != 'R') || (atmel_pri_ext.pri[2] != 'I')) - { - cfi_command(bank, 0xf0, command); - target->type->write_memory(target, flash_address(bank, 0, 0x0), bank->bus_width, 1, command); - return ERROR_FLASH_BANK_INVALID; - } - - pri_ext->pri[0] = atmel_pri_ext.pri[0]; - pri_ext->pri[1] = atmel_pri_ext.pri[1]; - pri_ext->pri[2] = atmel_pri_ext.pri[2]; - - atmel_pri_ext.major_version = cfi_query_u8(bank, 0, cfi_info->pri_addr + 3); - atmel_pri_ext.minor_version = cfi_query_u8(bank, 0, cfi_info->pri_addr + 4); - - DEBUG("pri: '%c%c%c', version: %c.%c", atmel_pri_ext.pri[0], atmel_pri_ext.pri[1], atmel_pri_ext.pri[2], atmel_pri_ext.major_version, atmel_pri_ext.minor_version); - - pri_ext->major_version = atmel_pri_ext.major_version; - pri_ext->minor_version = atmel_pri_ext.minor_version; - - atmel_pri_ext.features = cfi_query_u8(bank, 0, cfi_info->pri_addr + 5); - atmel_pri_ext.bottom_boot = cfi_query_u8(bank, 0, cfi_info->pri_addr + 6); - atmel_pri_ext.burst_mode = cfi_query_u8(bank, 0, cfi_info->pri_addr + 7); - atmel_pri_ext.page_mode = cfi_query_u8(bank, 0, cfi_info->pri_addr + 8); - - DEBUG("features: 0x%2.2x, bottom_boot: 0x%2.2x, burst_mode: 0x%2.2x, page_mode: 0x%2.2x", - atmel_pri_ext.features, atmel_pri_ext.bottom_boot, atmel_pri_ext.burst_mode, atmel_pri_ext.page_mode); - - if (atmel_pri_ext.features & 0x02) - pri_ext->EraseSuspend = 2; - - if (atmel_pri_ext.bottom_boot) - pri_ext->TopBottom = 2; - else - pri_ext->TopBottom = 3; - - pri_ext->_unlock1 = cfi_unlock_addresses[CFI_UNLOCK_555_2AA].unlock1; - pri_ext->_unlock2 = cfi_unlock_addresses[CFI_UNLOCK_555_2AA].unlock2; - - return ERROR_OK; -} - -int cfi_read_0002_pri_ext(flash_bank_t *bank) -{ - cfi_flash_bank_t *cfi_info = bank->driver_priv; - - if (cfi_info->manufacturer == CFI_MFR_ATMEL) - { - return cfi_read_atmel_pri_ext(bank); - } - else - { - return cfi_read_spansion_pri_ext(bank); - } -} - -int cfi_spansion_info(struct flash_bank_s *bank, char *buf, int buf_size) -{ - int printed; - cfi_flash_bank_t *cfi_info = bank->driver_priv; - cfi_spansion_pri_ext_t *pri_ext = cfi_info->pri_ext; - - printed = snprintf(buf, buf_size, "\nSpansion primary algorithm extend information:\n"); - buf += printed; - buf_size -= printed; - - printed = snprintf(buf, buf_size, "pri: '%c%c%c', version: %c.%c\n", pri_ext->pri[0], - pri_ext->pri[1], pri_ext->pri[2], - pri_ext->major_version, pri_ext->minor_version); - buf += printed; - buf_size -= printed; - - printed = snprintf(buf, buf_size, "Silicon Rev.: 0x%x, Address Sensitive unlock: 0x%x\n", - (pri_ext->SiliconRevision) >> 2, - (pri_ext->SiliconRevision) & 0x03); - buf += printed; - buf_size -= printed; - - printed = snprintf(buf, buf_size, "Erase Suspend: 0x%x, Sector Protect: 0x%x\n", - pri_ext->EraseSuspend, - pri_ext->BlkProt); - buf += printed; - buf_size -= printed; - - printed = snprintf(buf, buf_size, "VppMin: %2.2d.%1.1x, VppMax: %2.2d.%1.1x\n", - (pri_ext->VppMin & 0xf0) >> 4, pri_ext->VppMin & 0x0f, - (pri_ext->VppMax & 0xf0) >> 4, pri_ext->VppMax & 0x0f); - - return ERROR_OK; -} - -int cfi_intel_info(struct flash_bank_s *bank, char *buf, int buf_size) -{ - int printed; - cfi_flash_bank_t *cfi_info = bank->driver_priv; - cfi_intel_pri_ext_t *pri_ext = cfi_info->pri_ext; - - printed = snprintf(buf, buf_size, "\nintel primary algorithm extend information:\n"); - buf += printed; - buf_size -= printed; - - printed = snprintf(buf, buf_size, "pri: '%c%c%c', version: %c.%c\n", pri_ext->pri[0], pri_ext->pri[1], pri_ext->pri[2], pri_ext->major_version, pri_ext->minor_version); - buf += printed; - buf_size -= printed; - - printed = snprintf(buf, buf_size, "feature_support: 0x%x, suspend_cmd_support: 0x%x, blk_status_reg_mask: 0x%x\n", pri_ext->feature_support, pri_ext->suspend_cmd_support, pri_ext->blk_status_reg_mask); - buf += printed; - buf_size -= printed; - - printed = snprintf(buf, buf_size, "Vcc opt: %1.1x.%1.1x, Vpp opt: %1.1x.%1.1x\n", - (pri_ext->vcc_optimal & 0xf0) >> 4, pri_ext->vcc_optimal & 0x0f, - (pri_ext->vpp_optimal & 0xf0) >> 4, pri_ext->vpp_optimal & 0x0f); - buf += printed; - buf_size -= printed; - - printed = snprintf(buf, buf_size, "protection_fields: %i, prot_reg_addr: 0x%x, factory pre-programmed: %i, user programmable: %i\n", pri_ext->num_protection_fields, pri_ext->prot_reg_addr, 1 << pri_ext->fact_prot_reg_size, 1 << pri_ext->user_prot_reg_size); - - return ERROR_OK; -} - -int cfi_register_commands(struct command_context_s *cmd_ctx) -{ - /*command_t *cfi_cmd = */ - register_command(cmd_ctx, NULL, "cfi", NULL, COMMAND_ANY, "flash bank cfi [jedec_probe/x16_as_x8]"); - /* - register_command(cmd_ctx, cfi_cmd, "part_id", cfi_handle_part_id_command, COMMAND_EXEC, - "print part id of cfi flash bank "); - */ - return ERROR_OK; -} - -/* flash_bank cfi [options] - */ -int cfi_flash_bank_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc, struct flash_bank_s *bank) -{ - cfi_flash_bank_t *cfi_info; - int i; - - if (argc < 6) - { - WARNING("incomplete flash_bank cfi configuration"); - return ERROR_FLASH_BANK_INVALID; - } - - if ((strtoul(args[4], NULL, 0) > CFI_MAX_CHIP_WIDTH) - || (strtoul(args[3], NULL, 0) > CFI_MAX_BUS_WIDTH)) - { - ERROR("chip and bus width have to specified in bytes"); - return ERROR_FLASH_BANK_INVALID; - } - - cfi_info = malloc(sizeof(cfi_flash_bank_t)); - cfi_info->probed = 0; - bank->driver_priv = cfi_info; - - cfi_info->write_algorithm = NULL; - cfi_info->erase_check_algorithm = NULL; - - cfi_info->x16_as_x8 = 0; - cfi_info->jedec_probe = 0; - cfi_info->not_cfi = 0; - - for (i = 6; i < argc; i++) - { - if (strcmp(args[i], "x16_as_x8") == 0) - { - cfi_info->x16_as_x8 = 1; - } - else if (strcmp(args[i], "jedec_probe") == 0) - { - cfi_info->jedec_probe = 1; - } - } - - cfi_info->write_algorithm = NULL; - - /* bank wasn't probed yet */ - cfi_info->qry[0] = -1; - - return ERROR_OK; -} - -int cfi_intel_erase(struct flash_bank_s *bank, int first, int last) -{ - cfi_flash_bank_t *cfi_info = bank->driver_priv; - target_t *target = bank->target; - u8 command[8]; - int i; - - cfi_intel_clear_status_register(bank); - - for (i = first; i <= last; i++) - { - cfi_command(bank, 0x20, command); - target->type->write_memory(target, flash_address(bank, i, 0x0), bank->bus_width, 1, command); - - cfi_command(bank, 0xd0, command); - target->type->write_memory(target, flash_address(bank, i, 0x0), bank->bus_width, 1, command); - - if (cfi_intel_wait_status_busy(bank, 1000 * (1 << cfi_info->block_erase_timeout_typ)) == 0x80) - bank->sectors[i].is_erased = 1; - else - { - cfi_command(bank, 0xff, command); - target->type->write_memory(target, flash_address(bank, 0, 0x0), bank->bus_width, 1, command); - - ERROR("couldn't erase block %i of flash bank at base 0x%x", i, bank->base); - return ERROR_FLASH_OPERATION_FAILED; - } - } - - cfi_command(bank, 0xff, command); - target->type->write_memory(target, flash_address(bank, 0, 0x0), bank->bus_width, 1, command); - - return ERROR_OK; -} - -int cfi_spansion_erase(struct flash_bank_s *bank, int first, int last) -{ - cfi_flash_bank_t *cfi_info = bank->driver_priv; - cfi_spansion_pri_ext_t *pri_ext = cfi_info->pri_ext; - target_t *target = bank->target; - u8 command[8]; - int i; - - for (i = first; i <= last; i++) - { - cfi_command(bank, 0xaa, command); - target->type->write_memory(target, flash_address(bank, 0, pri_ext->_unlock1), bank->bus_width, 1, command); - - cfi_command(bank, 0x55, command); - target->type->write_memory(target, flash_address(bank, 0, pri_ext->_unlock2), bank->bus_width, 1, command); - - cfi_command(bank, 0x80, command); - target->type->write_memory(target, flash_address(bank, 0, pri_ext->_unlock1), bank->bus_width, 1, command); - - cfi_command(bank, 0xaa, command); - target->type->write_memory(target, flash_address(bank, 0, pri_ext->_unlock1), bank->bus_width, 1, command); - - cfi_command(bank, 0x55, command); - target->type->write_memory(target, flash_address(bank, 0, pri_ext->_unlock2), bank->bus_width, 1, command); - - cfi_command(bank, 0x30, command); - target->type->write_memory(target, flash_address(bank, i, 0x0), bank->bus_width, 1, command); - - if (cfi_spansion_wait_status_busy(bank, 1000 * (1 << cfi_info->block_erase_timeout_typ)) == ERROR_OK) - bank->sectors[i].is_erased = 1; - else - { - cfi_command(bank, 0xf0, command); - target->type->write_memory(target, flash_address(bank, 0, 0x0), bank->bus_width, 1, command); - - ERROR("couldn't erase block %i of flash bank at base 0x%x", i, bank->base); - return ERROR_FLASH_OPERATION_FAILED; - } - } - - cfi_command(bank, 0xf0, command); - target->type->write_memory(target, flash_address(bank, 0, 0x0), bank->bus_width, 1, command); - - return ERROR_OK; -} - -int cfi_erase(struct flash_bank_s *bank, int first, int last) -{ - cfi_flash_bank_t *cfi_info = bank->driver_priv; - - if (bank->target->state != TARGET_HALTED) - { - return ERROR_TARGET_NOT_HALTED; - } - - if ((first < 0) || (last < first) || (last >= bank->num_sectors)) - { - return ERROR_FLASH_SECTOR_INVALID; - } - - if (cfi_info->qry[0] != 'Q') - return ERROR_FLASH_BANK_NOT_PROBED; - - switch(cfi_info->pri_id) - { - case 1: - case 3: - return cfi_intel_erase(bank, first, last); - break; - case 2: - return cfi_spansion_erase(bank, first, last); - break; - default: - ERROR("cfi primary command set %i unsupported", cfi_info->pri_id); - break; - } - - return ERROR_OK; -} - -int cfi_intel_protect(struct flash_bank_s *bank, int set, int first, int last) -{ - cfi_flash_bank_t *cfi_info = bank->driver_priv; - cfi_intel_pri_ext_t *pri_ext = cfi_info->pri_ext; - target_t *target = bank->target; - u8 command[8]; - int retry = 0; - int i; - - /* if the device supports neither legacy lock/unlock (bit 3) nor - * instant individual block locking (bit 5). - */ - if (!(pri_ext->feature_support & 0x28)) - return ERROR_FLASH_OPERATION_FAILED; - - cfi_intel_clear_status_register(bank); - - for (i = first; i <= last; i++) - { - cfi_command(bank, 0x60, command); - DEBUG("address: 0x%4.4x, command: 0x%4.4x", flash_address(bank, i, 0x0), target_buffer_get_u32(target, command)); - target->type->write_memory(target, flash_address(bank, i, 0x0), bank->bus_width, 1, command); - if (set) - { - cfi_command(bank, 0x01, command); - DEBUG("address: 0x%4.4x, command: 0x%4.4x", flash_address(bank, i, 0x0), target_buffer_get_u32(target, command)); - target->type->write_memory(target, flash_address(bank, i, 0x0), bank->bus_width, 1, command); - bank->sectors[i].is_protected = 1; - } - else - { - cfi_command(bank, 0xd0, command); - DEBUG("address: 0x%4.4x, command: 0x%4.4x", flash_address(bank, i, 0x0), target_buffer_get_u32(target, command)); - target->type->write_memory(target, flash_address(bank, i, 0x0), bank->bus_width, 1, command); - bank->sectors[i].is_protected = 0; - } - - /* instant individual block locking doesn't require reading of the status register */ - if (!(pri_ext->feature_support & 0x20)) - { - /* Clear lock bits operation may take up to 1.4s */ - cfi_intel_wait_status_busy(bank, 1400); - } - else - { - u8 block_status; - /* read block lock bit, to verify status */ - cfi_command(bank, 0x90, command); - target->type->write_memory(target, flash_address(bank, 0, 0x55), bank->bus_width, 1, command); - block_status = cfi_get_u8(bank, i, 0x2); - - if ((block_status & 0x1) != set) - { - ERROR("couldn't change block lock status (set = %i, block_status = 0x%2.2x)", set, block_status); - cfi_command(bank, 0x70, command); - target->type->write_memory(target, flash_address(bank, 0, 0x55), bank->bus_width, 1, command); - cfi_intel_wait_status_busy(bank, 10); - - if (retry > 10) - return ERROR_FLASH_OPERATION_FAILED; - else - { - i--; - retry++; - } - } - } - } - - /* if the device doesn't support individual block lock bits set/clear, - * all blocks have been unlocked in parallel, so we set those that should be protected - */ - if ((!set) && (!(pri_ext->feature_support & 0x20))) - { - for (i = 0; i < bank->num_sectors; i++) - { - if (bank->sectors[i].is_protected == 1) - { - cfi_intel_clear_status_register(bank); - - cfi_command(bank, 0x60, command); - target->type->write_memory(target, flash_address(bank, i, 0x0), bank->bus_width, 1, command); - - cfi_command(bank, 0x01, command); - target->type->write_memory(target, flash_address(bank, i, 0x0), bank->bus_width, 1, command); - - cfi_intel_wait_status_busy(bank, 100); - } - } - } - - cfi_command(bank, 0xff, command); - target->type->write_memory(target, flash_address(bank, 0, 0x0), bank->bus_width, 1, command); - - return ERROR_OK; -} - -int cfi_protect(struct flash_bank_s *bank, int set, int first, int last) -{ - cfi_flash_bank_t *cfi_info = bank->driver_priv; - - if (bank->target->state != TARGET_HALTED) - { - return ERROR_TARGET_NOT_HALTED; - } - - if ((first < 0) || (last < first) || (last >= bank->num_sectors)) - { - return ERROR_FLASH_SECTOR_INVALID; - } - - if (cfi_info->qry[0] != 'Q') - return ERROR_FLASH_BANK_NOT_PROBED; - - switch(cfi_info->pri_id) - { - case 1: - case 3: - cfi_intel_protect(bank, set, first, last); - break; - default: - ERROR("cfi primary command set %i unsupported", cfi_info->pri_id); - break; - } - - return ERROR_OK; -} - -/* FIXME Replace this by a simple memcpy() - still unsure about sideeffects */ -static void cfi_add_byte(struct flash_bank_s *bank, u8 *word, u8 byte) -{ - //target_t *target = bank->target; - - int i; - - // NOTE: - // The data to flash must not be changed in endian! We write a bytestrem in - // target byte order already. Only the control and status byte lane of the flash - // WSM is interpreted by the CPU in different ways, when read a u16 or u32 - // word (data seems to be in the upper or lower byte lane for u16 accesses). - - //if (target->endianness == TARGET_LITTLE_ENDIAN) - //{ - /* shift bytes */ - for (i = 0; i < bank->bus_width - 1; i++) - word[i] = word[i + 1]; - word[bank->bus_width - 1] = byte; - //} - //else - //{ - // /* shift bytes */ - // for (i = bank->bus_width - 1; i > 0; i--) - // word[i] = word[i - 1]; - // word[0] = byte; - //} -} - -/* Convert code image to target endian */ -/* FIXME create general block conversion fcts in target.c?) */ static -void cfi_fix_code_endian(target_t *target, u32 *dest, const u32 *src, u32 count) -{ - u32 i; - for (i=0; i< count; i++) - { - target_buffer_set_u32(target, (u8*)dest, *src); - dest++; - src++; - } -} - -int cfi_intel_write_block(struct flash_bank_s *bank, u8 *buffer, u32 address, u32 count) -{ - cfi_flash_bank_t *cfi_info = bank->driver_priv; - target_t *target = bank->target; - reg_param_t reg_params[7]; - armv4_5_algorithm_t armv4_5_info; - working_area_t *source; - u32 buffer_size = 32768; - u8 write_command_buf[CFI_MAX_BUS_WIDTH]; - u8 busy_pattern_buf[CFI_MAX_BUS_WIDTH]; - u8 error_pattern_buf[CFI_MAX_BUS_WIDTH]; - u32 write_command_val, busy_pattern_val, error_pattern_val; - - /* algorithm register usage: - * r0: source address (in RAM) - * r1: target address (in Flash) - * r2: count - * r3: flash write command - * r4: status byte (returned to host) - * r5: busy test pattern - * r6: error test pattern - */ - - static const u32 word_32_code[] = { - 0xe4904004, /* loop: ldr r4, [r0], #4 */ - 0xe5813000, /* str r3, [r1] */ - 0xe5814000, /* str r4, [r1] */ - 0xe5914000, /* busy: ldr r4, [r1] */ - 0xe0047005, /* and r7, r4, r5 */ - 0xe1570005, /* cmp r7, r5 */ - 0x1afffffb, /* bne busy */ - 0xe1140006, /* tst r4, r6 */ - 0x1a000003, /* bne done */ - 0xe2522001, /* subs r2, r2, #1 */ - 0x0a000001, /* beq done */ - 0xe2811004, /* add r1, r1 #4 */ - 0xeafffff2, /* b loop */ - 0xeafffffe /* done: b -2 */ - }; - - static const u32 word_16_code[] = { - 0xe0d040b2, /* loop: ldrh r4, [r0], #2 */ - 0xe1c130b0, /* strh r3, [r1] */ - 0xe1c140b0, /* strh r4, [r1] */ - 0xe1d140b0, /* busy ldrh r4, [r1] */ - 0xe0047005, /* and r7, r4, r5 */ - 0xe1570005, /* cmp r7, r5 */ - 0x1afffffb, /* bne busy */ - 0xe1140006, /* tst r4, r6 */ - 0x1a000003, /* bne done */ - 0xe2522001, /* subs r2, r2, #1 */ - 0x0a000001, /* beq done */ - 0xe2811002, /* add r1, r1 #2 */ - 0xeafffff2, /* b loop */ - 0xeafffffe /* done: b -2 */ - }; - - static const u32 word_8_code[] = { - 0xe4d04001, /* loop: ldrb r4, [r0], #1 */ - 0xe5c13000, /* strb r3, [r1] */ - 0xe5c14000, /* strb r4, [r1] */ - 0xe5d14000, /* busy ldrb r4, [r1] */ - 0xe0047005, /* and r7, r4, r5 */ - 0xe1570005, /* cmp r7, r5 */ - 0x1afffffb, /* bne busy */ - 0xe1140006, /* tst r4, r6 */ - 0x1a000003, /* bne done */ - 0xe2522001, /* subs r2, r2, #1 */ - 0x0a000001, /* beq done */ - 0xe2811001, /* add r1, r1 #1 */ - 0xeafffff2, /* b loop */ - 0xeafffffe /* done: b -2 */ - }; - u32 target_code[CFI_MAX_INTEL_CODESIZE]; - const u32 *target_code_src; - int target_code_size; - int retval = ERROR_OK; - - - cfi_intel_clear_status_register(bank); - - armv4_5_info.common_magic = ARMV4_5_COMMON_MAGIC; - armv4_5_info.core_mode = ARMV4_5_MODE_SVC; - armv4_5_info.core_state = ARMV4_5_STATE_ARM; - - /* If we are setting up the write_algorith, we need target_code_src */ - /* if not we only need target_code_size. */ - /* */ - /* However, we don't want to create multiple code paths, so we */ - /* do the unecessary evaluation of target_code_src, which the */ - /* compiler will probably nicely optimize away if not needed */ - - /* prepare algorithm code for target endian */ - switch (bank->bus_width) - { - case 1 : - target_code_src = word_8_code; - target_code_size = sizeof(word_8_code); - break; - case 2 : - target_code_src = word_16_code; - target_code_size = sizeof(word_16_code); - break; - case 4 : - target_code_src = word_32_code; - target_code_size = sizeof(word_32_code); - break; - default: - ERROR("Unsupported bank buswidth %d, can't do block memory writes", bank->bus_width); - return ERROR_TARGET_RESOURCE_NOT_AVAILABLE; - } - - /* flash write code */ - if (!cfi_info->write_algorithm) - { - if ( target_code_size > sizeof(target_code) ) - { - WARNING("Internal error - target code buffer to small. Increase CFI_MAX_INTEL_CODESIZE and recompile."); - return ERROR_TARGET_RESOURCE_NOT_AVAILABLE; - } - cfi_fix_code_endian(target, target_code, target_code_src, target_code_size); - - /* Get memory for block write handler */ - retval = target_alloc_working_area(target, target_code_size, &cfi_info->write_algorithm); - if (retval != ERROR_OK) - { - WARNING("No working area available, can't do block memory writes"); - return ERROR_TARGET_RESOURCE_NOT_AVAILABLE; - }; - - /* write algorithm code to working area */ - retval = target_write_buffer(target, cfi_info->write_algorithm->address, target_code_size, (u8*)target_code); - if (retval != ERROR_OK) - { - ERROR("Unable to write block write code to target"); - goto cleanup; - } - } - - /* Get a workspace buffer for the data to flash starting with 32k size. - Half size until buffer would be smaller 256 Bytem then fail back */ - /* FIXME Why 256 bytes, why not 32 bytes (smallest flash write page */ - while (target_alloc_working_area(target, buffer_size, &source) != ERROR_OK) - { - buffer_size /= 2; - if (buffer_size <= 256) - { - WARNING("no large enough working area available, can't do block memory writes"); - retval = ERROR_TARGET_RESOURCE_NOT_AVAILABLE; - goto cleanup; - } - }; - - /* setup algo registers */ - init_reg_param(®_params[0], "r0", 32, PARAM_OUT); - init_reg_param(®_params[1], "r1", 32, PARAM_OUT); - init_reg_param(®_params[2], "r2", 32, PARAM_OUT); - init_reg_param(®_params[3], "r3", 32, PARAM_OUT); - init_reg_param(®_params[4], "r4", 32, PARAM_IN); - init_reg_param(®_params[5], "r5", 32, PARAM_OUT); - init_reg_param(®_params[6], "r6", 32, PARAM_OUT); - - /* prepare command and status register patterns */ - cfi_command(bank, 0x40, write_command_buf); - cfi_command(bank, 0x80, busy_pattern_buf); - cfi_command(bank, 0x7e, error_pattern_buf); - - switch (bank->bus_width) - { - case 1 : - write_command_val = write_command_buf[0]; - busy_pattern_val = busy_pattern_buf[0]; - error_pattern_val = error_pattern_buf[0]; - break; - case 2 : - write_command_val = target_buffer_get_u16(target, write_command_buf); - busy_pattern_val = target_buffer_get_u16(target, busy_pattern_buf); - error_pattern_val = target_buffer_get_u16(target, error_pattern_buf); - break; - case 4 : - write_command_val = target_buffer_get_u32(target, write_command_buf); - busy_pattern_val = target_buffer_get_u32(target, busy_pattern_buf); - error_pattern_val = target_buffer_get_u32(target, error_pattern_buf); - break; - default : - ERROR("Unsupported bank buswidth %d, can't do block memory writes", bank->bus_width); - retval = ERROR_TARGET_RESOURCE_NOT_AVAILABLE; - goto cleanup; - } - - INFO("Using target buffer at 0x%08x and of size 0x%04x", source->address, buffer_size ); - - /* Programming main loop */ - while (count > 0) - { - u32 thisrun_count = (count > buffer_size) ? buffer_size : count; - u32 wsm_error; - - target_write_buffer(target, source->address, thisrun_count, buffer); - - buf_set_u32(reg_params[0].value, 0, 32, source->address); - buf_set_u32(reg_params[1].value, 0, 32, address); - buf_set_u32(reg_params[2].value, 0, 32, thisrun_count / bank->bus_width); - - buf_set_u32(reg_params[3].value, 0, 32, write_command_val); - buf_set_u32(reg_params[5].value, 0, 32, busy_pattern_val); - buf_set_u32(reg_params[6].value, 0, 32, error_pattern_val); - - INFO("Write 0x%04x bytes to flash at 0x%08x", thisrun_count, address ); - - /* Execute algorithm, assume breakpoint for last instruction */ - retval = target->type->run_algorithm(target, 0, NULL, 7, reg_params, - cfi_info->write_algorithm->address, - cfi_info->write_algorithm->address + target_code_size - sizeof(u32), - 10000, /* 10s should be enough for max. 32k of data */ - &armv4_5_info); - - /* On failure try a fall back to direct word writes */ - if (retval != ERROR_OK) - { - cfi_intel_clear_status_register(bank); - ERROR("Execution of flash algorythm failed. Can't fall back. Please report."); - retval = ERROR_FLASH_OPERATION_FAILED; - //retval = ERROR_TARGET_RESOURCE_NOT_AVAILABLE; - // FIXME To allow fall back or recovery, we must save the actual status - // somewhere, so that a higher level code can start recovery. - goto cleanup; - } - - /* Check return value from algo code */ - wsm_error = buf_get_u32(reg_params[4].value, 0, 32) & error_pattern_val; - if (wsm_error) - { - /* read status register (outputs debug inforation) */ - cfi_intel_wait_status_busy(bank, 100); - cfi_intel_clear_status_register(bank); - retval = ERROR_FLASH_OPERATION_FAILED; - goto cleanup; - } - - buffer += thisrun_count; - address += thisrun_count; - count -= thisrun_count; - } - - /* free up resources */ -cleanup: - if (source) - target_free_working_area(target, source); - - if (cfi_info->write_algorithm) - { - target_free_working_area(target, cfi_info->write_algorithm); - cfi_info->write_algorithm = NULL; - } - - destroy_reg_param(®_params[0]); - destroy_reg_param(®_params[1]); - destroy_reg_param(®_params[2]); - destroy_reg_param(®_params[3]); - destroy_reg_param(®_params[4]); - destroy_reg_param(®_params[5]); - destroy_reg_param(®_params[6]); - - return retval; -} - -int cfi_spansion_write_block(struct flash_bank_s *bank, u8 *buffer, u32 address, u32 count) -{ - cfi_flash_bank_t *cfi_info = bank->driver_priv; - cfi_spansion_pri_ext_t *pri_ext = cfi_info->pri_ext; - target_t *target = bank->target; - reg_param_t reg_params[10]; - armv4_5_algorithm_t armv4_5_info; - working_area_t *source; - u32 buffer_size = 32768; - u8 write_command[CFI_MAX_BUS_WIDTH]; - u32 status; - int i; - int retval; - int exit_code = ERROR_OK; - - /* input parameters - */ - /* R0 = source address */ - /* R1 = destination address */ - /* R2 = number of writes */ - /* R3 = flash write command */ - /* R4 = constant to mask DQ7 bits (also used for Dq5 with shift) */ - /* output parameters - */ - /* R5 = 0x80 ok 0x00 bad */ - /* temp registers - */ - /* R6 = value read from flash to test status */ - /* R7 = holding register */ - /* unlock registers - */ - /* R8 = unlock1_addr */ - /* R9 = unlock1_cmd */ - /* R10 = unlock2_addr */ - /* R11 = unlock2_cmd */ - - u32 word_32_code[] = { - /* 00008100 : */ - 0xe4905004, /* ldr r5, [r0], #4 */ - 0xe5889000, /* str r9, [r8] */ - 0xe58ab000, /* str r11, [r10] */ - 0xe5883000, /* str r3, [r8] */ - 0xe5815000, /* str r5, [r1] */ - 0xe1a00000, /* nop */ - /* */ - /* 00008110 : */ - 0xe5916000, /* ldr r6, [r1] */ - 0xe0257006, /* eor r7, r5, r6 */ - 0xe0147007, /* ands r7, r4, r7 */ - 0x0a000007, /* beq 8140 ; b if DQ7 == Data7 */ - 0xe0166124, /* ands r6, r6, r4, lsr #2 */ - 0x0afffff9, /* beq 8110 ; b if DQ5 low */ - 0xe5916000, /* ldr r6, [r1] */ - 0xe0257006, /* eor r7, r5, r6 */ - 0xe0147007, /* ands r7, r4, r7 */ - 0x0a000001, /* beq 8140 ; b if DQ7 == Data7 */ - 0xe3a05000, /* mov r5, #0 ; 0x0 - return 0x00, error */ - 0x1a000004, /* bne 8154 */ - /* */ - /* 00008140 : */ - 0xe2522001, /* subs r2, r2, #1 ; 0x1 */ - 0x03a05080, /* moveq r5, #128 ; 0x80 */ - 0x0a000001, /* beq 8154 */ - 0xe2811004, /* add r1, r1, #4 ; 0x4 */ - 0xeaffffe8, /* b 8100 */ - /* */ - /* 00008154 : */ - 0xeafffffe /* b 8154 */ - }; - - u32 word_16_code[] = { - /* 00008158 : */ - 0xe0d050b2, /* ldrh r5, [r0], #2 */ - 0xe1c890b0, /* strh r9, [r8] */ - 0xe1cab0b0, /* strh r11, [r10] */ - 0xe1c830b0, /* strh r3, [r8] */ - 0xe1c150b0, /* strh r5, [r1] */ - 0xe1a00000, /* nop (mov r0,r0) */ - /* */ - /* 00008168 : */ - 0xe1d160b0, /* ldrh r6, [r1] */ - 0xe0257006, /* eor r7, r5, r6 */ - 0xe0147007, /* ands r7, r4, r7 */ - 0x0a000007, /* beq 8198 */ - 0xe0166124, /* ands r6, r6, r4, lsr #2 */ - 0x0afffff9, /* beq 8168 */ - 0xe1d160b0, /* ldrh r6, [r1] */ - 0xe0257006, /* eor r7, r5, r6 */ - 0xe0147007, /* ands r7, r4, r7 */ - 0x0a000001, /* beq 8198 */ - 0xe3a05000, /* mov r5, #0 ; 0x0 */ - 0x1a000004, /* bne 81ac */ - /* */ - /* 00008198 : */ - 0xe2522001, /* subs r2, r2, #1 ; 0x1 */ - 0x03a05080, /* moveq r5, #128 ; 0x80 */ - 0x0a000001, /* beq 81ac */ - 0xe2811002, /* add r1, r1, #2 ; 0x2 */ - 0xeaffffe8, /* b 8158 */ - /* */ - /* 000081ac : */ - 0xeafffffe /* b 81ac */ - }; - - u32 word_8_code[] = { - /* 000081b0 : */ - 0xe4d05001, /* ldrb r5, [r0], #1 */ - 0xe5c89000, /* strb r9, [r8] */ - 0xe5cab000, /* strb r11, [r10] */ - 0xe5c83000, /* strb r3, [r8] */ - 0xe5c15000, /* strb r5, [r1] */ - 0xe1a00000, /* nop (mov r0,r0) */ - /* */ - /* 000081c0 : */ - 0xe5d16000, /* ldrb r6, [r1] */ - 0xe0257006, /* eor r7, r5, r6 */ - 0xe0147007, /* ands r7, r4, r7 */ - 0x0a000007, /* beq 81f0 */ - 0xe0166124, /* ands r6, r6, r4, lsr #2 */ - 0x0afffff9, /* beq 81c0 */ - 0xe5d16000, /* ldrb r6, [r1] */ - 0xe0257006, /* eor r7, r5, r6 */ - 0xe0147007, /* ands r7, r4, r7 */ - 0x0a000001, /* beq 81f0 */ - 0xe3a05000, /* mov r5, #0 ; 0x0 */ - 0x1a000004, /* bne 8204 */ - /* */ - /* 000081f0 : */ - 0xe2522001, /* subs r2, r2, #1 ; 0x1 */ - 0x03a05080, /* moveq r5, #128 ; 0x80 */ - 0x0a000001, /* beq 8204 */ - 0xe2811001, /* add r1, r1, #1 ; 0x1 */ - 0xeaffffe8, /* b 81b0 */ - /* */ - /* 00008204 : */ - 0xeafffffe /* b 8204 */ - }; - - armv4_5_info.common_magic = ARMV4_5_COMMON_MAGIC; - armv4_5_info.core_mode = ARMV4_5_MODE_SVC; - armv4_5_info.core_state = ARMV4_5_STATE_ARM; - - /* flash write code */ - if (!cfi_info->write_algorithm) - { - u8 *code_p; - - /* convert bus-width dependent algorithm code to correct endiannes */ - if (bank->bus_width == 1) - { - code_p = malloc(24 * 4); - - for (i = 0; i < 24; i++) - target_buffer_set_u32(target, code_p + (i*4), word_8_code[i]); - } - else if (bank->bus_width == 2) - { - code_p = malloc(24 * 4); - - for (i = 0; i < 24; i++) - target_buffer_set_u32(target, code_p + (i*4), word_16_code[i]); - } - else if (bank->bus_width == 4) - { - code_p = malloc(24 * 4); - - for (i = 0; i < 24; i++) - target_buffer_set_u32(target, code_p + (i*4), word_32_code[i]); - } - else - { - return ERROR_FLASH_OPERATION_FAILED; - } - - /* allocate working area */ - retval=target_alloc_working_area(target, 24 * 4, - &cfi_info->write_algorithm); - if (retval != ERROR_OK) - { - return retval; - } - - /* write algorithm code to working area */ - target_write_buffer(target, cfi_info->write_algorithm->address, 24 * 4, code_p); - - free(code_p); - } - - while (target_alloc_working_area(target, buffer_size, &source) != ERROR_OK) - { - buffer_size /= 2; - if (buffer_size <= 256) - { - /* if we already allocated the writing code, but failed to get a buffer, free the algorithm */ - if (cfi_info->write_algorithm) - target_free_working_area(target, cfi_info->write_algorithm); - - WARNING("not enough working area available, can't do block memory writes"); - return ERROR_TARGET_RESOURCE_NOT_AVAILABLE; - } - }; - - init_reg_param(®_params[0], "r0", 32, PARAM_OUT); - init_reg_param(®_params[1], "r1", 32, PARAM_OUT); - init_reg_param(®_params[2], "r2", 32, PARAM_OUT); - init_reg_param(®_params[3], "r3", 32, PARAM_OUT); - init_reg_param(®_params[4], "r4", 32, PARAM_OUT); - init_reg_param(®_params[5], "r5", 32, PARAM_IN); - init_reg_param(®_params[6], "r8", 32, PARAM_OUT); - init_reg_param(®_params[7], "r9", 32, PARAM_OUT); - init_reg_param(®_params[8], "r10", 32, PARAM_OUT); - init_reg_param(®_params[9], "r11", 32, PARAM_OUT); - - while (count > 0) - { - u32 thisrun_count = (count > buffer_size) ? buffer_size : count; - - target_write_buffer(target, source->address, thisrun_count, buffer); - - buf_set_u32(reg_params[0].value, 0, 32, source->address); - buf_set_u32(reg_params[1].value, 0, 32, address); - buf_set_u32(reg_params[2].value, 0, 32, thisrun_count / bank->bus_width); - cfi_command(bank, 0xA0, write_command); - buf_set_u32(reg_params[3].value, 0, 32, buf_get_u32(write_command, 0, 32)); - cfi_command(bank, 0x80, write_command); - buf_set_u32(reg_params[4].value, 0, 32, buf_get_u32(write_command, 0, 32)); - buf_set_u32(reg_params[6].value, 0, 32, flash_address(bank, 0, pri_ext->_unlock1)); - buf_set_u32(reg_params[7].value, 0, 32, 0xaa); - buf_set_u32(reg_params[8].value, 0, 32, flash_address(bank, 0, pri_ext->_unlock2)); - buf_set_u32(reg_params[9].value, 0, 32, 0x55); - - retval = target->type->run_algorithm(target, 0, NULL, 10, reg_params, - cfi_info->write_algorithm->address, - cfi_info->write_algorithm->address + ((24 * 4) - 4), - 10000, &armv4_5_info); - - status = buf_get_u32(reg_params[5].value, 0, 32); - - if ((retval != ERROR_OK) || status != 0x80) - { - DEBUG("status: 0x%x", status); - exit_code = ERROR_FLASH_OPERATION_FAILED; - break; - } - - buffer += thisrun_count; - address += thisrun_count; - count -= thisrun_count; - } - - target_free_working_area(target, source); - - destroy_reg_param(®_params[0]); - destroy_reg_param(®_params[1]); - destroy_reg_param(®_params[2]); - destroy_reg_param(®_params[3]); - destroy_reg_param(®_params[4]); - destroy_reg_param(®_params[5]); - destroy_reg_param(®_params[6]); - destroy_reg_param(®_params[7]); - destroy_reg_param(®_params[8]); - destroy_reg_param(®_params[9]); - - return exit_code; -} - -int cfi_intel_write_word(struct flash_bank_s *bank, u8 *word, u32 address) -{ - cfi_flash_bank_t *cfi_info = bank->driver_priv; - target_t *target = bank->target; - u8 command[8]; - - cfi_intel_clear_status_register(bank); - cfi_command(bank, 0x40, command); - target->type->write_memory(target, address, bank->bus_width, 1, command); - - target->type->write_memory(target, address, bank->bus_width, 1, word); - - if (cfi_intel_wait_status_busy(bank, 1000 * (1 << cfi_info->word_write_timeout_max)) != 0x80) - { - cfi_command(bank, 0xff, command); - target->type->write_memory(target, flash_address(bank, 0, 0x0), bank->bus_width, 1, command); - - ERROR("couldn't write word at base 0x%x, address %x", bank->base, address); - return ERROR_FLASH_OPERATION_FAILED; - } - - return ERROR_OK; -} - -int cfi_intel_write_words(struct flash_bank_s *bank, u8 *word, u32 wordcount, u32 address) -{ - cfi_flash_bank_t *cfi_info = bank->driver_priv; - target_t *target = bank->target; - u8 command[8]; - - /* Calculate buffer size and boundary mask */ - u32 buffersize = 1UL << cfi_info->max_buf_write_size; - u32 buffermask = buffersize-1; - u32 bufferwsize; - - /* Check for valid range */ - if (address & buffermask) - { - ERROR("Write address at base 0x%x, address %x not aligned to 2^%d boundary", bank->base, address, cfi_info->max_buf_write_size); - return ERROR_FLASH_OPERATION_FAILED; - } - switch(bank->chip_width) - { - case 4 : bufferwsize = buffersize / 4; break; - case 2 : bufferwsize = buffersize / 2; break; - case 1 : bufferwsize = buffersize; break; - default: - ERROR("Unsupported chip width %d", bank->chip_width); - return ERROR_FLASH_OPERATION_FAILED; - } - - /* Check for valid size */ - if (wordcount > bufferwsize) - { - ERROR("Number of data words %d exceeds available buffersize %d", wordcount, buffersize); - return ERROR_FLASH_OPERATION_FAILED; - } - - /* Write to flash buffer */ - cfi_intel_clear_status_register(bank); - - /* Initiate buffer operation _*/ - cfi_command(bank, 0xE8, command); - target->type->write_memory(target, address, bank->bus_width, 1, command); - if (cfi_intel_wait_status_busy(bank, 1000 * (1 << cfi_info->buf_write_timeout_max)) != 0x80) - { - cfi_command(bank, 0xff, command); - target->type->write_memory(target, flash_address(bank, 0, 0x0), bank->bus_width, 1, command); - - ERROR("couldn't start buffer write operation at base 0x%x, address %x", bank->base, address); - return ERROR_FLASH_OPERATION_FAILED; - } - - /* Write buffer wordcount-1 and data words */ - cfi_command(bank, bufferwsize-1, command); - target->type->write_memory(target, address, bank->bus_width, 1, command); - - target->type->write_memory(target, address, bank->bus_width, bufferwsize, word); - - /* Commit write operation */ - cfi_command(bank, 0xd0, command); - target->type->write_memory(target, address, bank->bus_width, 1, command); - if (cfi_intel_wait_status_busy(bank, 1000 * (1 << cfi_info->buf_write_timeout_max)) != 0x80) - { - cfi_command(bank, 0xff, command); - target->type->write_memory(target, flash_address(bank, 0, 0x0), bank->bus_width, 1, command); - - ERROR("Buffer write at base 0x%x, address %x failed.", bank->base, address); - return ERROR_FLASH_OPERATION_FAILED; - } - - return ERROR_OK; -} - -int cfi_spansion_write_word(struct flash_bank_s *bank, u8 *word, u32 address) -{ - cfi_flash_bank_t *cfi_info = bank->driver_priv; - cfi_spansion_pri_ext_t *pri_ext = cfi_info->pri_ext; - target_t *target = bank->target; - u8 command[8]; - - cfi_command(bank, 0xaa, command); - target->type->write_memory(target, flash_address(bank, 0, pri_ext->_unlock1), bank->bus_width, 1, command); - - cfi_command(bank, 0x55, command); - target->type->write_memory(target, flash_address(bank, 0, pri_ext->_unlock2), bank->bus_width, 1, command); - - cfi_command(bank, 0xa0, command); - target->type->write_memory(target, flash_address(bank, 0, pri_ext->_unlock1), bank->bus_width, 1, command); - - target->type->write_memory(target, address, bank->bus_width, 1, word); - - if (cfi_spansion_wait_status_busy(bank, 1000 * (1 << cfi_info->word_write_timeout_max)) != ERROR_OK) - { - cfi_command(bank, 0xf0, command); - target->type->write_memory(target, flash_address(bank, 0, 0x0), bank->bus_width, 1, command); - - ERROR("couldn't write word at base 0x%x, address %x", bank->base, address); - return ERROR_FLASH_OPERATION_FAILED; - } - - return ERROR_OK; -} - -int cfi_write_word(struct flash_bank_s *bank, u8 *word, u32 address) -{ - cfi_flash_bank_t *cfi_info = bank->driver_priv; - - switch(cfi_info->pri_id) - { - case 1: - case 3: - return cfi_intel_write_word(bank, word, address); - break; - case 2: - return cfi_spansion_write_word(bank, word, address); - break; - default: - ERROR("cfi primary command set %i unsupported", cfi_info->pri_id); - break; - } - - return ERROR_FLASH_OPERATION_FAILED; -} - -int cfi_write_words(struct flash_bank_s *bank, u8 *word, u32 wordcount, u32 address) -{ - cfi_flash_bank_t *cfi_info = bank->driver_priv; - - switch(cfi_info->pri_id) - { - case 1: - case 3: - return cfi_intel_write_words(bank, word, wordcount, address); - break; - case 2: - //return cfi_spansion_write_words(bank, word, address); - ERROR("cfi primary command set %i unimplemented - FIXME", cfi_info->pri_id); - break; - default: - ERROR("cfi primary command set %i unsupported", cfi_info->pri_id); - break; - } - - return ERROR_FLASH_OPERATION_FAILED; -} - -int cfi_write(struct flash_bank_s *bank, u8 *buffer, u32 offset, u32 count) -{ - cfi_flash_bank_t *cfi_info = bank->driver_priv; - target_t *target = bank->target; - u32 address = bank->base + offset; /* address of first byte to be programmed */ - u32 write_p, copy_p; - int align; /* number of unaligned bytes */ - int blk_count; /* number of bus_width bytes for block copy */ - u8 current_word[CFI_MAX_BUS_WIDTH * 4]; /* word (bus_width size) currently being programmed */ - int i; - int retval; - - if (offset + count > bank->size) - return ERROR_FLASH_DST_OUT_OF_BANK; - - if (cfi_info->qry[0] != 'Q') - return ERROR_FLASH_BANK_NOT_PROBED; - - /* start at the first byte of the first word (bus_width size) */ - write_p = address & ~(bank->bus_width - 1); - if ((align = address - write_p) != 0) - { - INFO("Fixup %d unaligned head bytes", align ); - - for (i = 0; i < bank->bus_width; i++) - current_word[i] = 0; - copy_p = write_p; - - /* copy bytes before the first write address */ - for (i = 0; i < align; ++i, ++copy_p) - { - u8 byte; - target->type->read_memory(target, copy_p, 1, 1, &byte); - cfi_add_byte(bank, current_word, byte); - } - - /* add bytes from the buffer */ - for (; (i < bank->bus_width) && (count > 0); i++) - { - cfi_add_byte(bank, current_word, *buffer++); - count--; - copy_p++; - } - - /* if the buffer is already finished, copy bytes after the last write address */ - for (; (count == 0) && (i < bank->bus_width); ++i, ++copy_p) - { - u8 byte; - target->type->read_memory(target, copy_p, 1, 1, &byte); - cfi_add_byte(bank, current_word, byte); - } - - retval = cfi_write_word(bank, current_word, write_p); - if (retval != ERROR_OK) - return retval; - write_p = copy_p; - } - - /* handle blocks of bus_size aligned bytes */ - blk_count = count & ~(bank->bus_width - 1); /* round down, leave tail bytes */ - switch(cfi_info->pri_id) - { - /* try block writes (fails without working area) */ - case 1: - case 3: - retval = cfi_intel_write_block(bank, buffer, write_p, blk_count); - break; - case 2: - retval = cfi_spansion_write_block(bank, buffer, write_p, blk_count); - break; - default: - ERROR("cfi primary command set %i unsupported", cfi_info->pri_id); - retval = ERROR_FLASH_OPERATION_FAILED; - break; - } - if (retval == ERROR_OK) - { - /* Increment pointers and decrease count on succesful block write */ - buffer += blk_count; - write_p += blk_count; - count -= blk_count; - } - else - { - if (retval == ERROR_TARGET_RESOURCE_NOT_AVAILABLE) - { - u32 buffersize = 1UL << cfi_info->max_buf_write_size; - u32 buffermask = buffersize-1; - u32 bufferwsize; - - switch(bank->chip_width) - { - case 4 : bufferwsize = buffersize / 4; break; - case 2 : bufferwsize = buffersize / 2; break; - case 1 : bufferwsize = buffersize; break; - default: - ERROR("Unsupported chip width %d", bank->chip_width); - return ERROR_FLASH_OPERATION_FAILED; - } - - /* fall back to memory writes */ - while (count > bank->bus_width) - { - if ((write_p & 0xff) == 0) - { - INFO("Programming at %08x, count %08x bytes remaining", write_p, count); - } -#if 0 - /* NB! this is broken for spansion! */ - if ((count > bufferwsize) && !(write_p & buffermask)) - { - retval = cfi_write_words(bank, buffer, bufferwsize, write_p); - if (retval != ERROR_OK) - return retval; - - buffer += buffersize; - write_p += buffersize; - count -= buffersize; - } - else -#endif - { - for (i = 0; i < bank->bus_width; i++) - current_word[i] = 0; - - for (i = 0; i < bank->bus_width; i++) - { - cfi_add_byte(bank, current_word, *buffer++); - } - - retval = cfi_write_word(bank, current_word, write_p); - if (retval != ERROR_OK) - return retval; - - write_p += bank->bus_width; - count -= bank->bus_width; - } - } - } - else - return retval; - } - - /* return to read array mode, so we can read from flash again for padding */ - cfi_command(bank, 0xf0, current_word); - target->type->write_memory(target, flash_address(bank, 0, 0x0), bank->bus_width, 1, current_word); - cfi_command(bank, 0xff, current_word); - target->type->write_memory(target, flash_address(bank, 0, 0x0), bank->bus_width, 1, current_word); - - /* handle unaligned tail bytes */ - if (count > 0) - { - INFO("Fixup %d unaligned tail bytes", count ); - - copy_p = write_p; - for (i = 0; i < bank->bus_width; i++) - current_word[i] = 0; - - for (i = 0; (i < bank->bus_width) && (count > 0); ++i, ++copy_p) - { - cfi_add_byte(bank, current_word, *buffer++); - count--; - } - for (; i < bank->bus_width; ++i, ++copy_p) - { - u8 byte; - target->type->read_memory(target, copy_p, 1, 1, &byte); - cfi_add_byte(bank, current_word, byte); - } - retval = cfi_write_word(bank, current_word, write_p); - if (retval != ERROR_OK) - return retval; - } - - /* return to read array mode */ - cfi_command(bank, 0xf0, current_word); - target->type->write_memory(target, flash_address(bank, 0, 0x0), bank->bus_width, 1, current_word); - cfi_command(bank, 0xff, current_word); - target->type->write_memory(target, flash_address(bank, 0, 0x0), bank->bus_width, 1, current_word); - - return ERROR_OK; -} - -void cfi_fixup_atmel_reversed_erase_regions(flash_bank_t *bank, void *param) -{ - cfi_flash_bank_t *cfi_info = bank->driver_priv; - cfi_spansion_pri_ext_t *pri_ext = cfi_info->pri_ext; - - pri_ext->_reversed_geometry = 1; -} - -void cfi_fixup_0002_erase_regions(flash_bank_t *bank, void *param) -{ - int i; - cfi_flash_bank_t *cfi_info = bank->driver_priv; - cfi_spansion_pri_ext_t *pri_ext = cfi_info->pri_ext; - - if ((pri_ext->_reversed_geometry) || (pri_ext->TopBottom == 3)) - { - DEBUG("swapping reversed erase region information on cmdset 0002 device"); - - for (i = 0; i < cfi_info->num_erase_regions / 2; i++) - { - int j = (cfi_info->num_erase_regions - 1) - i; - u32 swap; - - swap = cfi_info->erase_region_info[i]; - cfi_info->erase_region_info[i] = cfi_info->erase_region_info[j]; - cfi_info->erase_region_info[j] = swap; - } - } -} - -void cfi_fixup_0002_unlock_addresses(flash_bank_t *bank, void *param) -{ - cfi_flash_bank_t *cfi_info = bank->driver_priv; - cfi_spansion_pri_ext_t *pri_ext = cfi_info->pri_ext; - cfi_unlock_addresses_t *unlock_addresses = param; - - pri_ext->_unlock1 = unlock_addresses->unlock1; - pri_ext->_unlock2 = unlock_addresses->unlock2; -} - -int cfi_probe(struct flash_bank_s *bank) -{ - cfi_flash_bank_t *cfi_info = bank->driver_priv; - target_t *target = bank->target; - u8 command[8]; - int num_sectors = 0; - int i; - int sector = 0; - u32 offset = 0; - u32 unlock1 = 0x555; - u32 unlock2 = 0x2aa; - - cfi_info->probed = 0; - - /* JEDEC standard JESD21C uses 0x5555 and 0x2aaa as unlock addresses, - * while CFI compatible AMD/Spansion flashes use 0x555 and 0x2aa - */ - if (cfi_info->jedec_probe) - { - unlock1 = 0x5555; - unlock2 = 0x2aaa; - } - - /* switch to read identifier codes mode ("AUTOSELECT") */ - cfi_command(bank, 0xaa, command); - target->type->write_memory(target, flash_address(bank, 0, unlock1), bank->bus_width, 1, command); - cfi_command(bank, 0x55, command); - target->type->write_memory(target, flash_address(bank, 0, unlock2), bank->bus_width, 1, command); - cfi_command(bank, 0x90, command); - target->type->write_memory(target, flash_address(bank, 0, unlock1), bank->bus_width, 1, command); - - if (bank->chip_width == 1) - { - u8 manufacturer, device_id; - target_read_u8(target, bank->base + 0x0, &manufacturer); - target_read_u8(target, bank->base + 0x1, &device_id); - cfi_info->manufacturer = manufacturer; - cfi_info->device_id = device_id; - } - else if (bank->chip_width == 2) - { - target_read_u16(target, bank->base + 0x0, &cfi_info->manufacturer); - target_read_u16(target, bank->base + 0x2, &cfi_info->device_id); - } - - /* switch back to read array mode */ - cfi_command(bank, 0xf0, command); - target->type->write_memory(target, flash_address(bank, 0, 0x00), bank->bus_width, 1, command); - cfi_command(bank, 0xff, command); - target->type->write_memory(target, flash_address(bank, 0, 0x00), bank->bus_width, 1, command); - - cfi_fixup(bank, cfi_jedec_fixups); - - /* query only if this is a CFI compatible flash, - * otherwise the relevant info has already been filled in - */ - if (cfi_info->not_cfi == 0) - { - /* enter CFI query mode - * according to JEDEC Standard No. 68.01, - * a single bus sequence with address = 0x55, data = 0x98 should put - * the device into CFI query mode. - * - * SST flashes clearly violate this, and we will consider them incompatbile for now - */ - cfi_command(bank, 0x98, command); - target->type->write_memory(target, flash_address(bank, 0, 0x55), bank->bus_width, 1, command); - - cfi_info->qry[0] = cfi_query_u8(bank, 0, 0x10); - cfi_info->qry[1] = cfi_query_u8(bank, 0, 0x11); - cfi_info->qry[2] = cfi_query_u8(bank, 0, 0x12); - - DEBUG("CFI qry returned: 0x%2.2x 0x%2.2x 0x%2.2x", cfi_info->qry[0], cfi_info->qry[1], cfi_info->qry[2]); - - if ((cfi_info->qry[0] != 'Q') || (cfi_info->qry[1] != 'R') || (cfi_info->qry[2] != 'Y')) - { - cfi_command(bank, 0xf0, command); - target->type->write_memory(target, flash_address(bank, 0, 0x0), bank->bus_width, 1, command); - cfi_command(bank, 0xff, command); - target->type->write_memory(target, flash_address(bank, 0, 0x0), bank->bus_width, 1, command); - return ERROR_FLASH_BANK_INVALID; - } - - cfi_info->pri_id = cfi_query_u16(bank, 0, 0x13); - cfi_info->pri_addr = cfi_query_u16(bank, 0, 0x15); - cfi_info->alt_id = cfi_query_u16(bank, 0, 0x17); - cfi_info->alt_addr = cfi_query_u16(bank, 0, 0x19); - - DEBUG("qry: '%c%c%c', pri_id: 0x%4.4x, pri_addr: 0x%4.4x, alt_id: 0x%4.4x, alt_addr: 0x%4.4x", cfi_info->qry[0], cfi_info->qry[1], cfi_info->qry[2], cfi_info->pri_id, cfi_info->pri_addr, cfi_info->alt_id, cfi_info->alt_addr); - - cfi_info->vcc_min = cfi_query_u8(bank, 0, 0x1b); - cfi_info->vcc_max = cfi_query_u8(bank, 0, 0x1c); - cfi_info->vpp_min = cfi_query_u8(bank, 0, 0x1d); - cfi_info->vpp_max = cfi_query_u8(bank, 0, 0x1e); - cfi_info->word_write_timeout_typ = cfi_query_u8(bank, 0, 0x1f); - cfi_info->buf_write_timeout_typ = cfi_query_u8(bank, 0, 0x20); - cfi_info->block_erase_timeout_typ = cfi_query_u8(bank, 0, 0x21); - cfi_info->chip_erase_timeout_typ = cfi_query_u8(bank, 0, 0x22); - cfi_info->word_write_timeout_max = cfi_query_u8(bank, 0, 0x23); - cfi_info->buf_write_timeout_max = cfi_query_u8(bank, 0, 0x24); - cfi_info->block_erase_timeout_max = cfi_query_u8(bank, 0, 0x25); - cfi_info->chip_erase_timeout_max = cfi_query_u8(bank, 0, 0x26); - - DEBUG("Vcc min: %1.1x.%1.1x, Vcc max: %1.1x.%1.1x, Vpp min: %1.1x.%1.1x, Vpp max: %1.1x.%1.1x", - (cfi_info->vcc_min & 0xf0) >> 4, cfi_info->vcc_min & 0x0f, - (cfi_info->vcc_max & 0xf0) >> 4, cfi_info->vcc_max & 0x0f, - (cfi_info->vpp_min & 0xf0) >> 4, cfi_info->vpp_min & 0x0f, - (cfi_info->vpp_max & 0xf0) >> 4, cfi_info->vpp_max & 0x0f); - DEBUG("typ. word write timeout: %u, typ. buf write timeout: %u, typ. block erase timeout: %u, typ. chip erase timeout: %u", 1 << cfi_info->word_write_timeout_typ, 1 << cfi_info->buf_write_timeout_typ, - 1 << cfi_info->block_erase_timeout_typ, 1 << cfi_info->chip_erase_timeout_typ); - DEBUG("max. word write timeout: %u, max. buf write timeout: %u, max. block erase timeout: %u, max. chip erase timeout: %u", (1 << cfi_info->word_write_timeout_max) * (1 << cfi_info->word_write_timeout_typ), - (1 << cfi_info->buf_write_timeout_max) * (1 << cfi_info->buf_write_timeout_typ), - (1 << cfi_info->block_erase_timeout_max) * (1 << cfi_info->block_erase_timeout_typ), - (1 << cfi_info->chip_erase_timeout_max) * (1 << cfi_info->chip_erase_timeout_typ)); - - cfi_info->dev_size = cfi_query_u8(bank, 0, 0x27); - cfi_info->interface_desc = cfi_query_u16(bank, 0, 0x28); - cfi_info->max_buf_write_size = cfi_query_u16(bank, 0, 0x2a); - cfi_info->num_erase_regions = cfi_query_u8(bank, 0, 0x2c); - - DEBUG("size: 0x%x, interface desc: %i, max buffer write size: %x", 1 << cfi_info->dev_size, cfi_info->interface_desc, (1 << cfi_info->max_buf_write_size)); - - if (((1 << cfi_info->dev_size) * bank->bus_width / bank->chip_width) != bank->size) - { - WARNING("configuration specifies 0x%x size, but a 0x%x size flash was found", bank->size, 1 << cfi_info->dev_size); - } - - if (cfi_info->num_erase_regions) - { - cfi_info->erase_region_info = malloc(4 * cfi_info->num_erase_regions); - for (i = 0; i < cfi_info->num_erase_regions; i++) - { - cfi_info->erase_region_info[i] = cfi_query_u32(bank, 0, 0x2d + (4 * i)); - DEBUG("erase region[%i]: %i blocks of size 0x%x", i, (cfi_info->erase_region_info[i] & 0xffff) + 1, (cfi_info->erase_region_info[i] >> 16) * 256); - } - } - else - { - cfi_info->erase_region_info = NULL; - } - - /* We need to read the primary algorithm extended query table before calculating - * the sector layout to be able to apply fixups - */ - switch(cfi_info->pri_id) - { - /* Intel command set (standard and extended) */ - case 0x0001: - case 0x0003: - cfi_read_intel_pri_ext(bank); - break; - /* AMD/Spansion, Atmel, ... command set */ - case 0x0002: - cfi_read_0002_pri_ext(bank); - break; - default: - ERROR("cfi primary command set %i unsupported", cfi_info->pri_id); - break; - } - - /* return to read array mode - * we use both reset commands, as some Intel flashes fail to recognize the 0xF0 command - */ - cfi_command(bank, 0xf0, command); - target->type->write_memory(target, flash_address(bank, 0, 0x0), bank->bus_width, 1, command); - cfi_command(bank, 0xff, command); - target->type->write_memory(target, flash_address(bank, 0, 0x0), bank->bus_width, 1, command); - } - - /* apply fixups depending on the primary command set */ - switch(cfi_info->pri_id) - { - /* Intel command set (standard and extended) */ - case 0x0001: - case 0x0003: - cfi_fixup(bank, cfi_0001_fixups); - break; - /* AMD/Spansion, Atmel, ... command set */ - case 0x0002: - cfi_fixup(bank, cfi_0002_fixups); - break; - default: - ERROR("cfi primary command set %i unsupported", cfi_info->pri_id); - break; - } - - if (cfi_info->num_erase_regions == 0) - { - /* a device might have only one erase block, spanning the whole device */ - bank->num_sectors = 1; - bank->sectors = malloc(sizeof(flash_sector_t)); - - bank->sectors[sector].offset = 0x0; - bank->sectors[sector].size = bank->size; - bank->sectors[sector].is_erased = -1; - bank->sectors[sector].is_protected = -1; - } - else - { - for (i = 0; i < cfi_info->num_erase_regions; i++) - { - num_sectors += (cfi_info->erase_region_info[i] & 0xffff) + 1; - } - - bank->num_sectors = num_sectors; - bank->sectors = malloc(sizeof(flash_sector_t) * num_sectors); - - for (i = 0; i < cfi_info->num_erase_regions; i++) - { - int j; - for (j = 0; j < (cfi_info->erase_region_info[i] & 0xffff) + 1; j++) - { - bank->sectors[sector].offset = offset; - bank->sectors[sector].size = ((cfi_info->erase_region_info[i] >> 16) * 256) * bank->bus_width / bank->chip_width; - offset += bank->sectors[sector].size; - bank->sectors[sector].is_erased = -1; - bank->sectors[sector].is_protected = -1; - sector++; - } - } - } - - cfi_info->probed = 1; - - return ERROR_OK; -} - -int cfi_auto_probe(struct flash_bank_s *bank) -{ - cfi_flash_bank_t *cfi_info = bank->driver_priv; - if (cfi_info->probed) - return ERROR_OK; - return cfi_probe(bank); -} - -int cfi_erase_check(struct flash_bank_s *bank) -{ - cfi_flash_bank_t *cfi_info = bank->driver_priv; - target_t *target = bank->target; - int i; - int retval; - - if (!cfi_info->erase_check_algorithm) - { - u32 erase_check_code[] = - { - 0xe4d03001, /* ldrb r3, [r0], #1 */ - 0xe0022003, /* and r2, r2, r3 */ - 0xe2511001, /* subs r1, r1, #1 */ - 0x1afffffb, /* b -4 */ - 0xeafffffe /* b 0 */ - }; - - /* make sure we have a working area */ - if (target_alloc_working_area(target, 20, &cfi_info->erase_check_algorithm) != ERROR_OK) - { - WARNING("no working area available, falling back to slow memory reads"); - } - else - { - u8 erase_check_code_buf[5 * 4]; - - for (i = 0; i < 5; i++) - target_buffer_set_u32(target, erase_check_code_buf + (i*4), erase_check_code[i]); - - /* write algorithm code to working area */ - target->type->write_memory(target, cfi_info->erase_check_algorithm->address, 4, 5, erase_check_code_buf); - } - } - - if (!cfi_info->erase_check_algorithm) - { - u32 *buffer = malloc(4096); - - for (i = 0; i < bank->num_sectors; i++) - { - u32 address = bank->base + bank->sectors[i].offset; - u32 size = bank->sectors[i].size; - u32 check = 0xffffffffU; - int erased = 1; - - while (size > 0) - { - u32 thisrun_size = (size > 4096) ? 4096 : size; - int j; - - target->type->read_memory(target, address, 4, thisrun_size / 4, (u8*)buffer); - - for (j = 0; j < thisrun_size / 4; j++) - check &= buffer[j]; - - if (check != 0xffffffff) - { - erased = 0; - break; - } - - size -= thisrun_size; - address += thisrun_size; - } - - bank->sectors[i].is_erased = erased; - } - - free(buffer); - } - else - { - for (i = 0; i < bank->num_sectors; i++) - { - u32 address = bank->base + bank->sectors[i].offset; - u32 size = bank->sectors[i].size; - - reg_param_t reg_params[3]; - armv4_5_algorithm_t armv4_5_info; - - armv4_5_info.common_magic = ARMV4_5_COMMON_MAGIC; - armv4_5_info.core_mode = ARMV4_5_MODE_SVC; - armv4_5_info.core_state = ARMV4_5_STATE_ARM; - - init_reg_param(®_params[0], "r0", 32, PARAM_OUT); - buf_set_u32(reg_params[0].value, 0, 32, address); - - init_reg_param(®_params[1], "r1", 32, PARAM_OUT); - buf_set_u32(reg_params[1].value, 0, 32, size); - - init_reg_param(®_params[2], "r2", 32, PARAM_IN_OUT); - buf_set_u32(reg_params[2].value, 0, 32, 0xff); - - if ((retval = target->type->run_algorithm(target, 0, NULL, 3, reg_params, cfi_info->erase_check_algorithm->address, cfi_info->erase_check_algorithm->address + 0x10, 10000, &armv4_5_info)) != ERROR_OK) - return ERROR_FLASH_OPERATION_FAILED; - - if (buf_get_u32(reg_params[2].value, 0, 32) == 0xff) - bank->sectors[i].is_erased = 1; - else - bank->sectors[i].is_erased = 0; - - destroy_reg_param(®_params[0]); - destroy_reg_param(®_params[1]); - destroy_reg_param(®_params[2]); - } - } - - return ERROR_OK; -} - -int cfi_intel_protect_check(struct flash_bank_s *bank) -{ - cfi_flash_bank_t *cfi_info = bank->driver_priv; - cfi_intel_pri_ext_t *pri_ext = cfi_info->pri_ext; - target_t *target = bank->target; - u8 command[CFI_MAX_BUS_WIDTH]; - int i; - - /* check if block lock bits are supported on this device */ - if (!(pri_ext->blk_status_reg_mask & 0x1)) - return ERROR_FLASH_OPERATION_FAILED; - - cfi_command(bank, 0x90, command); - target->type->write_memory(target, flash_address(bank, 0, 0x55), bank->bus_width, 1, command); - - for (i = 0; i < bank->num_sectors; i++) - { - u8 block_status = cfi_get_u8(bank, i, 0x2); - - if (block_status & 1) - bank->sectors[i].is_protected = 1; - else - bank->sectors[i].is_protected = 0; - } - - cfi_command(bank, 0xff, command); - target->type->write_memory(target, flash_address(bank, 0, 0x0), bank->bus_width, 1, command); - - return ERROR_OK; -} - -int cfi_spansion_protect_check(struct flash_bank_s *bank) -{ - cfi_flash_bank_t *cfi_info = bank->driver_priv; - cfi_spansion_pri_ext_t *pri_ext = cfi_info->pri_ext; - target_t *target = bank->target; - u8 command[8]; - int i; - - cfi_command(bank, 0xaa, command); - target->type->write_memory(target, flash_address(bank, 0, pri_ext->_unlock1), bank->bus_width, 1, command); - - cfi_command(bank, 0x55, command); - target->type->write_memory(target, flash_address(bank, 0, pri_ext->_unlock2), bank->bus_width, 1, command); - - cfi_command(bank, 0x90, command); - target->type->write_memory(target, flash_address(bank, 0, pri_ext->_unlock1), bank->bus_width, 1, command); - - for (i = 0; i < bank->num_sectors; i++) - { - u8 block_status = cfi_get_u8(bank, i, 0x2); - - if (block_status & 1) - bank->sectors[i].is_protected = 1; - else - bank->sectors[i].is_protected = 0; - } - - cfi_command(bank, 0xf0, command); - target->type->write_memory(target, flash_address(bank, 0, 0x0), bank->bus_width, 1, command); - - return ERROR_OK; -} - -int cfi_protect_check(struct flash_bank_s *bank) -{ - cfi_flash_bank_t *cfi_info = bank->driver_priv; - - if (cfi_info->qry[0] != 'Q') - return ERROR_FLASH_BANK_NOT_PROBED; - - switch(cfi_info->pri_id) - { - case 1: - case 3: - return cfi_intel_protect_check(bank); - break; - case 2: - return cfi_spansion_protect_check(bank); - break; - default: - ERROR("cfi primary command set %i unsupported", cfi_info->pri_id); - break; - } - - return ERROR_OK; -} - -int cfi_info(struct flash_bank_s *bank, char *buf, int buf_size) -{ - int printed; - cfi_flash_bank_t *cfi_info = bank->driver_priv; - - if (cfi_info->qry[0] == (char)-1) - { - printed = snprintf(buf, buf_size, "\ncfi flash bank not probed yet\n"); - return ERROR_OK; - } - - printed = snprintf(buf, buf_size, "\ncfi information:\n"); - buf += printed; - buf_size -= printed; - - printed = snprintf(buf, buf_size, "\nmfr: 0x%4.4x, id:0x%4.4x\n", - cfi_info->manufacturer, cfi_info->device_id); - buf += printed; - buf_size -= printed; - - printed = snprintf(buf, buf_size, "qry: '%c%c%c', pri_id: 0x%4.4x, pri_addr: 0x%4.4x, alt_id: 0x%4.4x, alt_addr: 0x%4.4x\n", cfi_info->qry[0], cfi_info->qry[1], cfi_info->qry[2], cfi_info->pri_id, cfi_info->pri_addr, cfi_info->alt_id, cfi_info->alt_addr); - buf += printed; - buf_size -= printed; - - printed = snprintf(buf, buf_size, "Vcc min: %1.1x.%1.1x, Vcc max: %1.1x.%1.1x, Vpp min: %1.1x.%1.1x, Vpp max: %1.1x.%1.1x\n", (cfi_info->vcc_min & 0xf0) >> 4, cfi_info->vcc_min & 0x0f, - (cfi_info->vcc_max & 0xf0) >> 4, cfi_info->vcc_max & 0x0f, - (cfi_info->vpp_min & 0xf0) >> 4, cfi_info->vpp_min & 0x0f, - (cfi_info->vpp_max & 0xf0) >> 4, cfi_info->vpp_max & 0x0f); - buf += printed; - buf_size -= printed; - - printed = snprintf(buf, buf_size, "typ. word write timeout: %u, typ. buf write timeout: %u, typ. block erase timeout: %u, typ. chip erase timeout: %u\n", 1 << cfi_info->word_write_timeout_typ, 1 << cfi_info->buf_write_timeout_typ, - 1 << cfi_info->block_erase_timeout_typ, 1 << cfi_info->chip_erase_timeout_typ); - buf += printed; - buf_size -= printed; - - printed = snprintf(buf, buf_size, "max. word write timeout: %u, max. buf write timeout: %u, max. block erase timeout: %u, max. chip erase timeout: %u\n", (1 << cfi_info->word_write_timeout_max) * (1 << cfi_info->word_write_timeout_typ), - (1 << cfi_info->buf_write_timeout_max) * (1 << cfi_info->buf_write_timeout_typ), - (1 << cfi_info->block_erase_timeout_max) * (1 << cfi_info->block_erase_timeout_typ), - (1 << cfi_info->chip_erase_timeout_max) * (1 << cfi_info->chip_erase_timeout_typ)); - buf += printed; - buf_size -= printed; - - printed = snprintf(buf, buf_size, "size: 0x%x, interface desc: %i, max buffer write size: %x\n", 1 << cfi_info->dev_size, cfi_info->interface_desc, cfi_info->max_buf_write_size); - buf += printed; - buf_size -= printed; - - switch(cfi_info->pri_id) - { - case 1: - case 3: - cfi_intel_info(bank, buf, buf_size); - break; - case 2: - cfi_spansion_info(bank, buf, buf_size); - break; - default: - ERROR("cfi primary command set %i unsupported", cfi_info->pri_id); - break; - } - - return ERROR_OK; -} +/*************************************************************************** + * Copyright (C) 2005, 2007 by Dominic Rath * + * Dominic.Rath@gmx.de * + * * + * This program is free software; you can redistribute it and/or modify * + * it under the terms of the GNU General Public License as published by * + * the Free Software Foundation; either version 2 of the License, or * + * (at your option) any later version. * + * * + * This program is distributed in the hope that it will be useful, * + * but WITHOUT ANY WARRANTY; without even the implied warranty of * + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * + * GNU General Public License for more details. * + * * + * You should have received a copy of the GNU General Public License * + * along with this program; if not, write to the * + * Free Software Foundation, Inc., * + * 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. * + ***************************************************************************/ +#ifdef HAVE_CONFIG_H +#include "config.h" +#endif + +#include "replacements.h" + +#include "cfi.h" + +#include "flash.h" +#include "target.h" +#include "log.h" +#include "armv4_5.h" +#include "algorithm.h" +#include "binarybuffer.h" +#include "types.h" + +#include +#include +#include + +int cfi_register_commands(struct command_context_s *cmd_ctx); +int cfi_flash_bank_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc, struct flash_bank_s *bank); +int cfi_erase(struct flash_bank_s *bank, int first, int last); +int cfi_protect(struct flash_bank_s *bank, int set, int first, int last); +int cfi_write(struct flash_bank_s *bank, u8 *buffer, u32 offset, u32 count); +int cfi_probe(struct flash_bank_s *bank); +int cfi_auto_probe(struct flash_bank_s *bank); +int cfi_erase_check(struct flash_bank_s *bank); +int cfi_protect_check(struct flash_bank_s *bank); +int cfi_info(struct flash_bank_s *bank, char *buf, int buf_size); + +int cfi_handle_part_id_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc); + +#define CFI_MAX_BUS_WIDTH 4 +#define CFI_MAX_CHIP_WIDTH 4 + +/* defines internal maximum size for code fragment in cfi_intel_write_block() */ +#define CFI_MAX_INTEL_CODESIZE 256 + +flash_driver_t cfi_flash = +{ + .name = "cfi", + .register_commands = cfi_register_commands, + .flash_bank_command = cfi_flash_bank_command, + .erase = cfi_erase, + .protect = cfi_protect, + .write = cfi_write, + .probe = cfi_probe, + .auto_probe = cfi_auto_probe, + .erase_check = cfi_erase_check, + .protect_check = cfi_protect_check, + .info = cfi_info +}; + +cfi_unlock_addresses_t cfi_unlock_addresses[] = +{ + [CFI_UNLOCK_555_2AA] = { .unlock1 = 0x555, .unlock2 = 0x2aa }, + [CFI_UNLOCK_5555_2AAA] = { .unlock1 = 0x5555, .unlock2 = 0x2aaa }, +}; + +/* CFI fixups foward declarations */ +void cfi_fixup_non_cfi(flash_bank_t *flash, void *param); +void cfi_fixup_0002_erase_regions(flash_bank_t *flash, void *param); +void cfi_fixup_0002_unlock_addresses(flash_bank_t *flash, void *param); +void cfi_fixup_atmel_reversed_erase_regions(flash_bank_t *flash, void *param); + +/* fixup after identifying JEDEC manufactuer and ID */ +cfi_fixup_t cfi_jedec_fixups[] = { + {CFI_MFR_SST, 0x00D4, cfi_fixup_non_cfi, NULL}, + {CFI_MFR_SST, 0x00D5, cfi_fixup_non_cfi, NULL}, + {CFI_MFR_SST, 0x00D6, cfi_fixup_non_cfi, NULL}, + {CFI_MFR_SST, 0x00D7, cfi_fixup_non_cfi, NULL}, + {CFI_MFR_SST, 0x2780, cfi_fixup_non_cfi, NULL}, + {CFI_MFR_ST, 0x00D5, cfi_fixup_non_cfi, NULL}, + {CFI_MFR_ST, 0x00D6, cfi_fixup_non_cfi, NULL}, + {CFI_MFR_AMD, 0x2223, cfi_fixup_non_cfi, NULL}, + {CFI_MFR_AMD, 0x22ab, cfi_fixup_non_cfi, NULL}, + {0, 0, NULL, NULL} +}; + +/* fixup after reading cmdset 0002 primary query table */ +cfi_fixup_t cfi_0002_fixups[] = { + {CFI_MFR_SST, 0x00D4, cfi_fixup_0002_unlock_addresses, &cfi_unlock_addresses[CFI_UNLOCK_5555_2AAA]}, + {CFI_MFR_SST, 0x00D5, cfi_fixup_0002_unlock_addresses, &cfi_unlock_addresses[CFI_UNLOCK_5555_2AAA]}, + {CFI_MFR_SST, 0x00D6, cfi_fixup_0002_unlock_addresses, &cfi_unlock_addresses[CFI_UNLOCK_5555_2AAA]}, + {CFI_MFR_SST, 0x00D7, cfi_fixup_0002_unlock_addresses, &cfi_unlock_addresses[CFI_UNLOCK_5555_2AAA]}, + {CFI_MFR_SST, 0x2780, cfi_fixup_0002_unlock_addresses, &cfi_unlock_addresses[CFI_UNLOCK_5555_2AAA]}, + {CFI_MFR_ATMEL, 0x00C8, cfi_fixup_atmel_reversed_erase_regions, NULL}, + {CFI_MFR_ANY, CFI_ID_ANY, cfi_fixup_0002_erase_regions, NULL}, + {0, 0, NULL, NULL} +}; + +/* fixup after reading cmdset 0001 primary query table */ +cfi_fixup_t cfi_0001_fixups[] = { + {0, 0, NULL, NULL} +}; + +void cfi_fixup(flash_bank_t *bank, cfi_fixup_t *fixups) +{ + cfi_flash_bank_t *cfi_info = bank->driver_priv; + cfi_fixup_t *f; + + for (f = fixups; f->fixup; f++) + { + if (((f->mfr == CFI_MFR_ANY) || (f->mfr == cfi_info->manufacturer)) && + ((f->id == CFI_ID_ANY) || (f->id == cfi_info->device_id))) + { + f->fixup(bank, f->param); + } + } +} + +inline u32 flash_address(flash_bank_t *bank, int sector, u32 offset) +{ + /* while the sector list isn't built, only accesses to sector 0 work */ + if (sector == 0) + return bank->base + offset * bank->bus_width; + else + { + if (!bank->sectors) + { + ERROR("BUG: sector list not yet built"); + exit(-1); + } + return bank->base + bank->sectors[sector].offset + offset * bank->bus_width; + } + +} + +void cfi_command(flash_bank_t *bank, u8 cmd, u8 *cmd_buf) +{ + int i; + + /* clear whole buffer, to ensure bits that exceed the bus_width + * are set to zero + */ + for (i = 0; i < CFI_MAX_BUS_WIDTH; i++) + cmd_buf[i] = 0; + + if (bank->target->endianness == TARGET_LITTLE_ENDIAN) + { + for (i = bank->bus_width; i > 0; i--) + { + *cmd_buf++ = (i & (bank->chip_width - 1)) ? 0x0 : cmd; + } + } + else + { + for (i = 1; i <= bank->bus_width; i++) + { + *cmd_buf++ = (i & (bank->chip_width - 1)) ? 0x0 : cmd; + } + } +} + +/* read unsigned 8-bit value from the bank + * flash banks are expected to be made of similar chips + * the query result should be the same for all + */ +u8 cfi_query_u8(flash_bank_t *bank, int sector, u32 offset) +{ + target_t *target = bank->target; + u8 data[CFI_MAX_BUS_WIDTH]; + + target->type->read_memory(target, flash_address(bank, sector, offset), bank->bus_width, 1, data); + + if (bank->target->endianness == TARGET_LITTLE_ENDIAN) + return data[0]; + else + return data[bank->bus_width - 1]; +} + +/* read unsigned 8-bit value from the bank + * in case of a bank made of multiple chips, + * the individual values are ORed + */ +u8 cfi_get_u8(flash_bank_t *bank, int sector, u32 offset) +{ + target_t *target = bank->target; + u8 data[CFI_MAX_BUS_WIDTH]; + int i; + + target->type->read_memory(target, flash_address(bank, sector, offset), bank->bus_width, 1, data); + + if (bank->target->endianness == TARGET_LITTLE_ENDIAN) + { + for (i = 0; i < bank->bus_width / bank->chip_width; i++) + data[0] |= data[i]; + + return data[0]; + } + else + { + u8 value = 0; + for (i = 0; i < bank->bus_width / bank->chip_width; i++) + value |= data[bank->bus_width - 1 - i]; + + return value; + } +} + +u16 cfi_query_u16(flash_bank_t *bank, int sector, u32 offset) +{ + target_t *target = bank->target; + u8 data[CFI_MAX_BUS_WIDTH * 2]; + + target->type->read_memory(target, flash_address(bank, sector, offset), bank->bus_width, 2, data); + + if (bank->target->endianness == TARGET_LITTLE_ENDIAN) + return data[0] | data[bank->bus_width] << 8; + else + return data[bank->bus_width - 1] | data[(2 * bank->bus_width) - 1] << 8; +} + +u32 cfi_query_u32(flash_bank_t *bank, int sector, u32 offset) +{ + target_t *target = bank->target; + u8 data[CFI_MAX_BUS_WIDTH * 4]; + + target->type->read_memory(target, flash_address(bank, sector, offset), bank->bus_width, 4, data); + + if (bank->target->endianness == TARGET_LITTLE_ENDIAN) + return data[0] | data[bank->bus_width] << 8 | data[bank->bus_width * 2] << 16 | data[bank->bus_width * 3] << 24; + else + return data[bank->bus_width - 1] | data[(2* bank->bus_width) - 1] << 8 | + data[(3 * bank->bus_width) - 1] << 16 | data[(4 * bank->bus_width) - 1] << 24; +} + +void cfi_intel_clear_status_register(flash_bank_t *bank) +{ + target_t *target = bank->target; + u8 command[8]; + + if (target->state != TARGET_HALTED) + { + ERROR("BUG: attempted to clear status register while target wasn't halted"); + exit(-1); + } + + cfi_command(bank, 0x50, command); + target->type->write_memory(target, flash_address(bank, 0, 0x0), bank->bus_width, 1, command); +} + +u8 cfi_intel_wait_status_busy(flash_bank_t *bank, int timeout) +{ + u8 status; + + while ((!((status = cfi_get_u8(bank, 0, 0x0)) & 0x80)) && (timeout-- > 0)) + { + DEBUG("status: 0x%x", status); + usleep(1000); + } + + /* mask out bit 0 (reserved) */ + status = status & 0xfe; + + DEBUG("status: 0x%x", status); + + if ((status & 0x80) != 0x80) + { + ERROR("timeout while waiting for WSM to become ready"); + } + else if (status != 0x80) + { + ERROR("status register: 0x%x", status); + if (status & 0x2) + ERROR("Block Lock-Bit Detected, Operation Abort"); + if (status & 0x4) + ERROR("Program suspended"); + if (status & 0x8) + ERROR("Low Programming Voltage Detected, Operation Aborted"); + if (status & 0x10) + ERROR("Program Error / Error in Setting Lock-Bit"); + if (status & 0x20) + ERROR("Error in Block Erasure or Clear Lock-Bits"); + if (status & 0x40) + ERROR("Block Erase Suspended"); + + cfi_intel_clear_status_register(bank); + } + + return status; +} + +int cfi_spansion_wait_status_busy(flash_bank_t *bank, int timeout) +{ + u8 status, oldstatus; + + oldstatus = cfi_get_u8(bank, 0, 0x0); + + do { + status = cfi_get_u8(bank, 0, 0x0); + if ((status ^ oldstatus) & 0x40) { + if (status & 0x20) { + oldstatus = cfi_get_u8(bank, 0, 0x0); + status = cfi_get_u8(bank, 0, 0x0); + if ((status ^ oldstatus) & 0x40) { + ERROR("dq5 timeout, status: 0x%x", status); + return(ERROR_FLASH_OPERATION_FAILED); + } else { + DEBUG("status: 0x%x", status); + return(ERROR_OK); + } + } + } else { + DEBUG("status: 0x%x", status); + return(ERROR_OK); + } + + oldstatus = status; + usleep(1000); + } while (timeout-- > 0); + + ERROR("timeout, status: 0x%x", status); + + return(ERROR_FLASH_BUSY); +} + +int cfi_read_intel_pri_ext(flash_bank_t *bank) +{ + cfi_flash_bank_t *cfi_info = bank->driver_priv; + cfi_intel_pri_ext_t *pri_ext = malloc(sizeof(cfi_intel_pri_ext_t)); + target_t *target = bank->target; + u8 command[8]; + + cfi_info->pri_ext = pri_ext; + + pri_ext->pri[0] = cfi_query_u8(bank, 0, cfi_info->pri_addr + 0); + pri_ext->pri[1] = cfi_query_u8(bank, 0, cfi_info->pri_addr + 1); + pri_ext->pri[2] = cfi_query_u8(bank, 0, cfi_info->pri_addr + 2); + + if ((pri_ext->pri[0] != 'P') || (pri_ext->pri[1] != 'R') || (pri_ext->pri[2] != 'I')) + { + cfi_command(bank, 0xf0, command); + target->type->write_memory(target, flash_address(bank, 0, 0x0), bank->bus_width, 1, command); + cfi_command(bank, 0xff, command); + target->type->write_memory(target, flash_address(bank, 0, 0x0), bank->bus_width, 1, command); + return ERROR_FLASH_BANK_INVALID; + } + + pri_ext->major_version = cfi_query_u8(bank, 0, cfi_info->pri_addr + 3); + pri_ext->minor_version = cfi_query_u8(bank, 0, cfi_info->pri_addr + 4); + + DEBUG("pri: '%c%c%c', version: %c.%c", pri_ext->pri[0], pri_ext->pri[1], pri_ext->pri[2], pri_ext->major_version, pri_ext->minor_version); + + pri_ext->feature_support = cfi_query_u32(bank, 0, cfi_info->pri_addr + 5); + pri_ext->suspend_cmd_support = cfi_query_u8(bank, 0, cfi_info->pri_addr + 9); + pri_ext->blk_status_reg_mask = cfi_query_u16(bank, 0, cfi_info->pri_addr + 0xa); + + DEBUG("feature_support: 0x%x, suspend_cmd_support: 0x%x, blk_status_reg_mask: 0x%x", pri_ext->feature_support, pri_ext->suspend_cmd_support, pri_ext->blk_status_reg_mask); + + pri_ext->vcc_optimal = cfi_query_u8(bank, 0, cfi_info->pri_addr + 0xc); + pri_ext->vpp_optimal = cfi_query_u8(bank, 0, cfi_info->pri_addr + 0xd); + + DEBUG("Vcc opt: %1.1x.%1.1x, Vpp opt: %1.1x.%1.1x", + (pri_ext->vcc_optimal & 0xf0) >> 4, pri_ext->vcc_optimal & 0x0f, + (pri_ext->vpp_optimal & 0xf0) >> 4, pri_ext->vpp_optimal & 0x0f); + + pri_ext->num_protection_fields = cfi_query_u8(bank, 0, cfi_info->pri_addr + 0xe); + if (pri_ext->num_protection_fields != 1) + { + WARNING("expected one protection register field, but found %i", pri_ext->num_protection_fields); + } + + pri_ext->prot_reg_addr = cfi_query_u16(bank, 0, cfi_info->pri_addr + 0xf); + pri_ext->fact_prot_reg_size = cfi_query_u8(bank, 0, cfi_info->pri_addr + 0x11); + pri_ext->user_prot_reg_size = cfi_query_u8(bank, 0, cfi_info->pri_addr + 0x12); + + DEBUG("protection_fields: %i, prot_reg_addr: 0x%x, factory pre-programmed: %i, user programmable: %i", pri_ext->num_protection_fields, pri_ext->prot_reg_addr, 1 << pri_ext->fact_prot_reg_size, 1 << pri_ext->user_prot_reg_size); + + return ERROR_OK; +} + +int cfi_read_spansion_pri_ext(flash_bank_t *bank) +{ + cfi_flash_bank_t *cfi_info = bank->driver_priv; + cfi_spansion_pri_ext_t *pri_ext = malloc(sizeof(cfi_spansion_pri_ext_t)); + target_t *target = bank->target; + u8 command[8]; + + cfi_info->pri_ext = pri_ext; + + pri_ext->pri[0] = cfi_query_u8(bank, 0, cfi_info->pri_addr + 0); + pri_ext->pri[1] = cfi_query_u8(bank, 0, cfi_info->pri_addr + 1); + pri_ext->pri[2] = cfi_query_u8(bank, 0, cfi_info->pri_addr + 2); + + if ((pri_ext->pri[0] != 'P') || (pri_ext->pri[1] != 'R') || (pri_ext->pri[2] != 'I')) + { + cfi_command(bank, 0xf0, command); + target->type->write_memory(target, flash_address(bank, 0, 0x0), bank->bus_width, 1, command); + return ERROR_FLASH_BANK_INVALID; + } + + pri_ext->major_version = cfi_query_u8(bank, 0, cfi_info->pri_addr + 3); + pri_ext->minor_version = cfi_query_u8(bank, 0, cfi_info->pri_addr + 4); + + DEBUG("pri: '%c%c%c', version: %c.%c", pri_ext->pri[0], pri_ext->pri[1], pri_ext->pri[2], pri_ext->major_version, pri_ext->minor_version); + + pri_ext->SiliconRevision = cfi_query_u8(bank, 0, cfi_info->pri_addr + 5); + pri_ext->EraseSuspend = cfi_query_u8(bank, 0, cfi_info->pri_addr + 6); + pri_ext->BlkProt = cfi_query_u8(bank, 0, cfi_info->pri_addr + 7); + pri_ext->TmpBlkUnprotect = cfi_query_u8(bank, 0, cfi_info->pri_addr + 8); + pri_ext->BlkProtUnprot = cfi_query_u8(bank, 0, cfi_info->pri_addr + 9); + pri_ext->SimultaneousOps = cfi_query_u8(bank, 0, cfi_info->pri_addr + 10); + pri_ext->BurstMode = cfi_query_u8(bank, 0, cfi_info->pri_addr + 11); + pri_ext->PageMode = cfi_query_u8(bank, 0, cfi_info->pri_addr + 12); + pri_ext->VppMin = cfi_query_u8(bank, 0, cfi_info->pri_addr + 13); + pri_ext->VppMax = cfi_query_u8(bank, 0, cfi_info->pri_addr + 14); + pri_ext->TopBottom = cfi_query_u8(bank, 0, cfi_info->pri_addr + 15); + + DEBUG("Silicon Revision: 0x%x, Erase Suspend: 0x%x, Block protect: 0x%x", pri_ext->SiliconRevision, + pri_ext->EraseSuspend, pri_ext->BlkProt); + + DEBUG("Temporary Unprotect: 0x%x, Block Protect Scheme: 0x%x, Simultaneous Ops: 0x%x", pri_ext->TmpBlkUnprotect, + pri_ext->BlkProtUnprot, pri_ext->SimultaneousOps); + + DEBUG("Burst Mode: 0x%x, Page Mode: 0x%x, ", pri_ext->BurstMode, pri_ext->PageMode); + + + DEBUG("Vpp min: %2.2d.%1.1d, Vpp max: %2.2d.%1.1x", + (pri_ext->VppMin & 0xf0) >> 4, pri_ext->VppMin & 0x0f, + (pri_ext->VppMax & 0xf0) >> 4, pri_ext->VppMax & 0x0f); + + DEBUG("WP# protection 0x%x", pri_ext->TopBottom); + + /* default values for implementation specific workarounds */ + pri_ext->_unlock1 = cfi_unlock_addresses[CFI_UNLOCK_555_2AA].unlock1; + pri_ext->_unlock2 = cfi_unlock_addresses[CFI_UNLOCK_555_2AA].unlock2; + pri_ext->_reversed_geometry = 0; + + return ERROR_OK; +} + +int cfi_read_atmel_pri_ext(flash_bank_t *bank) +{ + cfi_atmel_pri_ext_t atmel_pri_ext; + cfi_flash_bank_t *cfi_info = bank->driver_priv; + cfi_spansion_pri_ext_t *pri_ext = malloc(sizeof(cfi_spansion_pri_ext_t)); + target_t *target = bank->target; + u8 command[8]; + + /* ATMEL devices use the same CFI primary command set (0x2) as AMD/Spansion, + * but a different primary extended query table. + * We read the atmel table, and prepare a valid AMD/Spansion query table. + */ + + memset(pri_ext, 0, sizeof(cfi_spansion_pri_ext_t)); + + cfi_info->pri_ext = pri_ext; + + atmel_pri_ext.pri[0] = cfi_query_u8(bank, 0, cfi_info->pri_addr + 0); + atmel_pri_ext.pri[1] = cfi_query_u8(bank, 0, cfi_info->pri_addr + 1); + atmel_pri_ext.pri[2] = cfi_query_u8(bank, 0, cfi_info->pri_addr + 2); + + if ((atmel_pri_ext.pri[0] != 'P') || (atmel_pri_ext.pri[1] != 'R') || (atmel_pri_ext.pri[2] != 'I')) + { + cfi_command(bank, 0xf0, command); + target->type->write_memory(target, flash_address(bank, 0, 0x0), bank->bus_width, 1, command); + return ERROR_FLASH_BANK_INVALID; + } + + pri_ext->pri[0] = atmel_pri_ext.pri[0]; + pri_ext->pri[1] = atmel_pri_ext.pri[1]; + pri_ext->pri[2] = atmel_pri_ext.pri[2]; + + atmel_pri_ext.major_version = cfi_query_u8(bank, 0, cfi_info->pri_addr + 3); + atmel_pri_ext.minor_version = cfi_query_u8(bank, 0, cfi_info->pri_addr + 4); + + DEBUG("pri: '%c%c%c', version: %c.%c", atmel_pri_ext.pri[0], atmel_pri_ext.pri[1], atmel_pri_ext.pri[2], atmel_pri_ext.major_version, atmel_pri_ext.minor_version); + + pri_ext->major_version = atmel_pri_ext.major_version; + pri_ext->minor_version = atmel_pri_ext.minor_version; + + atmel_pri_ext.features = cfi_query_u8(bank, 0, cfi_info->pri_addr + 5); + atmel_pri_ext.bottom_boot = cfi_query_u8(bank, 0, cfi_info->pri_addr + 6); + atmel_pri_ext.burst_mode = cfi_query_u8(bank, 0, cfi_info->pri_addr + 7); + atmel_pri_ext.page_mode = cfi_query_u8(bank, 0, cfi_info->pri_addr + 8); + + DEBUG("features: 0x%2.2x, bottom_boot: 0x%2.2x, burst_mode: 0x%2.2x, page_mode: 0x%2.2x", + atmel_pri_ext.features, atmel_pri_ext.bottom_boot, atmel_pri_ext.burst_mode, atmel_pri_ext.page_mode); + + if (atmel_pri_ext.features & 0x02) + pri_ext->EraseSuspend = 2; + + if (atmel_pri_ext.bottom_boot) + pri_ext->TopBottom = 2; + else + pri_ext->TopBottom = 3; + + pri_ext->_unlock1 = cfi_unlock_addresses[CFI_UNLOCK_555_2AA].unlock1; + pri_ext->_unlock2 = cfi_unlock_addresses[CFI_UNLOCK_555_2AA].unlock2; + + return ERROR_OK; +} + +int cfi_read_0002_pri_ext(flash_bank_t *bank) +{ + cfi_flash_bank_t *cfi_info = bank->driver_priv; + + if (cfi_info->manufacturer == CFI_MFR_ATMEL) + { + return cfi_read_atmel_pri_ext(bank); + } + else + { + return cfi_read_spansion_pri_ext(bank); + } +} + +int cfi_spansion_info(struct flash_bank_s *bank, char *buf, int buf_size) +{ + int printed; + cfi_flash_bank_t *cfi_info = bank->driver_priv; + cfi_spansion_pri_ext_t *pri_ext = cfi_info->pri_ext; + + printed = snprintf(buf, buf_size, "\nSpansion primary algorithm extend information:\n"); + buf += printed; + buf_size -= printed; + + printed = snprintf(buf, buf_size, "pri: '%c%c%c', version: %c.%c\n", pri_ext->pri[0], + pri_ext->pri[1], pri_ext->pri[2], + pri_ext->major_version, pri_ext->minor_version); + buf += printed; + buf_size -= printed; + + printed = snprintf(buf, buf_size, "Silicon Rev.: 0x%x, Address Sensitive unlock: 0x%x\n", + (pri_ext->SiliconRevision) >> 2, + (pri_ext->SiliconRevision) & 0x03); + buf += printed; + buf_size -= printed; + + printed = snprintf(buf, buf_size, "Erase Suspend: 0x%x, Sector Protect: 0x%x\n", + pri_ext->EraseSuspend, + pri_ext->BlkProt); + buf += printed; + buf_size -= printed; + + printed = snprintf(buf, buf_size, "VppMin: %2.2d.%1.1x, VppMax: %2.2d.%1.1x\n", + (pri_ext->VppMin & 0xf0) >> 4, pri_ext->VppMin & 0x0f, + (pri_ext->VppMax & 0xf0) >> 4, pri_ext->VppMax & 0x0f); + + return ERROR_OK; +} + +int cfi_intel_info(struct flash_bank_s *bank, char *buf, int buf_size) +{ + int printed; + cfi_flash_bank_t *cfi_info = bank->driver_priv; + cfi_intel_pri_ext_t *pri_ext = cfi_info->pri_ext; + + printed = snprintf(buf, buf_size, "\nintel primary algorithm extend information:\n"); + buf += printed; + buf_size -= printed; + + printed = snprintf(buf, buf_size, "pri: '%c%c%c', version: %c.%c\n", pri_ext->pri[0], pri_ext->pri[1], pri_ext->pri[2], pri_ext->major_version, pri_ext->minor_version); + buf += printed; + buf_size -= printed; + + printed = snprintf(buf, buf_size, "feature_support: 0x%x, suspend_cmd_support: 0x%x, blk_status_reg_mask: 0x%x\n", pri_ext->feature_support, pri_ext->suspend_cmd_support, pri_ext->blk_status_reg_mask); + buf += printed; + buf_size -= printed; + + printed = snprintf(buf, buf_size, "Vcc opt: %1.1x.%1.1x, Vpp opt: %1.1x.%1.1x\n", + (pri_ext->vcc_optimal & 0xf0) >> 4, pri_ext->vcc_optimal & 0x0f, + (pri_ext->vpp_optimal & 0xf0) >> 4, pri_ext->vpp_optimal & 0x0f); + buf += printed; + buf_size -= printed; + + printed = snprintf(buf, buf_size, "protection_fields: %i, prot_reg_addr: 0x%x, factory pre-programmed: %i, user programmable: %i\n", pri_ext->num_protection_fields, pri_ext->prot_reg_addr, 1 << pri_ext->fact_prot_reg_size, 1 << pri_ext->user_prot_reg_size); + + return ERROR_OK; +} + +int cfi_register_commands(struct command_context_s *cmd_ctx) +{ + /*command_t *cfi_cmd = */ + register_command(cmd_ctx, NULL, "cfi", NULL, COMMAND_ANY, "flash bank cfi [jedec_probe/x16_as_x8]"); + /* + register_command(cmd_ctx, cfi_cmd, "part_id", cfi_handle_part_id_command, COMMAND_EXEC, + "print part id of cfi flash bank "); + */ + return ERROR_OK; +} + +/* flash_bank cfi [options] + */ +int cfi_flash_bank_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc, struct flash_bank_s *bank) +{ + cfi_flash_bank_t *cfi_info; + int i; + + if (argc < 6) + { + WARNING("incomplete flash_bank cfi configuration"); + return ERROR_FLASH_BANK_INVALID; + } + + if ((strtoul(args[4], NULL, 0) > CFI_MAX_CHIP_WIDTH) + || (strtoul(args[3], NULL, 0) > CFI_MAX_BUS_WIDTH)) + { + ERROR("chip and bus width have to specified in bytes"); + return ERROR_FLASH_BANK_INVALID; + } + + cfi_info = malloc(sizeof(cfi_flash_bank_t)); + cfi_info->probed = 0; + bank->driver_priv = cfi_info; + + cfi_info->write_algorithm = NULL; + cfi_info->erase_check_algorithm = NULL; + + cfi_info->x16_as_x8 = 0; + cfi_info->jedec_probe = 0; + cfi_info->not_cfi = 0; + + for (i = 6; i < argc; i++) + { + if (strcmp(args[i], "x16_as_x8") == 0) + { + cfi_info->x16_as_x8 = 1; + } + else if (strcmp(args[i], "jedec_probe") == 0) + { + cfi_info->jedec_probe = 1; + } + } + + cfi_info->write_algorithm = NULL; + + /* bank wasn't probed yet */ + cfi_info->qry[0] = -1; + + return ERROR_OK; +} + +int cfi_intel_erase(struct flash_bank_s *bank, int first, int last) +{ + cfi_flash_bank_t *cfi_info = bank->driver_priv; + target_t *target = bank->target; + u8 command[8]; + int i; + + cfi_intel_clear_status_register(bank); + + for (i = first; i <= last; i++) + { + cfi_command(bank, 0x20, command); + target->type->write_memory(target, flash_address(bank, i, 0x0), bank->bus_width, 1, command); + + cfi_command(bank, 0xd0, command); + target->type->write_memory(target, flash_address(bank, i, 0x0), bank->bus_width, 1, command); + + if (cfi_intel_wait_status_busy(bank, 1000 * (1 << cfi_info->block_erase_timeout_typ)) == 0x80) + bank->sectors[i].is_erased = 1; + else + { + cfi_command(bank, 0xff, command); + target->type->write_memory(target, flash_address(bank, 0, 0x0), bank->bus_width, 1, command); + + ERROR("couldn't erase block %i of flash bank at base 0x%x", i, bank->base); + return ERROR_FLASH_OPERATION_FAILED; + } + } + + cfi_command(bank, 0xff, command); + target->type->write_memory(target, flash_address(bank, 0, 0x0), bank->bus_width, 1, command); + + return ERROR_OK; +} + +int cfi_spansion_erase(struct flash_bank_s *bank, int first, int last) +{ + cfi_flash_bank_t *cfi_info = bank->driver_priv; + cfi_spansion_pri_ext_t *pri_ext = cfi_info->pri_ext; + target_t *target = bank->target; + u8 command[8]; + int i; + + for (i = first; i <= last; i++) + { + cfi_command(bank, 0xaa, command); + target->type->write_memory(target, flash_address(bank, 0, pri_ext->_unlock1), bank->bus_width, 1, command); + + cfi_command(bank, 0x55, command); + target->type->write_memory(target, flash_address(bank, 0, pri_ext->_unlock2), bank->bus_width, 1, command); + + cfi_command(bank, 0x80, command); + target->type->write_memory(target, flash_address(bank, 0, pri_ext->_unlock1), bank->bus_width, 1, command); + + cfi_command(bank, 0xaa, command); + target->type->write_memory(target, flash_address(bank, 0, pri_ext->_unlock1), bank->bus_width, 1, command); + + cfi_command(bank, 0x55, command); + target->type->write_memory(target, flash_address(bank, 0, pri_ext->_unlock2), bank->bus_width, 1, command); + + cfi_command(bank, 0x30, command); + target->type->write_memory(target, flash_address(bank, i, 0x0), bank->bus_width, 1, command); + + if (cfi_spansion_wait_status_busy(bank, 1000 * (1 << cfi_info->block_erase_timeout_typ)) == ERROR_OK) + bank->sectors[i].is_erased = 1; + else + { + cfi_command(bank, 0xf0, command); + target->type->write_memory(target, flash_address(bank, 0, 0x0), bank->bus_width, 1, command); + + ERROR("couldn't erase block %i of flash bank at base 0x%x", i, bank->base); + return ERROR_FLASH_OPERATION_FAILED; + } + } + + cfi_command(bank, 0xf0, command); + target->type->write_memory(target, flash_address(bank, 0, 0x0), bank->bus_width, 1, command); + + return ERROR_OK; +} + +int cfi_erase(struct flash_bank_s *bank, int first, int last) +{ + cfi_flash_bank_t *cfi_info = bank->driver_priv; + + if (bank->target->state != TARGET_HALTED) + { + return ERROR_TARGET_NOT_HALTED; + } + + if ((first < 0) || (last < first) || (last >= bank->num_sectors)) + { + return ERROR_FLASH_SECTOR_INVALID; + } + + if (cfi_info->qry[0] != 'Q') + return ERROR_FLASH_BANK_NOT_PROBED; + + switch(cfi_info->pri_id) + { + case 1: + case 3: + return cfi_intel_erase(bank, first, last); + break; + case 2: + return cfi_spansion_erase(bank, first, last); + break; + default: + ERROR("cfi primary command set %i unsupported", cfi_info->pri_id); + break; + } + + return ERROR_OK; +} + +int cfi_intel_protect(struct flash_bank_s *bank, int set, int first, int last) +{ + cfi_flash_bank_t *cfi_info = bank->driver_priv; + cfi_intel_pri_ext_t *pri_ext = cfi_info->pri_ext; + target_t *target = bank->target; + u8 command[8]; + int retry = 0; + int i; + + /* if the device supports neither legacy lock/unlock (bit 3) nor + * instant individual block locking (bit 5). + */ + if (!(pri_ext->feature_support & 0x28)) + return ERROR_FLASH_OPERATION_FAILED; + + cfi_intel_clear_status_register(bank); + + for (i = first; i <= last; i++) + { + cfi_command(bank, 0x60, command); + DEBUG("address: 0x%4.4x, command: 0x%4.4x", flash_address(bank, i, 0x0), target_buffer_get_u32(target, command)); + target->type->write_memory(target, flash_address(bank, i, 0x0), bank->bus_width, 1, command); + if (set) + { + cfi_command(bank, 0x01, command); + DEBUG("address: 0x%4.4x, command: 0x%4.4x", flash_address(bank, i, 0x0), target_buffer_get_u32(target, command)); + target->type->write_memory(target, flash_address(bank, i, 0x0), bank->bus_width, 1, command); + bank->sectors[i].is_protected = 1; + } + else + { + cfi_command(bank, 0xd0, command); + DEBUG("address: 0x%4.4x, command: 0x%4.4x", flash_address(bank, i, 0x0), target_buffer_get_u32(target, command)); + target->type->write_memory(target, flash_address(bank, i, 0x0), bank->bus_width, 1, command); + bank->sectors[i].is_protected = 0; + } + + /* instant individual block locking doesn't require reading of the status register */ + if (!(pri_ext->feature_support & 0x20)) + { + /* Clear lock bits operation may take up to 1.4s */ + cfi_intel_wait_status_busy(bank, 1400); + } + else + { + u8 block_status; + /* read block lock bit, to verify status */ + cfi_command(bank, 0x90, command); + target->type->write_memory(target, flash_address(bank, 0, 0x55), bank->bus_width, 1, command); + block_status = cfi_get_u8(bank, i, 0x2); + + if ((block_status & 0x1) != set) + { + ERROR("couldn't change block lock status (set = %i, block_status = 0x%2.2x)", set, block_status); + cfi_command(bank, 0x70, command); + target->type->write_memory(target, flash_address(bank, 0, 0x55), bank->bus_width, 1, command); + cfi_intel_wait_status_busy(bank, 10); + + if (retry > 10) + return ERROR_FLASH_OPERATION_FAILED; + else + { + i--; + retry++; + } + } + } + } + + /* if the device doesn't support individual block lock bits set/clear, + * all blocks have been unlocked in parallel, so we set those that should be protected + */ + if ((!set) && (!(pri_ext->feature_support & 0x20))) + { + for (i = 0; i < bank->num_sectors; i++) + { + if (bank->sectors[i].is_protected == 1) + { + cfi_intel_clear_status_register(bank); + + cfi_command(bank, 0x60, command); + target->type->write_memory(target, flash_address(bank, i, 0x0), bank->bus_width, 1, command); + + cfi_command(bank, 0x01, command); + target->type->write_memory(target, flash_address(bank, i, 0x0), bank->bus_width, 1, command); + + cfi_intel_wait_status_busy(bank, 100); + } + } + } + + cfi_command(bank, 0xff, command); + target->type->write_memory(target, flash_address(bank, 0, 0x0), bank->bus_width, 1, command); + + return ERROR_OK; +} + +int cfi_protect(struct flash_bank_s *bank, int set, int first, int last) +{ + cfi_flash_bank_t *cfi_info = bank->driver_priv; + + if (bank->target->state != TARGET_HALTED) + { + return ERROR_TARGET_NOT_HALTED; + } + + if ((first < 0) || (last < first) || (last >= bank->num_sectors)) + { + return ERROR_FLASH_SECTOR_INVALID; + } + + if (cfi_info->qry[0] != 'Q') + return ERROR_FLASH_BANK_NOT_PROBED; + + switch(cfi_info->pri_id) + { + case 1: + case 3: + cfi_intel_protect(bank, set, first, last); + break; + default: + ERROR("cfi primary command set %i unsupported", cfi_info->pri_id); + break; + } + + return ERROR_OK; +} + +/* FIXME Replace this by a simple memcpy() - still unsure about sideeffects */ +static void cfi_add_byte(struct flash_bank_s *bank, u8 *word, u8 byte) +{ + //target_t *target = bank->target; + + int i; + + // NOTE: + // The data to flash must not be changed in endian! We write a bytestrem in + // target byte order already. Only the control and status byte lane of the flash + // WSM is interpreted by the CPU in different ways, when read a u16 or u32 + // word (data seems to be in the upper or lower byte lane for u16 accesses). + + //if (target->endianness == TARGET_LITTLE_ENDIAN) + //{ + /* shift bytes */ + for (i = 0; i < bank->bus_width - 1; i++) + word[i] = word[i + 1]; + word[bank->bus_width - 1] = byte; + //} + //else + //{ + // /* shift bytes */ + // for (i = bank->bus_width - 1; i > 0; i--) + // word[i] = word[i - 1]; + // word[0] = byte; + //} +} + +/* Convert code image to target endian */ +/* FIXME create general block conversion fcts in target.c?) */ static +void cfi_fix_code_endian(target_t *target, u32 *dest, const u32 *src, u32 count) +{ + u32 i; + for (i=0; i< count; i++) + { + target_buffer_set_u32(target, (u8*)dest, *src); + dest++; + src++; + } +} + +int cfi_intel_write_block(struct flash_bank_s *bank, u8 *buffer, u32 address, u32 count) +{ + cfi_flash_bank_t *cfi_info = bank->driver_priv; + target_t *target = bank->target; + reg_param_t reg_params[7]; + armv4_5_algorithm_t armv4_5_info; + working_area_t *source; + u32 buffer_size = 32768; + u8 write_command_buf[CFI_MAX_BUS_WIDTH]; + u8 busy_pattern_buf[CFI_MAX_BUS_WIDTH]; + u8 error_pattern_buf[CFI_MAX_BUS_WIDTH]; + u32 write_command_val, busy_pattern_val, error_pattern_val; + + /* algorithm register usage: + * r0: source address (in RAM) + * r1: target address (in Flash) + * r2: count + * r3: flash write command + * r4: status byte (returned to host) + * r5: busy test pattern + * r6: error test pattern + */ + + static const u32 word_32_code[] = { + 0xe4904004, /* loop: ldr r4, [r0], #4 */ + 0xe5813000, /* str r3, [r1] */ + 0xe5814000, /* str r4, [r1] */ + 0xe5914000, /* busy: ldr r4, [r1] */ + 0xe0047005, /* and r7, r4, r5 */ + 0xe1570005, /* cmp r7, r5 */ + 0x1afffffb, /* bne busy */ + 0xe1140006, /* tst r4, r6 */ + 0x1a000003, /* bne done */ + 0xe2522001, /* subs r2, r2, #1 */ + 0x0a000001, /* beq done */ + 0xe2811004, /* add r1, r1 #4 */ + 0xeafffff2, /* b loop */ + 0xeafffffe /* done: b -2 */ + }; + + static const u32 word_16_code[] = { + 0xe0d040b2, /* loop: ldrh r4, [r0], #2 */ + 0xe1c130b0, /* strh r3, [r1] */ + 0xe1c140b0, /* strh r4, [r1] */ + 0xe1d140b0, /* busy ldrh r4, [r1] */ + 0xe0047005, /* and r7, r4, r5 */ + 0xe1570005, /* cmp r7, r5 */ + 0x1afffffb, /* bne busy */ + 0xe1140006, /* tst r4, r6 */ + 0x1a000003, /* bne done */ + 0xe2522001, /* subs r2, r2, #1 */ + 0x0a000001, /* beq done */ + 0xe2811002, /* add r1, r1 #2 */ + 0xeafffff2, /* b loop */ + 0xeafffffe /* done: b -2 */ + }; + + static const u32 word_8_code[] = { + 0xe4d04001, /* loop: ldrb r4, [r0], #1 */ + 0xe5c13000, /* strb r3, [r1] */ + 0xe5c14000, /* strb r4, [r1] */ + 0xe5d14000, /* busy ldrb r4, [r1] */ + 0xe0047005, /* and r7, r4, r5 */ + 0xe1570005, /* cmp r7, r5 */ + 0x1afffffb, /* bne busy */ + 0xe1140006, /* tst r4, r6 */ + 0x1a000003, /* bne done */ + 0xe2522001, /* subs r2, r2, #1 */ + 0x0a000001, /* beq done */ + 0xe2811001, /* add r1, r1 #1 */ + 0xeafffff2, /* b loop */ + 0xeafffffe /* done: b -2 */ + }; + u32 target_code[CFI_MAX_INTEL_CODESIZE]; + const u32 *target_code_src; + int target_code_size; + int retval = ERROR_OK; + + + cfi_intel_clear_status_register(bank); + + armv4_5_info.common_magic = ARMV4_5_COMMON_MAGIC; + armv4_5_info.core_mode = ARMV4_5_MODE_SVC; + armv4_5_info.core_state = ARMV4_5_STATE_ARM; + + /* If we are setting up the write_algorith, we need target_code_src */ + /* if not we only need target_code_size. */ + /* */ + /* However, we don't want to create multiple code paths, so we */ + /* do the unecessary evaluation of target_code_src, which the */ + /* compiler will probably nicely optimize away if not needed */ + + /* prepare algorithm code for target endian */ + switch (bank->bus_width) + { + case 1 : + target_code_src = word_8_code; + target_code_size = sizeof(word_8_code); + break; + case 2 : + target_code_src = word_16_code; + target_code_size = sizeof(word_16_code); + break; + case 4 : + target_code_src = word_32_code; + target_code_size = sizeof(word_32_code); + break; + default: + ERROR("Unsupported bank buswidth %d, can't do block memory writes", bank->bus_width); + return ERROR_TARGET_RESOURCE_NOT_AVAILABLE; + } + + /* flash write code */ + if (!cfi_info->write_algorithm) + { + if ( target_code_size > sizeof(target_code) ) + { + WARNING("Internal error - target code buffer to small. Increase CFI_MAX_INTEL_CODESIZE and recompile."); + return ERROR_TARGET_RESOURCE_NOT_AVAILABLE; + } + cfi_fix_code_endian(target, target_code, target_code_src, target_code_size); + + /* Get memory for block write handler */ + retval = target_alloc_working_area(target, target_code_size, &cfi_info->write_algorithm); + if (retval != ERROR_OK) + { + WARNING("No working area available, can't do block memory writes"); + return ERROR_TARGET_RESOURCE_NOT_AVAILABLE; + }; + + /* write algorithm code to working area */ + retval = target_write_buffer(target, cfi_info->write_algorithm->address, target_code_size, (u8*)target_code); + if (retval != ERROR_OK) + { + ERROR("Unable to write block write code to target"); + goto cleanup; + } + } + + /* Get a workspace buffer for the data to flash starting with 32k size. + Half size until buffer would be smaller 256 Bytem then fail back */ + /* FIXME Why 256 bytes, why not 32 bytes (smallest flash write page */ + while (target_alloc_working_area(target, buffer_size, &source) != ERROR_OK) + { + buffer_size /= 2; + if (buffer_size <= 256) + { + WARNING("no large enough working area available, can't do block memory writes"); + retval = ERROR_TARGET_RESOURCE_NOT_AVAILABLE; + goto cleanup; + } + }; + + /* setup algo registers */ + init_reg_param(®_params[0], "r0", 32, PARAM_OUT); + init_reg_param(®_params[1], "r1", 32, PARAM_OUT); + init_reg_param(®_params[2], "r2", 32, PARAM_OUT); + init_reg_param(®_params[3], "r3", 32, PARAM_OUT); + init_reg_param(®_params[4], "r4", 32, PARAM_IN); + init_reg_param(®_params[5], "r5", 32, PARAM_OUT); + init_reg_param(®_params[6], "r6", 32, PARAM_OUT); + + /* prepare command and status register patterns */ + cfi_command(bank, 0x40, write_command_buf); + cfi_command(bank, 0x80, busy_pattern_buf); + cfi_command(bank, 0x7e, error_pattern_buf); + + switch (bank->bus_width) + { + case 1 : + write_command_val = write_command_buf[0]; + busy_pattern_val = busy_pattern_buf[0]; + error_pattern_val = error_pattern_buf[0]; + break; + case 2 : + write_command_val = target_buffer_get_u16(target, write_command_buf); + busy_pattern_val = target_buffer_get_u16(target, busy_pattern_buf); + error_pattern_val = target_buffer_get_u16(target, error_pattern_buf); + break; + case 4 : + write_command_val = target_buffer_get_u32(target, write_command_buf); + busy_pattern_val = target_buffer_get_u32(target, busy_pattern_buf); + error_pattern_val = target_buffer_get_u32(target, error_pattern_buf); + break; + default : + ERROR("Unsupported bank buswidth %d, can't do block memory writes", bank->bus_width); + retval = ERROR_TARGET_RESOURCE_NOT_AVAILABLE; + goto cleanup; + } + + INFO("Using target buffer at 0x%08x and of size 0x%04x", source->address, buffer_size ); + + /* Programming main loop */ + while (count > 0) + { + u32 thisrun_count = (count > buffer_size) ? buffer_size : count; + u32 wsm_error; + + target_write_buffer(target, source->address, thisrun_count, buffer); + + buf_set_u32(reg_params[0].value, 0, 32, source->address); + buf_set_u32(reg_params[1].value, 0, 32, address); + buf_set_u32(reg_params[2].value, 0, 32, thisrun_count / bank->bus_width); + + buf_set_u32(reg_params[3].value, 0, 32, write_command_val); + buf_set_u32(reg_params[5].value, 0, 32, busy_pattern_val); + buf_set_u32(reg_params[6].value, 0, 32, error_pattern_val); + + INFO("Write 0x%04x bytes to flash at 0x%08x", thisrun_count, address ); + + /* Execute algorithm, assume breakpoint for last instruction */ + retval = target->type->run_algorithm(target, 0, NULL, 7, reg_params, + cfi_info->write_algorithm->address, + cfi_info->write_algorithm->address + target_code_size - sizeof(u32), + 10000, /* 10s should be enough for max. 32k of data */ + &armv4_5_info); + + /* On failure try a fall back to direct word writes */ + if (retval != ERROR_OK) + { + cfi_intel_clear_status_register(bank); + ERROR("Execution of flash algorythm failed. Can't fall back. Please report."); + retval = ERROR_FLASH_OPERATION_FAILED; + //retval = ERROR_TARGET_RESOURCE_NOT_AVAILABLE; + // FIXME To allow fall back or recovery, we must save the actual status + // somewhere, so that a higher level code can start recovery. + goto cleanup; + } + + /* Check return value from algo code */ + wsm_error = buf_get_u32(reg_params[4].value, 0, 32) & error_pattern_val; + if (wsm_error) + { + /* read status register (outputs debug inforation) */ + cfi_intel_wait_status_busy(bank, 100); + cfi_intel_clear_status_register(bank); + retval = ERROR_FLASH_OPERATION_FAILED; + goto cleanup; + } + + buffer += thisrun_count; + address += thisrun_count; + count -= thisrun_count; + } + + /* free up resources */ +cleanup: + if (source) + target_free_working_area(target, source); + + if (cfi_info->write_algorithm) + { + target_free_working_area(target, cfi_info->write_algorithm); + cfi_info->write_algorithm = NULL; + } + + destroy_reg_param(®_params[0]); + destroy_reg_param(®_params[1]); + destroy_reg_param(®_params[2]); + destroy_reg_param(®_params[3]); + destroy_reg_param(®_params[4]); + destroy_reg_param(®_params[5]); + destroy_reg_param(®_params[6]); + + return retval; +} + +int cfi_spansion_write_block(struct flash_bank_s *bank, u8 *buffer, u32 address, u32 count) +{ + cfi_flash_bank_t *cfi_info = bank->driver_priv; + cfi_spansion_pri_ext_t *pri_ext = cfi_info->pri_ext; + target_t *target = bank->target; + reg_param_t reg_params[10]; + armv4_5_algorithm_t armv4_5_info; + working_area_t *source; + u32 buffer_size = 32768; + u8 write_command[CFI_MAX_BUS_WIDTH]; + u32 status; + int i; + int retval; + int exit_code = ERROR_OK; + + /* input parameters - */ + /* R0 = source address */ + /* R1 = destination address */ + /* R2 = number of writes */ + /* R3 = flash write command */ + /* R4 = constant to mask DQ7 bits (also used for Dq5 with shift) */ + /* output parameters - */ + /* R5 = 0x80 ok 0x00 bad */ + /* temp registers - */ + /* R6 = value read from flash to test status */ + /* R7 = holding register */ + /* unlock registers - */ + /* R8 = unlock1_addr */ + /* R9 = unlock1_cmd */ + /* R10 = unlock2_addr */ + /* R11 = unlock2_cmd */ + + u32 word_32_code[] = { + /* 00008100 : */ + 0xe4905004, /* ldr r5, [r0], #4 */ + 0xe5889000, /* str r9, [r8] */ + 0xe58ab000, /* str r11, [r10] */ + 0xe5883000, /* str r3, [r8] */ + 0xe5815000, /* str r5, [r1] */ + 0xe1a00000, /* nop */ + /* */ + /* 00008110 : */ + 0xe5916000, /* ldr r6, [r1] */ + 0xe0257006, /* eor r7, r5, r6 */ + 0xe0147007, /* ands r7, r4, r7 */ + 0x0a000007, /* beq 8140 ; b if DQ7 == Data7 */ + 0xe0166124, /* ands r6, r6, r4, lsr #2 */ + 0x0afffff9, /* beq 8110 ; b if DQ5 low */ + 0xe5916000, /* ldr r6, [r1] */ + 0xe0257006, /* eor r7, r5, r6 */ + 0xe0147007, /* ands r7, r4, r7 */ + 0x0a000001, /* beq 8140 ; b if DQ7 == Data7 */ + 0xe3a05000, /* mov r5, #0 ; 0x0 - return 0x00, error */ + 0x1a000004, /* bne 8154 */ + /* */ + /* 00008140 : */ + 0xe2522001, /* subs r2, r2, #1 ; 0x1 */ + 0x03a05080, /* moveq r5, #128 ; 0x80 */ + 0x0a000001, /* beq 8154 */ + 0xe2811004, /* add r1, r1, #4 ; 0x4 */ + 0xeaffffe8, /* b 8100 */ + /* */ + /* 00008154 : */ + 0xeafffffe /* b 8154 */ + }; + + u32 word_16_code[] = { + /* 00008158 : */ + 0xe0d050b2, /* ldrh r5, [r0], #2 */ + 0xe1c890b0, /* strh r9, [r8] */ + 0xe1cab0b0, /* strh r11, [r10] */ + 0xe1c830b0, /* strh r3, [r8] */ + 0xe1c150b0, /* strh r5, [r1] */ + 0xe1a00000, /* nop (mov r0,r0) */ + /* */ + /* 00008168 : */ + 0xe1d160b0, /* ldrh r6, [r1] */ + 0xe0257006, /* eor r7, r5, r6 */ + 0xe0147007, /* ands r7, r4, r7 */ + 0x0a000007, /* beq 8198 */ + 0xe0166124, /* ands r6, r6, r4, lsr #2 */ + 0x0afffff9, /* beq 8168 */ + 0xe1d160b0, /* ldrh r6, [r1] */ + 0xe0257006, /* eor r7, r5, r6 */ + 0xe0147007, /* ands r7, r4, r7 */ + 0x0a000001, /* beq 8198 */ + 0xe3a05000, /* mov r5, #0 ; 0x0 */ + 0x1a000004, /* bne 81ac */ + /* */ + /* 00008198 : */ + 0xe2522001, /* subs r2, r2, #1 ; 0x1 */ + 0x03a05080, /* moveq r5, #128 ; 0x80 */ + 0x0a000001, /* beq 81ac */ + 0xe2811002, /* add r1, r1, #2 ; 0x2 */ + 0xeaffffe8, /* b 8158 */ + /* */ + /* 000081ac : */ + 0xeafffffe /* b 81ac */ + }; + + u32 word_8_code[] = { + /* 000081b0 : */ + 0xe4d05001, /* ldrb r5, [r0], #1 */ + 0xe5c89000, /* strb r9, [r8] */ + 0xe5cab000, /* strb r11, [r10] */ + 0xe5c83000, /* strb r3, [r8] */ + 0xe5c15000, /* strb r5, [r1] */ + 0xe1a00000, /* nop (mov r0,r0) */ + /* */ + /* 000081c0 : */ + 0xe5d16000, /* ldrb r6, [r1] */ + 0xe0257006, /* eor r7, r5, r6 */ + 0xe0147007, /* ands r7, r4, r7 */ + 0x0a000007, /* beq 81f0 */ + 0xe0166124, /* ands r6, r6, r4, lsr #2 */ + 0x0afffff9, /* beq 81c0 */ + 0xe5d16000, /* ldrb r6, [r1] */ + 0xe0257006, /* eor r7, r5, r6 */ + 0xe0147007, /* ands r7, r4, r7 */ + 0x0a000001, /* beq 81f0 */ + 0xe3a05000, /* mov r5, #0 ; 0x0 */ + 0x1a000004, /* bne 8204 */ + /* */ + /* 000081f0 : */ + 0xe2522001, /* subs r2, r2, #1 ; 0x1 */ + 0x03a05080, /* moveq r5, #128 ; 0x80 */ + 0x0a000001, /* beq 8204 */ + 0xe2811001, /* add r1, r1, #1 ; 0x1 */ + 0xeaffffe8, /* b 81b0 */ + /* */ + /* 00008204 : */ + 0xeafffffe /* b 8204 */ + }; + + armv4_5_info.common_magic = ARMV4_5_COMMON_MAGIC; + armv4_5_info.core_mode = ARMV4_5_MODE_SVC; + armv4_5_info.core_state = ARMV4_5_STATE_ARM; + + /* flash write code */ + if (!cfi_info->write_algorithm) + { + u8 *code_p; + + /* convert bus-width dependent algorithm code to correct endiannes */ + if (bank->bus_width == 1) + { + code_p = malloc(24 * 4); + + for (i = 0; i < 24; i++) + target_buffer_set_u32(target, code_p + (i*4), word_8_code[i]); + } + else if (bank->bus_width == 2) + { + code_p = malloc(24 * 4); + + for (i = 0; i < 24; i++) + target_buffer_set_u32(target, code_p + (i*4), word_16_code[i]); + } + else if (bank->bus_width == 4) + { + code_p = malloc(24 * 4); + + for (i = 0; i < 24; i++) + target_buffer_set_u32(target, code_p + (i*4), word_32_code[i]); + } + else + { + return ERROR_FLASH_OPERATION_FAILED; + } + + /* allocate working area */ + retval=target_alloc_working_area(target, 24 * 4, + &cfi_info->write_algorithm); + if (retval != ERROR_OK) + { + return retval; + } + + /* write algorithm code to working area */ + target_write_buffer(target, cfi_info->write_algorithm->address, 24 * 4, code_p); + + free(code_p); + } + + while (target_alloc_working_area(target, buffer_size, &source) != ERROR_OK) + { + buffer_size /= 2; + if (buffer_size <= 256) + { + /* if we already allocated the writing code, but failed to get a buffer, free the algorithm */ + if (cfi_info->write_algorithm) + target_free_working_area(target, cfi_info->write_algorithm); + + WARNING("not enough working area available, can't do block memory writes"); + return ERROR_TARGET_RESOURCE_NOT_AVAILABLE; + } + }; + + init_reg_param(®_params[0], "r0", 32, PARAM_OUT); + init_reg_param(®_params[1], "r1", 32, PARAM_OUT); + init_reg_param(®_params[2], "r2", 32, PARAM_OUT); + init_reg_param(®_params[3], "r3", 32, PARAM_OUT); + init_reg_param(®_params[4], "r4", 32, PARAM_OUT); + init_reg_param(®_params[5], "r5", 32, PARAM_IN); + init_reg_param(®_params[6], "r8", 32, PARAM_OUT); + init_reg_param(®_params[7], "r9", 32, PARAM_OUT); + init_reg_param(®_params[8], "r10", 32, PARAM_OUT); + init_reg_param(®_params[9], "r11", 32, PARAM_OUT); + + while (count > 0) + { + u32 thisrun_count = (count > buffer_size) ? buffer_size : count; + + target_write_buffer(target, source->address, thisrun_count, buffer); + + buf_set_u32(reg_params[0].value, 0, 32, source->address); + buf_set_u32(reg_params[1].value, 0, 32, address); + buf_set_u32(reg_params[2].value, 0, 32, thisrun_count / bank->bus_width); + cfi_command(bank, 0xA0, write_command); + buf_set_u32(reg_params[3].value, 0, 32, buf_get_u32(write_command, 0, 32)); + cfi_command(bank, 0x80, write_command); + buf_set_u32(reg_params[4].value, 0, 32, buf_get_u32(write_command, 0, 32)); + buf_set_u32(reg_params[6].value, 0, 32, flash_address(bank, 0, pri_ext->_unlock1)); + buf_set_u32(reg_params[7].value, 0, 32, 0xaa); + buf_set_u32(reg_params[8].value, 0, 32, flash_address(bank, 0, pri_ext->_unlock2)); + buf_set_u32(reg_params[9].value, 0, 32, 0x55); + + retval = target->type->run_algorithm(target, 0, NULL, 10, reg_params, + cfi_info->write_algorithm->address, + cfi_info->write_algorithm->address + ((24 * 4) - 4), + 10000, &armv4_5_info); + + status = buf_get_u32(reg_params[5].value, 0, 32); + + if ((retval != ERROR_OK) || status != 0x80) + { + DEBUG("status: 0x%x", status); + exit_code = ERROR_FLASH_OPERATION_FAILED; + break; + } + + buffer += thisrun_count; + address += thisrun_count; + count -= thisrun_count; + } + + target_free_working_area(target, source); + + destroy_reg_param(®_params[0]); + destroy_reg_param(®_params[1]); + destroy_reg_param(®_params[2]); + destroy_reg_param(®_params[3]); + destroy_reg_param(®_params[4]); + destroy_reg_param(®_params[5]); + destroy_reg_param(®_params[6]); + destroy_reg_param(®_params[7]); + destroy_reg_param(®_params[8]); + destroy_reg_param(®_params[9]); + + return exit_code; +} + +int cfi_intel_write_word(struct flash_bank_s *bank, u8 *word, u32 address) +{ + cfi_flash_bank_t *cfi_info = bank->driver_priv; + target_t *target = bank->target; + u8 command[8]; + + cfi_intel_clear_status_register(bank); + cfi_command(bank, 0x40, command); + target->type->write_memory(target, address, bank->bus_width, 1, command); + + target->type->write_memory(target, address, bank->bus_width, 1, word); + + if (cfi_intel_wait_status_busy(bank, 1000 * (1 << cfi_info->word_write_timeout_max)) != 0x80) + { + cfi_command(bank, 0xff, command); + target->type->write_memory(target, flash_address(bank, 0, 0x0), bank->bus_width, 1, command); + + ERROR("couldn't write word at base 0x%x, address %x", bank->base, address); + return ERROR_FLASH_OPERATION_FAILED; + } + + return ERROR_OK; +} + +int cfi_intel_write_words(struct flash_bank_s *bank, u8 *word, u32 wordcount, u32 address) +{ + cfi_flash_bank_t *cfi_info = bank->driver_priv; + target_t *target = bank->target; + u8 command[8]; + + /* Calculate buffer size and boundary mask */ + u32 buffersize = 1UL << cfi_info->max_buf_write_size; + u32 buffermask = buffersize-1; + u32 bufferwsize; + + /* Check for valid range */ + if (address & buffermask) + { + ERROR("Write address at base 0x%x, address %x not aligned to 2^%d boundary", bank->base, address, cfi_info->max_buf_write_size); + return ERROR_FLASH_OPERATION_FAILED; + } + switch(bank->chip_width) + { + case 4 : bufferwsize = buffersize / 4; break; + case 2 : bufferwsize = buffersize / 2; break; + case 1 : bufferwsize = buffersize; break; + default: + ERROR("Unsupported chip width %d", bank->chip_width); + return ERROR_FLASH_OPERATION_FAILED; + } + + /* Check for valid size */ + if (wordcount > bufferwsize) + { + ERROR("Number of data words %d exceeds available buffersize %d", wordcount, buffersize); + return ERROR_FLASH_OPERATION_FAILED; + } + + /* Write to flash buffer */ + cfi_intel_clear_status_register(bank); + + /* Initiate buffer operation _*/ + cfi_command(bank, 0xE8, command); + target->type->write_memory(target, address, bank->bus_width, 1, command); + if (cfi_intel_wait_status_busy(bank, 1000 * (1 << cfi_info->buf_write_timeout_max)) != 0x80) + { + cfi_command(bank, 0xff, command); + target->type->write_memory(target, flash_address(bank, 0, 0x0), bank->bus_width, 1, command); + + ERROR("couldn't start buffer write operation at base 0x%x, address %x", bank->base, address); + return ERROR_FLASH_OPERATION_FAILED; + } + + /* Write buffer wordcount-1 and data words */ + cfi_command(bank, bufferwsize-1, command); + target->type->write_memory(target, address, bank->bus_width, 1, command); + + target->type->write_memory(target, address, bank->bus_width, bufferwsize, word); + + /* Commit write operation */ + cfi_command(bank, 0xd0, command); + target->type->write_memory(target, address, bank->bus_width, 1, command); + if (cfi_intel_wait_status_busy(bank, 1000 * (1 << cfi_info->buf_write_timeout_max)) != 0x80) + { + cfi_command(bank, 0xff, command); + target->type->write_memory(target, flash_address(bank, 0, 0x0), bank->bus_width, 1, command); + + ERROR("Buffer write at base 0x%x, address %x failed.", bank->base, address); + return ERROR_FLASH_OPERATION_FAILED; + } + + return ERROR_OK; +} + +int cfi_spansion_write_word(struct flash_bank_s *bank, u8 *word, u32 address) +{ + cfi_flash_bank_t *cfi_info = bank->driver_priv; + cfi_spansion_pri_ext_t *pri_ext = cfi_info->pri_ext; + target_t *target = bank->target; + u8 command[8]; + + cfi_command(bank, 0xaa, command); + target->type->write_memory(target, flash_address(bank, 0, pri_ext->_unlock1), bank->bus_width, 1, command); + + cfi_command(bank, 0x55, command); + target->type->write_memory(target, flash_address(bank, 0, pri_ext->_unlock2), bank->bus_width, 1, command); + + cfi_command(bank, 0xa0, command); + target->type->write_memory(target, flash_address(bank, 0, pri_ext->_unlock1), bank->bus_width, 1, command); + + target->type->write_memory(target, address, bank->bus_width, 1, word); + + if (cfi_spansion_wait_status_busy(bank, 1000 * (1 << cfi_info->word_write_timeout_max)) != ERROR_OK) + { + cfi_command(bank, 0xf0, command); + target->type->write_memory(target, flash_address(bank, 0, 0x0), bank->bus_width, 1, command); + + ERROR("couldn't write word at base 0x%x, address %x", bank->base, address); + return ERROR_FLASH_OPERATION_FAILED; + } + + return ERROR_OK; +} + +int cfi_write_word(struct flash_bank_s *bank, u8 *word, u32 address) +{ + cfi_flash_bank_t *cfi_info = bank->driver_priv; + + switch(cfi_info->pri_id) + { + case 1: + case 3: + return cfi_intel_write_word(bank, word, address); + break; + case 2: + return cfi_spansion_write_word(bank, word, address); + break; + default: + ERROR("cfi primary command set %i unsupported", cfi_info->pri_id); + break; + } + + return ERROR_FLASH_OPERATION_FAILED; +} + +int cfi_write_words(struct flash_bank_s *bank, u8 *word, u32 wordcount, u32 address) +{ + cfi_flash_bank_t *cfi_info = bank->driver_priv; + + switch(cfi_info->pri_id) + { + case 1: + case 3: + return cfi_intel_write_words(bank, word, wordcount, address); + break; + case 2: + //return cfi_spansion_write_words(bank, word, address); + ERROR("cfi primary command set %i unimplemented - FIXME", cfi_info->pri_id); + break; + default: + ERROR("cfi primary command set %i unsupported", cfi_info->pri_id); + break; + } + + return ERROR_FLASH_OPERATION_FAILED; +} + +int cfi_write(struct flash_bank_s *bank, u8 *buffer, u32 offset, u32 count) +{ + cfi_flash_bank_t *cfi_info = bank->driver_priv; + target_t *target = bank->target; + u32 address = bank->base + offset; /* address of first byte to be programmed */ + u32 write_p, copy_p; + int align; /* number of unaligned bytes */ + int blk_count; /* number of bus_width bytes for block copy */ + u8 current_word[CFI_MAX_BUS_WIDTH * 4]; /* word (bus_width size) currently being programmed */ + int i; + int retval; + + if (offset + count > bank->size) + return ERROR_FLASH_DST_OUT_OF_BANK; + + if (cfi_info->qry[0] != 'Q') + return ERROR_FLASH_BANK_NOT_PROBED; + + /* start at the first byte of the first word (bus_width size) */ + write_p = address & ~(bank->bus_width - 1); + if ((align = address - write_p) != 0) + { + INFO("Fixup %d unaligned head bytes", align ); + + for (i = 0; i < bank->bus_width; i++) + current_word[i] = 0; + copy_p = write_p; + + /* copy bytes before the first write address */ + for (i = 0; i < align; ++i, ++copy_p) + { + u8 byte; + target->type->read_memory(target, copy_p, 1, 1, &byte); + cfi_add_byte(bank, current_word, byte); + } + + /* add bytes from the buffer */ + for (; (i < bank->bus_width) && (count > 0); i++) + { + cfi_add_byte(bank, current_word, *buffer++); + count--; + copy_p++; + } + + /* if the buffer is already finished, copy bytes after the last write address */ + for (; (count == 0) && (i < bank->bus_width); ++i, ++copy_p) + { + u8 byte; + target->type->read_memory(target, copy_p, 1, 1, &byte); + cfi_add_byte(bank, current_word, byte); + } + + retval = cfi_write_word(bank, current_word, write_p); + if (retval != ERROR_OK) + return retval; + write_p = copy_p; + } + + /* handle blocks of bus_size aligned bytes */ + blk_count = count & ~(bank->bus_width - 1); /* round down, leave tail bytes */ + switch(cfi_info->pri_id) + { + /* try block writes (fails without working area) */ + case 1: + case 3: + retval = cfi_intel_write_block(bank, buffer, write_p, blk_count); + break; + case 2: + retval = cfi_spansion_write_block(bank, buffer, write_p, blk_count); + break; + default: + ERROR("cfi primary command set %i unsupported", cfi_info->pri_id); + retval = ERROR_FLASH_OPERATION_FAILED; + break; + } + if (retval == ERROR_OK) + { + /* Increment pointers and decrease count on succesful block write */ + buffer += blk_count; + write_p += blk_count; + count -= blk_count; + } + else + { + if (retval == ERROR_TARGET_RESOURCE_NOT_AVAILABLE) + { + u32 buffersize = 1UL << cfi_info->max_buf_write_size; + u32 buffermask = buffersize-1; + u32 bufferwsize; + + switch(bank->chip_width) + { + case 4 : bufferwsize = buffersize / 4; break; + case 2 : bufferwsize = buffersize / 2; break; + case 1 : bufferwsize = buffersize; break; + default: + ERROR("Unsupported chip width %d", bank->chip_width); + return ERROR_FLASH_OPERATION_FAILED; + } + + /* fall back to memory writes */ + while (count > bank->bus_width) + { + if ((write_p & 0xff) == 0) + { + INFO("Programming at %08x, count %08x bytes remaining", write_p, count); + } +#if 0 + /* NB! this is broken for spansion! */ + if ((count > bufferwsize) && !(write_p & buffermask)) + { + retval = cfi_write_words(bank, buffer, bufferwsize, write_p); + if (retval != ERROR_OK) + return retval; + + buffer += buffersize; + write_p += buffersize; + count -= buffersize; + } + else +#endif + { + for (i = 0; i < bank->bus_width; i++) + current_word[i] = 0; + + for (i = 0; i < bank->bus_width; i++) + { + cfi_add_byte(bank, current_word, *buffer++); + } + + retval = cfi_write_word(bank, current_word, write_p); + if (retval != ERROR_OK) + return retval; + + write_p += bank->bus_width; + count -= bank->bus_width; + } + } + } + else + return retval; + } + + /* return to read array mode, so we can read from flash again for padding */ + cfi_command(bank, 0xf0, current_word); + target->type->write_memory(target, flash_address(bank, 0, 0x0), bank->bus_width, 1, current_word); + cfi_command(bank, 0xff, current_word); + target->type->write_memory(target, flash_address(bank, 0, 0x0), bank->bus_width, 1, current_word); + + /* handle unaligned tail bytes */ + if (count > 0) + { + INFO("Fixup %d unaligned tail bytes", count ); + + copy_p = write_p; + for (i = 0; i < bank->bus_width; i++) + current_word[i] = 0; + + for (i = 0; (i < bank->bus_width) && (count > 0); ++i, ++copy_p) + { + cfi_add_byte(bank, current_word, *buffer++); + count--; + } + for (; i < bank->bus_width; ++i, ++copy_p) + { + u8 byte; + target->type->read_memory(target, copy_p, 1, 1, &byte); + cfi_add_byte(bank, current_word, byte); + } + retval = cfi_write_word(bank, current_word, write_p); + if (retval != ERROR_OK) + return retval; + } + + /* return to read array mode */ + cfi_command(bank, 0xf0, current_word); + target->type->write_memory(target, flash_address(bank, 0, 0x0), bank->bus_width, 1, current_word); + cfi_command(bank, 0xff, current_word); + target->type->write_memory(target, flash_address(bank, 0, 0x0), bank->bus_width, 1, current_word); + + return ERROR_OK; +} + +void cfi_fixup_atmel_reversed_erase_regions(flash_bank_t *bank, void *param) +{ + cfi_flash_bank_t *cfi_info = bank->driver_priv; + cfi_spansion_pri_ext_t *pri_ext = cfi_info->pri_ext; + + pri_ext->_reversed_geometry = 1; +} + +void cfi_fixup_0002_erase_regions(flash_bank_t *bank, void *param) +{ + int i; + cfi_flash_bank_t *cfi_info = bank->driver_priv; + cfi_spansion_pri_ext_t *pri_ext = cfi_info->pri_ext; + + if ((pri_ext->_reversed_geometry) || (pri_ext->TopBottom == 3)) + { + DEBUG("swapping reversed erase region information on cmdset 0002 device"); + + for (i = 0; i < cfi_info->num_erase_regions / 2; i++) + { + int j = (cfi_info->num_erase_regions - 1) - i; + u32 swap; + + swap = cfi_info->erase_region_info[i]; + cfi_info->erase_region_info[i] = cfi_info->erase_region_info[j]; + cfi_info->erase_region_info[j] = swap; + } + } +} + +void cfi_fixup_0002_unlock_addresses(flash_bank_t *bank, void *param) +{ + cfi_flash_bank_t *cfi_info = bank->driver_priv; + cfi_spansion_pri_ext_t *pri_ext = cfi_info->pri_ext; + cfi_unlock_addresses_t *unlock_addresses = param; + + pri_ext->_unlock1 = unlock_addresses->unlock1; + pri_ext->_unlock2 = unlock_addresses->unlock2; +} + +int cfi_probe(struct flash_bank_s *bank) +{ + cfi_flash_bank_t *cfi_info = bank->driver_priv; + target_t *target = bank->target; + u8 command[8]; + int num_sectors = 0; + int i; + int sector = 0; + u32 offset = 0; + u32 unlock1 = 0x555; + u32 unlock2 = 0x2aa; + + cfi_info->probed = 0; + + /* JEDEC standard JESD21C uses 0x5555 and 0x2aaa as unlock addresses, + * while CFI compatible AMD/Spansion flashes use 0x555 and 0x2aa + */ + if (cfi_info->jedec_probe) + { + unlock1 = 0x5555; + unlock2 = 0x2aaa; + } + + /* switch to read identifier codes mode ("AUTOSELECT") */ + cfi_command(bank, 0xaa, command); + target->type->write_memory(target, flash_address(bank, 0, unlock1), bank->bus_width, 1, command); + cfi_command(bank, 0x55, command); + target->type->write_memory(target, flash_address(bank, 0, unlock2), bank->bus_width, 1, command); + cfi_command(bank, 0x90, command); + target->type->write_memory(target, flash_address(bank, 0, unlock1), bank->bus_width, 1, command); + + if (bank->chip_width == 1) + { + u8 manufacturer, device_id; + target_read_u8(target, bank->base + 0x0, &manufacturer); + target_read_u8(target, bank->base + 0x1, &device_id); + cfi_info->manufacturer = manufacturer; + cfi_info->device_id = device_id; + } + else if (bank->chip_width == 2) + { + target_read_u16(target, bank->base + 0x0, &cfi_info->manufacturer); + target_read_u16(target, bank->base + 0x2, &cfi_info->device_id); + } + + /* switch back to read array mode */ + cfi_command(bank, 0xf0, command); + target->type->write_memory(target, flash_address(bank, 0, 0x00), bank->bus_width, 1, command); + cfi_command(bank, 0xff, command); + target->type->write_memory(target, flash_address(bank, 0, 0x00), bank->bus_width, 1, command); + + cfi_fixup(bank, cfi_jedec_fixups); + + /* query only if this is a CFI compatible flash, + * otherwise the relevant info has already been filled in + */ + if (cfi_info->not_cfi == 0) + { + /* enter CFI query mode + * according to JEDEC Standard No. 68.01, + * a single bus sequence with address = 0x55, data = 0x98 should put + * the device into CFI query mode. + * + * SST flashes clearly violate this, and we will consider them incompatbile for now + */ + cfi_command(bank, 0x98, command); + target->type->write_memory(target, flash_address(bank, 0, 0x55), bank->bus_width, 1, command); + + cfi_info->qry[0] = cfi_query_u8(bank, 0, 0x10); + cfi_info->qry[1] = cfi_query_u8(bank, 0, 0x11); + cfi_info->qry[2] = cfi_query_u8(bank, 0, 0x12); + + DEBUG("CFI qry returned: 0x%2.2x 0x%2.2x 0x%2.2x", cfi_info->qry[0], cfi_info->qry[1], cfi_info->qry[2]); + + if ((cfi_info->qry[0] != 'Q') || (cfi_info->qry[1] != 'R') || (cfi_info->qry[2] != 'Y')) + { + cfi_command(bank, 0xf0, command); + target->type->write_memory(target, flash_address(bank, 0, 0x0), bank->bus_width, 1, command); + cfi_command(bank, 0xff, command); + target->type->write_memory(target, flash_address(bank, 0, 0x0), bank->bus_width, 1, command); + return ERROR_FLASH_BANK_INVALID; + } + + cfi_info->pri_id = cfi_query_u16(bank, 0, 0x13); + cfi_info->pri_addr = cfi_query_u16(bank, 0, 0x15); + cfi_info->alt_id = cfi_query_u16(bank, 0, 0x17); + cfi_info->alt_addr = cfi_query_u16(bank, 0, 0x19); + + DEBUG("qry: '%c%c%c', pri_id: 0x%4.4x, pri_addr: 0x%4.4x, alt_id: 0x%4.4x, alt_addr: 0x%4.4x", cfi_info->qry[0], cfi_info->qry[1], cfi_info->qry[2], cfi_info->pri_id, cfi_info->pri_addr, cfi_info->alt_id, cfi_info->alt_addr); + + cfi_info->vcc_min = cfi_query_u8(bank, 0, 0x1b); + cfi_info->vcc_max = cfi_query_u8(bank, 0, 0x1c); + cfi_info->vpp_min = cfi_query_u8(bank, 0, 0x1d); + cfi_info->vpp_max = cfi_query_u8(bank, 0, 0x1e); + cfi_info->word_write_timeout_typ = cfi_query_u8(bank, 0, 0x1f); + cfi_info->buf_write_timeout_typ = cfi_query_u8(bank, 0, 0x20); + cfi_info->block_erase_timeout_typ = cfi_query_u8(bank, 0, 0x21); + cfi_info->chip_erase_timeout_typ = cfi_query_u8(bank, 0, 0x22); + cfi_info->word_write_timeout_max = cfi_query_u8(bank, 0, 0x23); + cfi_info->buf_write_timeout_max = cfi_query_u8(bank, 0, 0x24); + cfi_info->block_erase_timeout_max = cfi_query_u8(bank, 0, 0x25); + cfi_info->chip_erase_timeout_max = cfi_query_u8(bank, 0, 0x26); + + DEBUG("Vcc min: %1.1x.%1.1x, Vcc max: %1.1x.%1.1x, Vpp min: %1.1x.%1.1x, Vpp max: %1.1x.%1.1x", + (cfi_info->vcc_min & 0xf0) >> 4, cfi_info->vcc_min & 0x0f, + (cfi_info->vcc_max & 0xf0) >> 4, cfi_info->vcc_max & 0x0f, + (cfi_info->vpp_min & 0xf0) >> 4, cfi_info->vpp_min & 0x0f, + (cfi_info->vpp_max & 0xf0) >> 4, cfi_info->vpp_max & 0x0f); + DEBUG("typ. word write timeout: %u, typ. buf write timeout: %u, typ. block erase timeout: %u, typ. chip erase timeout: %u", 1 << cfi_info->word_write_timeout_typ, 1 << cfi_info->buf_write_timeout_typ, + 1 << cfi_info->block_erase_timeout_typ, 1 << cfi_info->chip_erase_timeout_typ); + DEBUG("max. word write timeout: %u, max. buf write timeout: %u, max. block erase timeout: %u, max. chip erase timeout: %u", (1 << cfi_info->word_write_timeout_max) * (1 << cfi_info->word_write_timeout_typ), + (1 << cfi_info->buf_write_timeout_max) * (1 << cfi_info->buf_write_timeout_typ), + (1 << cfi_info->block_erase_timeout_max) * (1 << cfi_info->block_erase_timeout_typ), + (1 << cfi_info->chip_erase_timeout_max) * (1 << cfi_info->chip_erase_timeout_typ)); + + cfi_info->dev_size = cfi_query_u8(bank, 0, 0x27); + cfi_info->interface_desc = cfi_query_u16(bank, 0, 0x28); + cfi_info->max_buf_write_size = cfi_query_u16(bank, 0, 0x2a); + cfi_info->num_erase_regions = cfi_query_u8(bank, 0, 0x2c); + + DEBUG("size: 0x%x, interface desc: %i, max buffer write size: %x", 1 << cfi_info->dev_size, cfi_info->interface_desc, (1 << cfi_info->max_buf_write_size)); + + if (((1 << cfi_info->dev_size) * bank->bus_width / bank->chip_width) != bank->size) + { + WARNING("configuration specifies 0x%x size, but a 0x%x size flash was found", bank->size, 1 << cfi_info->dev_size); + } + + if (cfi_info->num_erase_regions) + { + cfi_info->erase_region_info = malloc(4 * cfi_info->num_erase_regions); + for (i = 0; i < cfi_info->num_erase_regions; i++) + { + cfi_info->erase_region_info[i] = cfi_query_u32(bank, 0, 0x2d + (4 * i)); + DEBUG("erase region[%i]: %i blocks of size 0x%x", i, (cfi_info->erase_region_info[i] & 0xffff) + 1, (cfi_info->erase_region_info[i] >> 16) * 256); + } + } + else + { + cfi_info->erase_region_info = NULL; + } + + /* We need to read the primary algorithm extended query table before calculating + * the sector layout to be able to apply fixups + */ + switch(cfi_info->pri_id) + { + /* Intel command set (standard and extended) */ + case 0x0001: + case 0x0003: + cfi_read_intel_pri_ext(bank); + break; + /* AMD/Spansion, Atmel, ... command set */ + case 0x0002: + cfi_read_0002_pri_ext(bank); + break; + default: + ERROR("cfi primary command set %i unsupported", cfi_info->pri_id); + break; + } + + /* return to read array mode + * we use both reset commands, as some Intel flashes fail to recognize the 0xF0 command + */ + cfi_command(bank, 0xf0, command); + target->type->write_memory(target, flash_address(bank, 0, 0x0), bank->bus_width, 1, command); + cfi_command(bank, 0xff, command); + target->type->write_memory(target, flash_address(bank, 0, 0x0), bank->bus_width, 1, command); + } + + /* apply fixups depending on the primary command set */ + switch(cfi_info->pri_id) + { + /* Intel command set (standard and extended) */ + case 0x0001: + case 0x0003: + cfi_fixup(bank, cfi_0001_fixups); + break; + /* AMD/Spansion, Atmel, ... command set */ + case 0x0002: + cfi_fixup(bank, cfi_0002_fixups); + break; + default: + ERROR("cfi primary command set %i unsupported", cfi_info->pri_id); + break; + } + + if (cfi_info->num_erase_regions == 0) + { + /* a device might have only one erase block, spanning the whole device */ + bank->num_sectors = 1; + bank->sectors = malloc(sizeof(flash_sector_t)); + + bank->sectors[sector].offset = 0x0; + bank->sectors[sector].size = bank->size; + bank->sectors[sector].is_erased = -1; + bank->sectors[sector].is_protected = -1; + } + else + { + for (i = 0; i < cfi_info->num_erase_regions; i++) + { + num_sectors += (cfi_info->erase_region_info[i] & 0xffff) + 1; + } + + bank->num_sectors = num_sectors; + bank->sectors = malloc(sizeof(flash_sector_t) * num_sectors); + + for (i = 0; i < cfi_info->num_erase_regions; i++) + { + int j; + for (j = 0; j < (cfi_info->erase_region_info[i] & 0xffff) + 1; j++) + { + bank->sectors[sector].offset = offset; + bank->sectors[sector].size = ((cfi_info->erase_region_info[i] >> 16) * 256) * bank->bus_width / bank->chip_width; + offset += bank->sectors[sector].size; + bank->sectors[sector].is_erased = -1; + bank->sectors[sector].is_protected = -1; + sector++; + } + } + } + + cfi_info->probed = 1; + + return ERROR_OK; +} + +int cfi_auto_probe(struct flash_bank_s *bank) +{ + cfi_flash_bank_t *cfi_info = bank->driver_priv; + if (cfi_info->probed) + return ERROR_OK; + return cfi_probe(bank); +} + +int cfi_erase_check(struct flash_bank_s *bank) +{ + cfi_flash_bank_t *cfi_info = bank->driver_priv; + target_t *target = bank->target; + int i; + int retval; + + if (!cfi_info->erase_check_algorithm) + { + u32 erase_check_code[] = + { + 0xe4d03001, /* ldrb r3, [r0], #1 */ + 0xe0022003, /* and r2, r2, r3 */ + 0xe2511001, /* subs r1, r1, #1 */ + 0x1afffffb, /* b -4 */ + 0xeafffffe /* b 0 */ + }; + + /* make sure we have a working area */ + if (target_alloc_working_area(target, 20, &cfi_info->erase_check_algorithm) != ERROR_OK) + { + WARNING("no working area available, falling back to slow memory reads"); + } + else + { + u8 erase_check_code_buf[5 * 4]; + + for (i = 0; i < 5; i++) + target_buffer_set_u32(target, erase_check_code_buf + (i*4), erase_check_code[i]); + + /* write algorithm code to working area */ + target->type->write_memory(target, cfi_info->erase_check_algorithm->address, 4, 5, erase_check_code_buf); + } + } + + if (!cfi_info->erase_check_algorithm) + { + u32 *buffer = malloc(4096); + + for (i = 0; i < bank->num_sectors; i++) + { + u32 address = bank->base + bank->sectors[i].offset; + u32 size = bank->sectors[i].size; + u32 check = 0xffffffffU; + int erased = 1; + + while (size > 0) + { + u32 thisrun_size = (size > 4096) ? 4096 : size; + int j; + + target->type->read_memory(target, address, 4, thisrun_size / 4, (u8*)buffer); + + for (j = 0; j < thisrun_size / 4; j++) + check &= buffer[j]; + + if (check != 0xffffffff) + { + erased = 0; + break; + } + + size -= thisrun_size; + address += thisrun_size; + } + + bank->sectors[i].is_erased = erased; + } + + free(buffer); + } + else + { + for (i = 0; i < bank->num_sectors; i++) + { + u32 address = bank->base + bank->sectors[i].offset; + u32 size = bank->sectors[i].size; + + reg_param_t reg_params[3]; + armv4_5_algorithm_t armv4_5_info; + + armv4_5_info.common_magic = ARMV4_5_COMMON_MAGIC; + armv4_5_info.core_mode = ARMV4_5_MODE_SVC; + armv4_5_info.core_state = ARMV4_5_STATE_ARM; + + init_reg_param(®_params[0], "r0", 32, PARAM_OUT); + buf_set_u32(reg_params[0].value, 0, 32, address); + + init_reg_param(®_params[1], "r1", 32, PARAM_OUT); + buf_set_u32(reg_params[1].value, 0, 32, size); + + init_reg_param(®_params[2], "r2", 32, PARAM_IN_OUT); + buf_set_u32(reg_params[2].value, 0, 32, 0xff); + + if ((retval = target->type->run_algorithm(target, 0, NULL, 3, reg_params, cfi_info->erase_check_algorithm->address, cfi_info->erase_check_algorithm->address + 0x10, 10000, &armv4_5_info)) != ERROR_OK) + return ERROR_FLASH_OPERATION_FAILED; + + if (buf_get_u32(reg_params[2].value, 0, 32) == 0xff) + bank->sectors[i].is_erased = 1; + else + bank->sectors[i].is_erased = 0; + + destroy_reg_param(®_params[0]); + destroy_reg_param(®_params[1]); + destroy_reg_param(®_params[2]); + } + } + + return ERROR_OK; +} + +int cfi_intel_protect_check(struct flash_bank_s *bank) +{ + cfi_flash_bank_t *cfi_info = bank->driver_priv; + cfi_intel_pri_ext_t *pri_ext = cfi_info->pri_ext; + target_t *target = bank->target; + u8 command[CFI_MAX_BUS_WIDTH]; + int i; + + /* check if block lock bits are supported on this device */ + if (!(pri_ext->blk_status_reg_mask & 0x1)) + return ERROR_FLASH_OPERATION_FAILED; + + cfi_command(bank, 0x90, command); + target->type->write_memory(target, flash_address(bank, 0, 0x55), bank->bus_width, 1, command); + + for (i = 0; i < bank->num_sectors; i++) + { + u8 block_status = cfi_get_u8(bank, i, 0x2); + + if (block_status & 1) + bank->sectors[i].is_protected = 1; + else + bank->sectors[i].is_protected = 0; + } + + cfi_command(bank, 0xff, command); + target->type->write_memory(target, flash_address(bank, 0, 0x0), bank->bus_width, 1, command); + + return ERROR_OK; +} + +int cfi_spansion_protect_check(struct flash_bank_s *bank) +{ + cfi_flash_bank_t *cfi_info = bank->driver_priv; + cfi_spansion_pri_ext_t *pri_ext = cfi_info->pri_ext; + target_t *target = bank->target; + u8 command[8]; + int i; + + cfi_command(bank, 0xaa, command); + target->type->write_memory(target, flash_address(bank, 0, pri_ext->_unlock1), bank->bus_width, 1, command); + + cfi_command(bank, 0x55, command); + target->type->write_memory(target, flash_address(bank, 0, pri_ext->_unlock2), bank->bus_width, 1, command); + + cfi_command(bank, 0x90, command); + target->type->write_memory(target, flash_address(bank, 0, pri_ext->_unlock1), bank->bus_width, 1, command); + + for (i = 0; i < bank->num_sectors; i++) + { + u8 block_status = cfi_get_u8(bank, i, 0x2); + + if (block_status & 1) + bank->sectors[i].is_protected = 1; + else + bank->sectors[i].is_protected = 0; + } + + cfi_command(bank, 0xf0, command); + target->type->write_memory(target, flash_address(bank, 0, 0x0), bank->bus_width, 1, command); + + return ERROR_OK; +} + +int cfi_protect_check(struct flash_bank_s *bank) +{ + cfi_flash_bank_t *cfi_info = bank->driver_priv; + + if (cfi_info->qry[0] != 'Q') + return ERROR_FLASH_BANK_NOT_PROBED; + + switch(cfi_info->pri_id) + { + case 1: + case 3: + return cfi_intel_protect_check(bank); + break; + case 2: + return cfi_spansion_protect_check(bank); + break; + default: + ERROR("cfi primary command set %i unsupported", cfi_info->pri_id); + break; + } + + return ERROR_OK; +} + +int cfi_info(struct flash_bank_s *bank, char *buf, int buf_size) +{ + int printed; + cfi_flash_bank_t *cfi_info = bank->driver_priv; + + if (cfi_info->qry[0] == (char)-1) + { + printed = snprintf(buf, buf_size, "\ncfi flash bank not probed yet\n"); + return ERROR_OK; + } + + printed = snprintf(buf, buf_size, "\ncfi information:\n"); + buf += printed; + buf_size -= printed; + + printed = snprintf(buf, buf_size, "\nmfr: 0x%4.4x, id:0x%4.4x\n", + cfi_info->manufacturer, cfi_info->device_id); + buf += printed; + buf_size -= printed; + + printed = snprintf(buf, buf_size, "qry: '%c%c%c', pri_id: 0x%4.4x, pri_addr: 0x%4.4x, alt_id: 0x%4.4x, alt_addr: 0x%4.4x\n", cfi_info->qry[0], cfi_info->qry[1], cfi_info->qry[2], cfi_info->pri_id, cfi_info->pri_addr, cfi_info->alt_id, cfi_info->alt_addr); + buf += printed; + buf_size -= printed; + + printed = snprintf(buf, buf_size, "Vcc min: %1.1x.%1.1x, Vcc max: %1.1x.%1.1x, Vpp min: %1.1x.%1.1x, Vpp max: %1.1x.%1.1x\n", (cfi_info->vcc_min & 0xf0) >> 4, cfi_info->vcc_min & 0x0f, + (cfi_info->vcc_max & 0xf0) >> 4, cfi_info->vcc_max & 0x0f, + (cfi_info->vpp_min & 0xf0) >> 4, cfi_info->vpp_min & 0x0f, + (cfi_info->vpp_max & 0xf0) >> 4, cfi_info->vpp_max & 0x0f); + buf += printed; + buf_size -= printed; + + printed = snprintf(buf, buf_size, "typ. word write timeout: %u, typ. buf write timeout: %u, typ. block erase timeout: %u, typ. chip erase timeout: %u\n", 1 << cfi_info->word_write_timeout_typ, 1 << cfi_info->buf_write_timeout_typ, + 1 << cfi_info->block_erase_timeout_typ, 1 << cfi_info->chip_erase_timeout_typ); + buf += printed; + buf_size -= printed; + + printed = snprintf(buf, buf_size, "max. word write timeout: %u, max. buf write timeout: %u, max. block erase timeout: %u, max. chip erase timeout: %u\n", (1 << cfi_info->word_write_timeout_max) * (1 << cfi_info->word_write_timeout_typ), + (1 << cfi_info->buf_write_timeout_max) * (1 << cfi_info->buf_write_timeout_typ), + (1 << cfi_info->block_erase_timeout_max) * (1 << cfi_info->block_erase_timeout_typ), + (1 << cfi_info->chip_erase_timeout_max) * (1 << cfi_info->chip_erase_timeout_typ)); + buf += printed; + buf_size -= printed; + + printed = snprintf(buf, buf_size, "size: 0x%x, interface desc: %i, max buffer write size: %x\n", 1 << cfi_info->dev_size, cfi_info->interface_desc, cfi_info->max_buf_write_size); + buf += printed; + buf_size -= printed; + + switch(cfi_info->pri_id) + { + case 1: + case 3: + cfi_intel_info(bank, buf, buf_size); + break; + case 2: + cfi_spansion_info(bank, buf, buf_size); + break; + default: + ERROR("cfi primary command set %i unsupported", cfi_info->pri_id); + break; + } + + return ERROR_OK; +} diff --git a/src/flash/s3c2440_nand.c b/src/flash/s3c2440_nand.c index 1390a3fb..4e3234f8 100644 --- a/src/flash/s3c2440_nand.c +++ b/src/flash/s3c2440_nand.c @@ -1,179 +1,179 @@ -/* src/flash/s3c2440_nand.c - * - * S3C2440 OpenOCD NAND Flash controller support. - * - * Copyright 2007,2008 Ben Dooks - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * Many thanks to Simtec Electronics for sponsoring this work. - */ - -#ifdef HAVE_CONFIG_H -#include "config.h" -#endif - -#include "replacements.h" -#include "log.h" - -#include -#include - -#include "nand.h" -#include "s3c24xx_nand.h" -#include "target.h" - -int s3c2440_nand_device_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc, struct nand_device_s *device); -int s3c2440_init(struct nand_device_s *device); -int s3c2440_nand_ready(struct nand_device_s *device, int timeout); - -nand_flash_controller_t s3c2440_nand_controller = -{ - .name = "s3c2440", - .nand_device_command = s3c2440_nand_device_command, - .register_commands = s3c24xx_register_commands, - .init = s3c2440_init, - .reset = s3c24xx_reset, - .command = s3c24xx_command, - .address = s3c24xx_address, - .write_data = s3c24xx_write_data, - .read_data = s3c24xx_read_data, - .write_page = s3c24xx_write_page, - .read_page = s3c24xx_read_page, - .write_block_data = s3c2440_write_block_data, - .read_block_data = s3c2440_read_block_data, - .controller_ready = s3c24xx_controller_ready, - .nand_ready = s3c2440_nand_ready, -}; - -int s3c2440_nand_device_command(struct command_context_s *cmd_ctx, char *cmd, - char **args, int argc, - struct nand_device_s *device) -{ - s3c24xx_nand_controller_t *info; - - info = s3c24xx_nand_device_command(cmd_ctx, cmd, args, argc, device); - if (info == NULL) { - return ERROR_NAND_DEVICE_INVALID; - } - - /* fill in the address fields for the core device */ - info->cmd = S3C2440_NFCMD; - info->addr = S3C2440_NFADDR; - info->data = S3C2440_NFDATA; - info->nfstat = S3C2440_NFSTAT; - - return ERROR_OK; -} - -int s3c2440_init(struct nand_device_s *device) -{ - s3c24xx_nand_controller_t *s3c24xx_info = device->controller_priv; - target_t *target = s3c24xx_info->target; - u32 version; - - target_write_u32(target, S3C2410_NFCONF, - S3C2440_NFCONF_TACLS(3) | - S3C2440_NFCONF_TWRPH0(7) | - S3C2440_NFCONF_TWRPH1(7)); - - target_write_u32(target, S3C2440_NFCONT, - S3C2440_NFCONT_INITECC | S3C2440_NFCONT_ENABLE); - - return ERROR_OK; -} - -int s3c2440_nand_ready(struct nand_device_s *device, int timeout) -{ - s3c24xx_nand_controller_t *s3c24xx_info = device->controller_priv; - target_t *target = s3c24xx_info->target; - u8 status; - - if (target->state != TARGET_HALTED) { - ERROR("target must be halted to use S3C24XX NAND flash controller"); - return ERROR_NAND_OPERATION_FAILED; - } - - do { - target_read_u8(target, s3c24xx_info->nfstat, &status); - - if (status & S3C2440_NFSTAT_READY) - return 1; - - usleep(1000); - } while (timeout-- > 0); - - - return 0; -} - -/* use the fact we can read/write 4 bytes in one go via a single 32bit op */ - -int s3c2440_read_block_data(struct nand_device_s *device, u8 *data, int data_size) -{ - s3c24xx_nand_controller_t *s3c24xx_info = device->controller_priv; - target_t *target = s3c24xx_info->target; - u32 nfdata = s3c24xx_info->data; - u32 tmp; - - INFO("%s: reading data: %p, %p, %d\n", __func__, device, data, data_size); - - if (target->state != TARGET_HALTED) { - ERROR("target must be halted to use S3C24XX NAND flash controller"); - return ERROR_NAND_OPERATION_FAILED; - } - - while (data_size >= 4) { - target_read_u32(target, nfdata, &tmp); - - data[0] = tmp; - data[1] = tmp >> 8; - data[2] = tmp >> 16; - data[3] = tmp >> 24; - - data_size -= 4; - data += 4; - } - - while (data_size > 0) { - target_read_u8(target, nfdata, data); - - data_size -= 1; - data += 1; - } - - return ERROR_OK; -} - -int s3c2440_write_block_data(struct nand_device_s *device, u8 *data, int data_size) -{ - s3c24xx_nand_controller_t *s3c24xx_info = device->controller_priv; - target_t *target = s3c24xx_info->target; - u32 nfdata = s3c24xx_info->data; - u32 tmp; - - if (target->state != TARGET_HALTED) { - ERROR("target must be halted to use S3C24XX NAND flash controller"); - return ERROR_NAND_OPERATION_FAILED; - } - - while (data_size >= 4) { - tmp = le_to_h_u32(data); - target_write_u32(target, nfdata, tmp); - - data_size -= 4; - data += 4; - } - - while (data_size > 0) { - target_write_u8(target, nfdata, *data); - - data_size -= 1; - data += 1; - } - - return ERROR_OK; -} +/* src/flash/s3c2440_nand.c + * + * S3C2440 OpenOCD NAND Flash controller support. + * + * Copyright 2007,2008 Ben Dooks + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * Many thanks to Simtec Electronics for sponsoring this work. + */ + +#ifdef HAVE_CONFIG_H +#include "config.h" +#endif + +#include "replacements.h" +#include "log.h" + +#include +#include + +#include "nand.h" +#include "s3c24xx_nand.h" +#include "target.h" + +int s3c2440_nand_device_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc, struct nand_device_s *device); +int s3c2440_init(struct nand_device_s *device); +int s3c2440_nand_ready(struct nand_device_s *device, int timeout); + +nand_flash_controller_t s3c2440_nand_controller = +{ + .name = "s3c2440", + .nand_device_command = s3c2440_nand_device_command, + .register_commands = s3c24xx_register_commands, + .init = s3c2440_init, + .reset = s3c24xx_reset, + .command = s3c24xx_command, + .address = s3c24xx_address, + .write_data = s3c24xx_write_data, + .read_data = s3c24xx_read_data, + .write_page = s3c24xx_write_page, + .read_page = s3c24xx_read_page, + .write_block_data = s3c2440_write_block_data, + .read_block_data = s3c2440_read_block_data, + .controller_ready = s3c24xx_controller_ready, + .nand_ready = s3c2440_nand_ready, +}; + +int s3c2440_nand_device_command(struct command_context_s *cmd_ctx, char *cmd, + char **args, int argc, + struct nand_device_s *device) +{ + s3c24xx_nand_controller_t *info; + + info = s3c24xx_nand_device_command(cmd_ctx, cmd, args, argc, device); + if (info == NULL) { + return ERROR_NAND_DEVICE_INVALID; + } + + /* fill in the address fields for the core device */ + info->cmd = S3C2440_NFCMD; + info->addr = S3C2440_NFADDR; + info->data = S3C2440_NFDATA; + info->nfstat = S3C2440_NFSTAT; + + return ERROR_OK; +} + +int s3c2440_init(struct nand_device_s *device) +{ + s3c24xx_nand_controller_t *s3c24xx_info = device->controller_priv; + target_t *target = s3c24xx_info->target; + u32 version; + + target_write_u32(target, S3C2410_NFCONF, + S3C2440_NFCONF_TACLS(3) | + S3C2440_NFCONF_TWRPH0(7) | + S3C2440_NFCONF_TWRPH1(7)); + + target_write_u32(target, S3C2440_NFCONT, + S3C2440_NFCONT_INITECC | S3C2440_NFCONT_ENABLE); + + return ERROR_OK; +} + +int s3c2440_nand_ready(struct nand_device_s *device, int timeout) +{ + s3c24xx_nand_controller_t *s3c24xx_info = device->controller_priv; + target_t *target = s3c24xx_info->target; + u8 status; + + if (target->state != TARGET_HALTED) { + ERROR("target must be halted to use S3C24XX NAND flash controller"); + return ERROR_NAND_OPERATION_FAILED; + } + + do { + target_read_u8(target, s3c24xx_info->nfstat, &status); + + if (status & S3C2440_NFSTAT_READY) + return 1; + + usleep(1000); + } while (timeout-- > 0); + + + return 0; +} + +/* use the fact we can read/write 4 bytes in one go via a single 32bit op */ + +int s3c2440_read_block_data(struct nand_device_s *device, u8 *data, int data_size) +{ + s3c24xx_nand_controller_t *s3c24xx_info = device->controller_priv; + target_t *target = s3c24xx_info->target; + u32 nfdata = s3c24xx_info->data; + u32 tmp; + + INFO("%s: reading data: %p, %p, %d\n", __func__, device, data, data_size); + + if (target->state != TARGET_HALTED) { + ERROR("target must be halted to use S3C24XX NAND flash controller"); + return ERROR_NAND_OPERATION_FAILED; + } + + while (data_size >= 4) { + target_read_u32(target, nfdata, &tmp); + + data[0] = tmp; + data[1] = tmp >> 8; + data[2] = tmp >> 16; + data[3] = tmp >> 24; + + data_size -= 4; + data += 4; + } + + while (data_size > 0) { + target_read_u8(target, nfdata, data); + + data_size -= 1; + data += 1; + } + + return ERROR_OK; +} + +int s3c2440_write_block_data(struct nand_device_s *device, u8 *data, int data_size) +{ + s3c24xx_nand_controller_t *s3c24xx_info = device->controller_priv; + target_t *target = s3c24xx_info->target; + u32 nfdata = s3c24xx_info->data; + u32 tmp; + + if (target->state != TARGET_HALTED) { + ERROR("target must be halted to use S3C24XX NAND flash controller"); + return ERROR_NAND_OPERATION_FAILED; + } + + while (data_size >= 4) { + tmp = le_to_h_u32(data); + target_write_u32(target, nfdata, tmp); + + data_size -= 4; + data += 4; + } + + while (data_size > 0) { + target_write_u8(target, nfdata, *data); + + data_size -= 1; + data += 1; + } + + return ERROR_OK; +} diff --git a/src/flash/str9xpec.c b/src/flash/str9xpec.c index 9df57dd5..ea7aa97f 100644 --- a/src/flash/str9xpec.c +++ b/src/flash/str9xpec.c @@ -1,1348 +1,1348 @@ -/*************************************************************************** - * Copyright (C) 2005 by Dominic Rath * - * Dominic.Rath@gmx.de * - * * - * This program is free software; you can redistribute it and/or modify * - * it under the terms of the GNU General Public License as published by * - * the Free Software Foundation; either version 2 of the License, or * - * (at your option) any later version. * - * * - * This program is distributed in the hope that it will be useful, * - * but WITHOUT ANY WARRANTY; without even the implied warranty of * - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * - * GNU General Public License for more details. * - * * - * You should have received a copy of the GNU General Public License * - * along with this program; if not, write to the * - * Free Software Foundation, Inc., * - * 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. * - ***************************************************************************/ -#ifdef HAVE_CONFIG_H -#include "config.h" -#endif - -#include "replacements.h" - -#include "str9xpec.h" -#include "flash.h" -#include "target.h" -#include "log.h" -#include "armv4_5.h" -#include "arm7_9_common.h" -#include "jtag.h" -#include "binarybuffer.h" - -#include -#include -#include -#include - -str9xpec_mem_layout_t mem_layout_str9pec[] = { - {0x00000000, 0x10000, 0}, - {0x00010000, 0x10000, 1}, - {0x00020000, 0x10000, 2}, - {0x00030000, 0x10000, 3}, - {0x00040000, 0x10000, 4}, - {0x00050000, 0x10000, 5}, - {0x00060000, 0x10000, 6}, - {0x00070000, 0x10000, 7}, - {0x00080000, 0x02000, 32}, - {0x00082000, 0x02000, 33}, - {0x00084000, 0x02000, 34}, - {0x00086000, 0x02000, 35} -}; - -int str9xpec_register_commands(struct command_context_s *cmd_ctx); -int str9xpec_flash_bank_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc, struct flash_bank_s *bank); -int str9xpec_erase(struct flash_bank_s *bank, int first, int last); -int str9xpec_protect(struct flash_bank_s *bank, int set, int first, int last); -int str9xpec_write(struct flash_bank_s *bank, u8 *buffer, u32 offset, u32 count); -int str9xpec_probe(struct flash_bank_s *bank); -int str9xpec_handle_part_id_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc); -int str9xpec_protect_check(struct flash_bank_s *bank); -int str9xpec_erase_check(struct flash_bank_s *bank); -int str9xpec_info(struct flash_bank_s *bank, char *buf, int buf_size); - -int str9xpec_erase_area(struct flash_bank_s *bank, int first, int last); -int str9xpec_set_address(struct flash_bank_s *bank, u8 sector); -int str9xpec_write_options(struct flash_bank_s *bank); - -int str9xpec_handle_flash_options_cmap_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc); -int str9xpec_handle_flash_options_lvdthd_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc); -int str9xpec_handle_flash_options_lvdsel_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc); -int str9xpec_handle_flash_options_lvdwarn_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc); -int str9xpec_handle_flash_options_read_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc); -int str9xpec_handle_flash_options_write_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc); -int str9xpec_handle_flash_lock_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc); -int str9xpec_handle_flash_unlock_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc); -int str9xpec_handle_flash_enable_turbo_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc); -int str9xpec_handle_flash_disable_turbo_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc); - -flash_driver_t str9xpec_flash = -{ - .name = "str9xpec", - .register_commands = str9xpec_register_commands, - .flash_bank_command = str9xpec_flash_bank_command, - .erase = str9xpec_erase, - .protect = str9xpec_protect, - .write = str9xpec_write, - .probe = str9xpec_probe, - .auto_probe = str9xpec_probe, - .erase_check = str9xpec_erase_check, - .protect_check = str9xpec_protect_check, - .info = str9xpec_info -}; - -int str9xpec_register_commands(struct command_context_s *cmd_ctx) -{ - command_t *str9xpec_cmd = register_command(cmd_ctx, NULL, "str9xpec", NULL, COMMAND_ANY, "str9xpec flash specific commands"); - - register_command(cmd_ctx, str9xpec_cmd, "enable_turbo", str9xpec_handle_flash_enable_turbo_command, COMMAND_EXEC, - "enable str9xpec turbo mode"); - register_command(cmd_ctx, str9xpec_cmd, "disable_turbo", str9xpec_handle_flash_disable_turbo_command, COMMAND_EXEC, - "disable str9xpec turbo mode"); - register_command(cmd_ctx, str9xpec_cmd, "options_cmap", str9xpec_handle_flash_options_cmap_command, COMMAND_EXEC, - "configure str9xpec boot sector"); - register_command(cmd_ctx, str9xpec_cmd, "options_lvdthd", str9xpec_handle_flash_options_lvdthd_command, COMMAND_EXEC, - "configure str9xpec lvd threshold"); - register_command(cmd_ctx, str9xpec_cmd, "options_lvdsel", str9xpec_handle_flash_options_lvdsel_command, COMMAND_EXEC, - "configure str9xpec lvd selection"); - register_command(cmd_ctx, str9xpec_cmd, "options_lvdwarn", str9xpec_handle_flash_options_lvdwarn_command, COMMAND_EXEC, - "configure str9xpec lvd warning"); - register_command(cmd_ctx, str9xpec_cmd, "options_read", str9xpec_handle_flash_options_read_command, COMMAND_EXEC, - "read str9xpec options"); - register_command(cmd_ctx, str9xpec_cmd, "options_write", str9xpec_handle_flash_options_write_command, COMMAND_EXEC, - "write str9xpec options"); - register_command(cmd_ctx, str9xpec_cmd, "lock", str9xpec_handle_flash_lock_command, COMMAND_EXEC, - "lock str9xpec device"); - register_command(cmd_ctx, str9xpec_cmd, "unlock", str9xpec_handle_flash_unlock_command, COMMAND_EXEC, - "unlock str9xpec device"); - register_command(cmd_ctx, str9xpec_cmd, "part_id", str9xpec_handle_part_id_command, COMMAND_EXEC, - "print part id of str9xpec flash bank "); - - return ERROR_OK; -} - -int str9xpec_set_instr(int chain_pos, u32 new_instr, enum tap_state end_state) -{ - jtag_device_t *device = jtag_get_device(chain_pos); - - if (device == NULL) - { - DEBUG("Invalid Target"); - return ERROR_TARGET_INVALID; - } - - if (buf_get_u32(device->cur_instr, 0, device->ir_length) != new_instr) - { - scan_field_t field; - - field.device = chain_pos; - field.num_bits = device->ir_length; - field.out_value = calloc(CEIL(field.num_bits, 8), 1); - buf_set_u32(field.out_value, 0, field.num_bits, new_instr); - field.out_mask = NULL; - field.in_value = NULL; - field.in_check_value = NULL; - field.in_check_mask = NULL; - field.in_handler = NULL; - field.in_handler_priv = NULL; - - jtag_add_ir_scan(1, &field, end_state); - - free(field.out_value); - } - - return ERROR_OK; -} - -u8 str9xpec_isc_status(int chain_pos) -{ - scan_field_t field; - u8 status; - - if (str9xpec_set_instr(chain_pos, ISC_NOOP, TAP_PI) != ERROR_OK) - return ISC_STATUS_ERROR; - - field.device = chain_pos; - field.num_bits = 8; - field.out_value = NULL; - field.out_mask = NULL; - field.in_value = &status; - field.in_check_value = NULL; - field.in_check_mask = NULL; - field.in_handler = NULL; - field.in_handler_priv = NULL; - - jtag_add_dr_scan(1, &field, TAP_RTI); - jtag_execute_queue(); - - DEBUG("status: 0x%2.2x", status); - - if (status & ISC_STATUS_SECURITY) - INFO("Device Security Bit Set"); - - return status; -} - -int str9xpec_isc_enable(struct flash_bank_s *bank) -{ - u8 status; - u32 chain_pos; - str9xpec_flash_controller_t *str9xpec_info = bank->driver_priv; - - chain_pos = str9xpec_info->chain_pos; - - if (str9xpec_info->isc_enable) - return ERROR_OK; - - /* enter isc mode */ - if (str9xpec_set_instr(chain_pos, ISC_ENABLE, TAP_RTI) != ERROR_OK) - return ERROR_TARGET_INVALID; - - /* check ISC status */ - status = str9xpec_isc_status(chain_pos); - if (status & ISC_STATUS_MODE) - { - /* we have entered isc mode */ - str9xpec_info->isc_enable = 1; - DEBUG("ISC_MODE Enabled"); - } - - return ERROR_OK; -} - -int str9xpec_isc_disable(struct flash_bank_s *bank) -{ - u8 status; - u32 chain_pos; - str9xpec_flash_controller_t *str9xpec_info = bank->driver_priv; - - chain_pos = str9xpec_info->chain_pos; - - if (!str9xpec_info->isc_enable) - return ERROR_OK; - - if (str9xpec_set_instr(chain_pos, ISC_DISABLE, TAP_RTI) != ERROR_OK) - return ERROR_TARGET_INVALID; - - /* delay to handle aborts */ - jtag_add_sleep(50); - - /* check ISC status */ - status = str9xpec_isc_status(chain_pos); - if (!(status & ISC_STATUS_MODE)) - { - /* we have left isc mode */ - str9xpec_info->isc_enable = 0; - DEBUG("ISC_MODE Disabled"); - } - - return ERROR_OK; -} - -int str9xpec_read_config(struct flash_bank_s *bank) -{ - scan_field_t field; - u8 status; - u32 chain_pos; - - str9xpec_flash_controller_t *str9xpec_info = bank->driver_priv; - - chain_pos = str9xpec_info->chain_pos; - - DEBUG("ISC_CONFIGURATION"); - - /* execute ISC_CONFIGURATION command */ - str9xpec_set_instr(chain_pos, ISC_CONFIGURATION, TAP_PI); - - field.device = chain_pos; - field.num_bits = 64; - field.out_value = NULL; - field.out_mask = NULL; - field.in_value = str9xpec_info->options; - field.in_check_value = NULL; - field.in_check_mask = NULL; - field.in_handler = NULL; - field.in_handler_priv = NULL; - - jtag_add_dr_scan(1, &field, TAP_RTI); - jtag_execute_queue(); - - status = str9xpec_isc_status(chain_pos); - - return status; -} - -int str9xpec_build_block_list(struct flash_bank_s *bank) -{ - str9xpec_flash_controller_t *str9xpec_info = bank->driver_priv; - - int i; - int num_sectors = 0, b0_sectors = 0; - - switch (bank->size) - { - case (256 * 1024): - b0_sectors = 4; - break; - case (512 * 1024): - b0_sectors = 8; - break; - default: - ERROR("BUG: unknown bank->size encountered"); - exit(-1); - } - - /* include bank 1 sectors */ - num_sectors = b0_sectors + 4; - bank->size += (32 * 1024); - - bank->num_sectors = num_sectors; - bank->sectors = malloc(sizeof(flash_sector_t) * num_sectors); - str9xpec_info->sector_bits = malloc(sizeof(u32) * num_sectors); - - num_sectors = 0; - - for (i = 0; i < b0_sectors; i++) - { - bank->sectors[num_sectors].offset = mem_layout_str9pec[i].sector_start; - bank->sectors[num_sectors].size = mem_layout_str9pec[i].sector_size; - bank->sectors[num_sectors].is_erased = -1; - bank->sectors[num_sectors].is_protected = 1; - str9xpec_info->sector_bits[num_sectors++] = mem_layout_str9pec[i].sector_bit; - } - - for (i = 8; i < 12; i++) - { - bank->sectors[num_sectors].offset = mem_layout_str9pec[i].sector_start; - bank->sectors[num_sectors].size = mem_layout_str9pec[i].sector_size; - bank->sectors[num_sectors].is_erased = -1; - bank->sectors[num_sectors].is_protected = 1; - str9xpec_info->sector_bits[num_sectors++] = mem_layout_str9pec[i].sector_bit; - } - - return ERROR_OK; -} - -/* flash bank str9x 0 0 - */ -int str9xpec_flash_bank_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc, struct flash_bank_s *bank) -{ - str9xpec_flash_controller_t *str9xpec_info; - armv4_5_common_t *armv4_5 = NULL; - arm7_9_common_t *arm7_9 = NULL; - arm_jtag_t *jtag_info = NULL; - - if (argc < 6) - { - WARNING("incomplete flash_bank str9x configuration"); - return ERROR_FLASH_BANK_INVALID; - } - - str9xpec_info = malloc(sizeof(str9xpec_flash_controller_t)); - bank->driver_priv = str9xpec_info; - - if (bank->base != 0x00000000) - { - WARNING("overriding flash base address for STR91x device with 0x00000000"); - bank->base = 0x00000000; - } - - /* find out jtag position of flash controller - * it is always after the arm966 core */ - - armv4_5 = bank->target->arch_info; - arm7_9 = armv4_5->arch_info; - jtag_info = &arm7_9->jtag_info; - - str9xpec_info->chain_pos = (jtag_info->chain_pos - 1); - str9xpec_info->isc_enable = 0; - str9xpec_info->devarm = NULL; - - str9xpec_build_block_list(bank); - - /* clear option byte register */ - buf_set_u32(str9xpec_info->options, 0, 64, 0); - - return ERROR_OK; -} - -int str9xpec_blank_check(struct flash_bank_s *bank, int first, int last) -{ - scan_field_t field; - u8 status; - u32 chain_pos; - int i; - u8 *buffer = NULL; - - str9xpec_flash_controller_t *str9xpec_info = bank->driver_priv; - - chain_pos = str9xpec_info->chain_pos; - - if (!str9xpec_info->isc_enable) { - str9xpec_isc_enable( bank ); - } - - if (!str9xpec_info->isc_enable) { - return ERROR_FLASH_OPERATION_FAILED; - } - - buffer = calloc(CEIL(64, 8), 1); - - DEBUG("blank check: first_bank: %i, last_bank: %i", first, last); - - for (i = first; i <= last; i++) { - buf_set_u32(buffer, str9xpec_info->sector_bits[i], 1, 1); - } - - /* execute ISC_BLANK_CHECK command */ - str9xpec_set_instr(chain_pos, ISC_BLANK_CHECK, TAP_PI); - - field.device = chain_pos; - field.num_bits = 64; - field.out_value = buffer; - field.out_mask = NULL; - field.in_value = NULL; - field.in_check_value = NULL; - field.in_check_mask = NULL; - field.in_handler = NULL; - field.in_handler_priv = NULL; - - jtag_add_dr_scan(1, &field, TAP_RTI); - jtag_add_sleep(40000); - - /* read blank check result */ - field.device = chain_pos; - field.num_bits = 64; - field.out_value = NULL; - field.out_mask = NULL; - field.in_value = buffer; - field.in_check_value = NULL; - field.in_check_mask = NULL; - field.in_handler = NULL; - field.in_handler_priv = NULL; - - jtag_add_dr_scan(1, &field, TAP_PI); - jtag_execute_queue(); - - status = str9xpec_isc_status(chain_pos); - - for (i = first; i <= last; i++) - { - if (buf_get_u32(buffer, str9xpec_info->sector_bits[i], 1)) - bank->sectors[i].is_erased = 0; - else - bank->sectors[i].is_erased = 1; - } - - free(buffer); - - str9xpec_isc_disable(bank); - - if ((status & ISC_STATUS_ERROR) != STR9XPEC_ISC_SUCCESS) - return ERROR_FLASH_OPERATION_FAILED; - return ERROR_OK; -} - -int str9xpec_protect_check(struct flash_bank_s *bank) -{ - u8 status; - int i; - - str9xpec_flash_controller_t *str9xpec_info = bank->driver_priv; - - status = str9xpec_read_config(bank); - - for (i = 0; i < bank->num_sectors; i++) - { - if (buf_get_u32(str9xpec_info->options, str9xpec_info->sector_bits[i], 1)) - bank->sectors[i].is_protected = 1; - else - bank->sectors[i].is_protected = 0; - } - - if ((status & ISC_STATUS_ERROR) != STR9XPEC_ISC_SUCCESS) - return ERROR_FLASH_OPERATION_FAILED; - return ERROR_OK; -} - -int str9xpec_erase_area(struct flash_bank_s *bank, int first, int last) -{ - scan_field_t field; - u8 status; - u32 chain_pos; - int i; - u8 *buffer = NULL; - - str9xpec_flash_controller_t *str9xpec_info = bank->driver_priv; - - chain_pos = str9xpec_info->chain_pos; - - if (!str9xpec_info->isc_enable) { - str9xpec_isc_enable( bank ); - } - - if (!str9xpec_info->isc_enable) { - return ISC_STATUS_ERROR; - } - - buffer = calloc(CEIL(64, 8), 1); - - DEBUG("erase: first_bank: %i, last_bank: %i", first, last); - - /* last bank: 0xFF signals a full erase (unlock complete device) */ - /* last bank: 0xFE signals a option byte erase */ - if (last == 0xFF) - { - for (i = 0; i < 64; i++) { - buf_set_u32(buffer, i, 1, 1); - } - } - else if (last == 0xFE) - { - buf_set_u32(buffer, 49, 1, 1); - } - else - { - for (i = first; i <= last; i++) { - buf_set_u32(buffer, str9xpec_info->sector_bits[i], 1, 1); - } - } - - DEBUG("ISC_ERASE"); - - /* execute ISC_ERASE command */ - str9xpec_set_instr(chain_pos, ISC_ERASE, TAP_PI); - - field.device = chain_pos; - field.num_bits = 64; - field.out_value = buffer; - field.out_mask = NULL; - field.in_value = NULL; - field.in_check_value = NULL; - field.in_check_mask = NULL; - field.in_handler = NULL; - field.in_handler_priv = NULL; - - jtag_add_dr_scan(1, &field, TAP_RTI); - jtag_execute_queue(); - - jtag_add_sleep(10); - - /* wait for erase completion */ - while (!((status = str9xpec_isc_status(chain_pos)) & ISC_STATUS_BUSY)) { - usleep(1000); - } - - free(buffer); - - str9xpec_isc_disable(bank); - - return status; -} - -int str9xpec_erase(struct flash_bank_s *bank, int first, int last) -{ - int status; - - status = str9xpec_erase_area(bank, first, last); - - if ((status & ISC_STATUS_ERROR) != STR9XPEC_ISC_SUCCESS) - return ERROR_FLASH_OPERATION_FAILED; - - return ERROR_OK; -} - -int str9xpec_lock_device(struct flash_bank_s *bank) -{ - scan_field_t field; - u8 status; - u32 chain_pos; - str9xpec_flash_controller_t *str9xpec_info = NULL; - - str9xpec_info = bank->driver_priv; - chain_pos = str9xpec_info->chain_pos; - - if (!str9xpec_info->isc_enable) { - str9xpec_isc_enable( bank ); - } - - if (!str9xpec_info->isc_enable) { - return ISC_STATUS_ERROR; - } - - /* set security address */ - str9xpec_set_address(bank, 0x80); - - /* execute ISC_PROGRAM command */ - str9xpec_set_instr(chain_pos, ISC_PROGRAM_SECURITY, TAP_RTI); - - str9xpec_set_instr(chain_pos, ISC_NOOP, TAP_PI); - - do { - field.device = chain_pos; - field.num_bits = 8; - field.out_value = NULL; - field.out_mask = NULL; - field.in_value = &status; - field.in_check_value = NULL; - field.in_check_mask = NULL; - field.in_handler = NULL; - field.in_handler_priv = NULL; - - jtag_add_dr_scan(1, &field, -1); - jtag_execute_queue(); - - } while(!(status & ISC_STATUS_BUSY)); - - str9xpec_isc_disable(bank); - - return status; -} - -int str9xpec_unlock_device(struct flash_bank_s *bank) -{ - u8 status; - - status = str9xpec_erase_area(bank, 0, 255); - - return status; -} - -int str9xpec_protect(struct flash_bank_s *bank, int set, int first, int last) -{ - u8 status; - int i; - - str9xpec_flash_controller_t *str9xpec_info = bank->driver_priv; - - status = str9xpec_read_config(bank); - - if ((status & ISC_STATUS_ERROR) != STR9XPEC_ISC_SUCCESS) - return ERROR_FLASH_OPERATION_FAILED; - - DEBUG("protect: first_bank: %i, last_bank: %i", first, last); - - /* last bank: 0xFF signals a full device protect */ - if (last == 0xFF) - { - if( set ) - { - status = str9xpec_lock_device(bank); - } - else - { - /* perform full erase to unlock device */ - status = str9xpec_unlock_device(bank); - } - } - else - { - for (i = first; i <= last; i++) - { - if( set ) - buf_set_u32(str9xpec_info->options, str9xpec_info->sector_bits[i], 1, 1); - else - buf_set_u32(str9xpec_info->options, str9xpec_info->sector_bits[i], 1, 0); - } - - status = str9xpec_write_options(bank); - } - - if ((status & ISC_STATUS_ERROR) != STR9XPEC_ISC_SUCCESS) - return ERROR_FLASH_OPERATION_FAILED; - - return ERROR_OK; -} - -int str9xpec_set_address(struct flash_bank_s *bank, u8 sector) -{ - u32 chain_pos; - scan_field_t field; - str9xpec_flash_controller_t *str9xpec_info = bank->driver_priv; - - chain_pos = str9xpec_info->chain_pos; - - /* set flash controller address */ - str9xpec_set_instr(chain_pos, ISC_ADDRESS_SHIFT, TAP_PI); - - field.device = chain_pos; - field.num_bits = 8; - field.out_value = §or; - field.out_mask = NULL; - field.in_value = NULL; - field.in_check_value = NULL; - field.in_check_mask = NULL; - field.in_handler = NULL; - field.in_handler_priv = NULL; - - jtag_add_dr_scan(1, &field, -1); - - return ERROR_OK; -} - -int str9xpec_write(struct flash_bank_s *bank, u8 *buffer, u32 offset, u32 count) -{ - str9xpec_flash_controller_t *str9xpec_info = bank->driver_priv; - u32 dwords_remaining = (count / 8); - u32 bytes_remaining = (count & 0x00000007); - u32 bytes_written = 0; - u8 status; - u32 check_address = offset; - u32 chain_pos; - scan_field_t field; - u8 *scanbuf; - int i; - u32 first_sector = 0; - u32 last_sector = 0; - - chain_pos = str9xpec_info->chain_pos; - - if (!str9xpec_info->isc_enable) { - str9xpec_isc_enable(bank); - } - - if (!str9xpec_info->isc_enable) { - return ERROR_FLASH_OPERATION_FAILED; - } - - if (offset & 0x7) - { - WARNING("offset 0x%x breaks required 8-byte alignment", offset); - return ERROR_FLASH_DST_BREAKS_ALIGNMENT; - } - - for (i = 0; i < bank->num_sectors; i++) - { - u32 sec_start = bank->sectors[i].offset; - u32 sec_end = sec_start + bank->sectors[i].size; - - /* check if destination falls within the current sector */ - if ((check_address >= sec_start) && (check_address < sec_end)) - { - /* check if destination ends in the current sector */ - if (offset + count < sec_end) - check_address = offset + count; - else - check_address = sec_end; - } - - if ((offset >= sec_start) && (offset < sec_end)){ - first_sector = i; - } - - if ((offset + count >= sec_start) && (offset + count < sec_end)){ - last_sector = i; - } - } - - if (check_address != offset + count) - return ERROR_FLASH_DST_OUT_OF_BANK; - - DEBUG("first_sector: %i, last_sector: %i", first_sector, last_sector); - - scanbuf = calloc(CEIL(64, 8), 1); - - DEBUG("ISC_PROGRAM"); - - for (i = first_sector; i <= last_sector; i++) - { - str9xpec_set_address(bank, str9xpec_info->sector_bits[i]); - - dwords_remaining = dwords_remaining < (bank->sectors[i].size/8) ? dwords_remaining : (bank->sectors[i].size/8); - - while (dwords_remaining > 0) - { - str9xpec_set_instr(chain_pos, ISC_PROGRAM, TAP_PI); - - field.device = chain_pos; - field.num_bits = 64; - field.out_value = (buffer + bytes_written); - field.out_mask = NULL; - field.in_value = NULL; - field.in_check_value = NULL; - field.in_check_mask = NULL; - field.in_handler = NULL; - field.in_handler_priv = NULL; - - jtag_add_dr_scan(1, &field, TAP_RTI); - - /* small delay before polling */ - jtag_add_sleep(50); - - str9xpec_set_instr(chain_pos, ISC_NOOP, TAP_PI); - - do { - field.device = chain_pos; - field.num_bits = 8; - field.out_value = NULL; - field.out_mask = NULL; - field.in_value = scanbuf; - field.in_check_value = NULL; - field.in_check_mask = NULL; - field.in_handler = NULL; - field.in_handler_priv = NULL; - - jtag_add_dr_scan(1, &field, -1); - jtag_execute_queue(); - - status = buf_get_u32(scanbuf, 0, 8); - - } while(!(status & ISC_STATUS_BUSY)); - - if ((status & ISC_STATUS_ERROR) != STR9XPEC_ISC_SUCCESS) - return ERROR_FLASH_OPERATION_FAILED; - - //if ((status & ISC_STATUS_INT_ERROR) != STR9XPEC_ISC_INTFAIL) - // return ERROR_FLASH_OPERATION_FAILED; - - dwords_remaining--; - bytes_written += 8; - } - } - - if (bytes_remaining) - { - u8 last_dword[8] = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff}; - int i = 0; - - while(bytes_remaining > 0) - { - last_dword[i++] = *(buffer + bytes_written); - bytes_remaining--; - bytes_written++; - } - - str9xpec_set_instr(chain_pos, ISC_PROGRAM, TAP_PI); - - field.device = chain_pos; - field.num_bits = 64; - field.out_value = last_dword; - field.out_mask = NULL; - field.in_value = NULL; - field.in_check_value = NULL; - field.in_check_mask = NULL; - field.in_handler = NULL; - field.in_handler_priv = NULL; - - jtag_add_dr_scan(1, &field, TAP_RTI); - - /* small delay before polling */ - jtag_add_sleep(50); - - str9xpec_set_instr(chain_pos, ISC_NOOP, TAP_PI); - - do { - field.device = chain_pos; - field.num_bits = 8; - field.out_value = NULL; - field.out_mask = NULL; - field.in_value = scanbuf; - field.in_check_value = NULL; - field.in_check_mask = NULL; - field.in_handler = NULL; - field.in_handler_priv = NULL; - - jtag_add_dr_scan(1, &field, -1); - jtag_execute_queue(); - - status = buf_get_u32(scanbuf, 0, 8); - - } while(!(status & ISC_STATUS_BUSY)); - - if ((status & ISC_STATUS_ERROR) != STR9XPEC_ISC_SUCCESS) - return ERROR_FLASH_OPERATION_FAILED; - - //if ((status & ISC_STATUS_INT_ERROR) != STR9XPEC_ISC_INTFAIL) - // return ERROR_FLASH_OPERATION_FAILED; - } - - free(scanbuf); - - str9xpec_isc_disable(bank); - - return ERROR_OK; -} - -int str9xpec_probe(struct flash_bank_s *bank) -{ - return ERROR_OK; -} - -int str9xpec_handle_part_id_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc) -{ - flash_bank_t *bank; - scan_field_t field; - u8 *buffer = NULL; - u32 chain_pos; - u32 idcode; - str9xpec_flash_controller_t *str9xpec_info = NULL; - - if (argc < 1) - { - return ERROR_COMMAND_SYNTAX_ERROR; - } - - bank = get_flash_bank_by_num(strtoul(args[0], NULL, 0)); - if (!bank) - { - command_print(cmd_ctx, "flash bank '#%s' is out of bounds", args[0]); - return ERROR_OK; - } - - str9xpec_info = bank->driver_priv; - chain_pos = str9xpec_info->chain_pos; - - buffer = calloc(CEIL(32, 8), 1); - - str9xpec_set_instr(chain_pos, ISC_IDCODE, TAP_PI); - - field.device = chain_pos; - field.num_bits = 32; - field.out_value = NULL; - field.out_mask = NULL; - field.in_value = buffer; - field.in_check_value = NULL; - field.in_check_mask = NULL; - field.in_handler = NULL; - field.in_handler_priv = NULL; - - jtag_add_dr_scan(1, &field, TAP_RTI); - jtag_execute_queue(); - - idcode = buf_get_u32(buffer, 0, 32); - - command_print(cmd_ctx, "str9xpec part id: 0x%8.8x", idcode); - - free(buffer); - - return ERROR_OK; -} - -int str9xpec_erase_check(struct flash_bank_s *bank) -{ - return str9xpec_blank_check(bank, 0, bank->num_sectors - 1); -} - -int str9xpec_info(struct flash_bank_s *bank, char *buf, int buf_size) -{ - snprintf(buf, buf_size, "str9xpec flash driver info" ); - return ERROR_OK; -} - -int str9xpec_handle_flash_options_read_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc) -{ - flash_bank_t *bank; - u8 status; - str9xpec_flash_controller_t *str9xpec_info = NULL; - - if (argc < 1) - { - command_print(cmd_ctx, "str9xpec options_read "); - return ERROR_OK; - } - - bank = get_flash_bank_by_num(strtoul(args[0], NULL, 0)); - if (!bank) - { - command_print(cmd_ctx, "flash bank '#%s' is out of bounds", args[0]); - return ERROR_OK; - } - - str9xpec_info = bank->driver_priv; - - status = str9xpec_read_config(bank); - - if ((status & ISC_STATUS_ERROR) != STR9XPEC_ISC_SUCCESS) - return ERROR_FLASH_OPERATION_FAILED; - - /* boot bank */ - if (buf_get_u32(str9xpec_info->options, STR9XPEC_OPT_CSMAPBIT, 1)) - command_print(cmd_ctx, "CS Map: bank1"); - else - command_print(cmd_ctx, "CS Map: bank0"); - - /* OTP lock */ - if (buf_get_u32(str9xpec_info->options, STR9XPEC_OPT_OTPBIT, 1)) - command_print(cmd_ctx, "OTP Lock: OTP Locked"); - else - command_print(cmd_ctx, "OTP Lock: OTP Unlocked"); - - /* LVD Threshold */ - if (buf_get_u32(str9xpec_info->options, STR9XPEC_OPT_LVDTHRESBIT, 1)) - command_print(cmd_ctx, "LVD Threshold: 2.7v"); - else - command_print(cmd_ctx, "LVD Threshold: 2.4v"); - - /* LVD reset warning */ - if (buf_get_u32(str9xpec_info->options, STR9XPEC_OPT_LVDWARNBIT, 1)) - command_print(cmd_ctx, "LVD Reset Warning: VDD or VDDQ Inputs"); - else - command_print(cmd_ctx, "LVD Reset Warning: VDD Input Only"); - - /* LVD reset select */ - if (buf_get_u32(str9xpec_info->options, STR9XPEC_OPT_LVDSELBIT, 1)) - command_print(cmd_ctx, "LVD Reset Selection: VDD or VDDQ Inputs"); - else - command_print(cmd_ctx, "LVD Reset Selection: VDD Input Only"); - - return ERROR_OK; -} - -int str9xpec_write_options(struct flash_bank_s *bank) -{ - scan_field_t field; - u8 status; - u32 chain_pos; - str9xpec_flash_controller_t *str9xpec_info = NULL; - - str9xpec_info = bank->driver_priv; - chain_pos = str9xpec_info->chain_pos; - - /* erase config options first */ - status = str9xpec_erase_area( bank, 0xFE, 0xFE ); - - if ((status & ISC_STATUS_ERROR) != STR9XPEC_ISC_SUCCESS) - return status; - - if (!str9xpec_info->isc_enable) { - str9xpec_isc_enable( bank ); - } - - if (!str9xpec_info->isc_enable) { - return ISC_STATUS_ERROR; - } - - /* according to data 64th bit has to be set */ - buf_set_u32(str9xpec_info->options, 63, 1, 1); - - /* set option byte address */ - str9xpec_set_address(bank, 0x50); - - /* execute ISC_PROGRAM command */ - str9xpec_set_instr(chain_pos, ISC_PROGRAM, TAP_PI); - - field.device = chain_pos; - field.num_bits = 64; - field.out_value = str9xpec_info->options; - field.out_mask = NULL; - field.in_value = NULL; - field.in_check_value = NULL; - field.in_check_mask = NULL; - field.in_handler = NULL; - field.in_handler_priv = NULL; - - jtag_add_dr_scan(1, &field, TAP_RTI); - - /* small delay before polling */ - jtag_add_sleep(50); - - str9xpec_set_instr(chain_pos, ISC_NOOP, TAP_PI); - - do { - field.device = chain_pos; - field.num_bits = 8; - field.out_value = NULL; - field.out_mask = NULL; - field.in_value = &status; - field.in_check_value = NULL; - field.in_check_mask = NULL; - field.in_handler = NULL; - field.in_handler_priv = NULL; - - jtag_add_dr_scan(1, &field, -1); - jtag_execute_queue(); - - } while(!(status & ISC_STATUS_BUSY)); - - str9xpec_isc_disable(bank); - - return status; -} - -int str9xpec_handle_flash_options_write_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc) -{ - flash_bank_t *bank; - u8 status; - - if (argc < 1) - { - command_print(cmd_ctx, "str9xpec options_write "); - return ERROR_OK; - } - - bank = get_flash_bank_by_num(strtoul(args[0], NULL, 0)); - if (!bank) - { - command_print(cmd_ctx, "flash bank '#%s' is out of bounds", args[0]); - return ERROR_OK; - } - - status = str9xpec_write_options(bank); - - if ((status & ISC_STATUS_ERROR) != STR9XPEC_ISC_SUCCESS) - return ERROR_FLASH_OPERATION_FAILED; - - return ERROR_OK; -} - -int str9xpec_handle_flash_options_cmap_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc) -{ - flash_bank_t *bank; - str9xpec_flash_controller_t *str9xpec_info = NULL; - - if (argc < 2) - { - command_print(cmd_ctx, "str9xpec options_cmap "); - return ERROR_OK; - } - - bank = get_flash_bank_by_num(strtoul(args[0], NULL, 0)); - if (!bank) - { - command_print(cmd_ctx, "flash bank '#%s' is out of bounds", args[0]); - return ERROR_OK; - } - - str9xpec_info = bank->driver_priv; - - if (strcmp(args[1], "bank1") == 0) - { - buf_set_u32(str9xpec_info->options, STR9XPEC_OPT_CSMAPBIT, 1, 1); - } - else - { - buf_set_u32(str9xpec_info->options, STR9XPEC_OPT_CSMAPBIT, 1, 0); - } - - return ERROR_OK; -} - -int str9xpec_handle_flash_options_lvdthd_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc) -{ - flash_bank_t *bank; - str9xpec_flash_controller_t *str9xpec_info = NULL; - - if (argc < 2) - { - command_print(cmd_ctx, "str9xpec options_lvdthd <2.4v|2.7v>"); - return ERROR_OK; - } - - bank = get_flash_bank_by_num(strtoul(args[0], NULL, 0)); - if (!bank) - { - command_print(cmd_ctx, "flash bank '#%s' is out of bounds", args[0]); - return ERROR_OK; - } - - str9xpec_info = bank->driver_priv; - - if (strcmp(args[1], "2.7v") == 0) - { - buf_set_u32(str9xpec_info->options, STR9XPEC_OPT_LVDTHRESBIT, 1, 1); - } - else - { - buf_set_u32(str9xpec_info->options, STR9XPEC_OPT_LVDTHRESBIT, 1, 0); - } - - return ERROR_OK; -} - -int str9xpec_handle_flash_options_lvdsel_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc) -{ - flash_bank_t *bank; - str9xpec_flash_controller_t *str9xpec_info = NULL; - - if (argc < 2) - { - command_print(cmd_ctx, "str9xpec options_lvdsel "); - return ERROR_OK; - } - - bank = get_flash_bank_by_num(strtoul(args[0], NULL, 0)); - if (!bank) - { - command_print(cmd_ctx, "flash bank '#%s' is out of bounds", args[0]); - return ERROR_OK; - } - - str9xpec_info = bank->driver_priv; - - if (strcmp(args[1], "vdd_vddq") == 0) - { - buf_set_u32(str9xpec_info->options, STR9XPEC_OPT_LVDSELBIT, 1, 1); - } - else - { - buf_set_u32(str9xpec_info->options, STR9XPEC_OPT_LVDSELBIT, 1, 0); - } - - return ERROR_OK; -} - -int str9xpec_handle_flash_options_lvdwarn_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc) -{ - flash_bank_t *bank; - str9xpec_flash_controller_t *str9xpec_info = NULL; - - if (argc < 2) - { - command_print(cmd_ctx, "str9xpec options_lvdwarn "); - return ERROR_OK; - } - - bank = get_flash_bank_by_num(strtoul(args[0], NULL, 0)); - if (!bank) - { - command_print(cmd_ctx, "flash bank '#%s' is out of bounds", args[0]); - return ERROR_OK; - } - - str9xpec_info = bank->driver_priv; - - if (strcmp(args[1], "vdd_vddq") == 0) - { - buf_set_u32(str9xpec_info->options, STR9XPEC_OPT_LVDWARNBIT, 1, 1); - } - else - { - buf_set_u32(str9xpec_info->options, STR9XPEC_OPT_LVDWARNBIT, 1, 0); - } - - return ERROR_OK; -} - -int str9xpec_handle_flash_lock_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc) -{ - u8 status; - flash_bank_t *bank; - - if (argc < 1) - { - command_print(cmd_ctx, "str9xpec lock "); - return ERROR_OK; - } - - bank = get_flash_bank_by_num(strtoul(args[0], NULL, 0)); - if (!bank) - { - command_print(cmd_ctx, "flash bank '#%s' is out of bounds", args[0]); - return ERROR_OK; - } - - status = str9xpec_lock_device(bank); - - if ((status & ISC_STATUS_ERROR) != STR9XPEC_ISC_SUCCESS) - return ERROR_FLASH_OPERATION_FAILED; - - return ERROR_OK; -} - -int str9xpec_handle_flash_unlock_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc) -{ - u8 status; - flash_bank_t *bank; - - if (argc < 1) - { - command_print(cmd_ctx, "str9xpec unlock "); - return ERROR_OK; - } - - bank = get_flash_bank_by_num(strtoul(args[0], NULL, 0)); - if (!bank) - { - command_print(cmd_ctx, "flash bank '#%s' is out of bounds", args[0]); - return ERROR_OK; - } - - status = str9xpec_unlock_device(bank); - - if ((status & ISC_STATUS_ERROR) != STR9XPEC_ISC_SUCCESS) - return ERROR_FLASH_OPERATION_FAILED; - - return ERROR_OK; -} - -int str9xpec_handle_flash_enable_turbo_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc) -{ - flash_bank_t *bank; - u32 chain_pos; - jtag_device_t* dev0; - jtag_device_t* dev2; - str9xpec_flash_controller_t *str9xpec_info = NULL; - - if (argc < 1) - { - command_print(cmd_ctx, "str9xpec enable_turbo "); - return ERROR_OK; - } - - bank = get_flash_bank_by_num(strtoul(args[0], NULL, 0)); - if (!bank) - { - command_print(cmd_ctx, "flash bank '#%s' is out of bounds", args[0]); - return ERROR_OK; - } - - str9xpec_info = bank->driver_priv; - - chain_pos = str9xpec_info->chain_pos; - - /* remove arm core from chain - enter turbo mode */ - - str9xpec_set_instr(chain_pos+2, 0xD, TAP_RTI); - jtag_execute_queue(); - - /* modify scan chain - str9 core has been removed */ - dev0 = jtag_get_device(chain_pos); - str9xpec_info->devarm = jtag_get_device(chain_pos+1); - dev2 = jtag_get_device(chain_pos+2); - dev0->next = dev2; - jtag_num_devices--; - - return ERROR_OK; -} - -int str9xpec_handle_flash_disable_turbo_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc) -{ - flash_bank_t *bank; - u32 chain_pos; - jtag_device_t* dev0; - str9xpec_flash_controller_t *str9xpec_info = NULL; - - if (argc < 1) - { - command_print(cmd_ctx, "str9xpec disable_turbo "); - return ERROR_OK; - } - - bank = get_flash_bank_by_num(strtoul(args[0], NULL, 0)); - if (!bank) - { - command_print(cmd_ctx, "flash bank '#%s' is out of bounds", args[0]); - return ERROR_OK; - } - - str9xpec_info = bank->driver_priv; - - chain_pos = str9xpec_info->chain_pos; - - dev0 = jtag_get_device(chain_pos); - - /* exit turbo mode via TLR */ - str9xpec_set_instr(chain_pos, ISC_NOOP, TAP_TLR); - jtag_execute_queue(); - - /* restore previous scan chain */ - if( str9xpec_info->devarm ) { - dev0->next = str9xpec_info->devarm; - jtag_num_devices++; - str9xpec_info->devarm = NULL; - } - - return ERROR_OK; -} +/*************************************************************************** + * Copyright (C) 2005 by Dominic Rath * + * Dominic.Rath@gmx.de * + * * + * This program is free software; you can redistribute it and/or modify * + * it under the terms of the GNU General Public License as published by * + * the Free Software Foundation; either version 2 of the License, or * + * (at your option) any later version. * + * * + * This program is distributed in the hope that it will be useful, * + * but WITHOUT ANY WARRANTY; without even the implied warranty of * + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * + * GNU General Public License for more details. * + * * + * You should have received a copy of the GNU General Public License * + * along with this program; if not, write to the * + * Free Software Foundation, Inc., * + * 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. * + ***************************************************************************/ +#ifdef HAVE_CONFIG_H +#include "config.h" +#endif + +#include "replacements.h" + +#include "str9xpec.h" +#include "flash.h" +#include "target.h" +#include "log.h" +#include "armv4_5.h" +#include "arm7_9_common.h" +#include "jtag.h" +#include "binarybuffer.h" + +#include +#include +#include +#include + +str9xpec_mem_layout_t mem_layout_str9pec[] = { + {0x00000000, 0x10000, 0}, + {0x00010000, 0x10000, 1}, + {0x00020000, 0x10000, 2}, + {0x00030000, 0x10000, 3}, + {0x00040000, 0x10000, 4}, + {0x00050000, 0x10000, 5}, + {0x00060000, 0x10000, 6}, + {0x00070000, 0x10000, 7}, + {0x00080000, 0x02000, 32}, + {0x00082000, 0x02000, 33}, + {0x00084000, 0x02000, 34}, + {0x00086000, 0x02000, 35} +}; + +int str9xpec_register_commands(struct command_context_s *cmd_ctx); +int str9xpec_flash_bank_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc, struct flash_bank_s *bank); +int str9xpec_erase(struct flash_bank_s *bank, int first, int last); +int str9xpec_protect(struct flash_bank_s *bank, int set, int first, int last); +int str9xpec_write(struct flash_bank_s *bank, u8 *buffer, u32 offset, u32 count); +int str9xpec_probe(struct flash_bank_s *bank); +int str9xpec_handle_part_id_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc); +int str9xpec_protect_check(struct flash_bank_s *bank); +int str9xpec_erase_check(struct flash_bank_s *bank); +int str9xpec_info(struct flash_bank_s *bank, char *buf, int buf_size); + +int str9xpec_erase_area(struct flash_bank_s *bank, int first, int last); +int str9xpec_set_address(struct flash_bank_s *bank, u8 sector); +int str9xpec_write_options(struct flash_bank_s *bank); + +int str9xpec_handle_flash_options_cmap_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc); +int str9xpec_handle_flash_options_lvdthd_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc); +int str9xpec_handle_flash_options_lvdsel_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc); +int str9xpec_handle_flash_options_lvdwarn_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc); +int str9xpec_handle_flash_options_read_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc); +int str9xpec_handle_flash_options_write_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc); +int str9xpec_handle_flash_lock_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc); +int str9xpec_handle_flash_unlock_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc); +int str9xpec_handle_flash_enable_turbo_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc); +int str9xpec_handle_flash_disable_turbo_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc); + +flash_driver_t str9xpec_flash = +{ + .name = "str9xpec", + .register_commands = str9xpec_register_commands, + .flash_bank_command = str9xpec_flash_bank_command, + .erase = str9xpec_erase, + .protect = str9xpec_protect, + .write = str9xpec_write, + .probe = str9xpec_probe, + .auto_probe = str9xpec_probe, + .erase_check = str9xpec_erase_check, + .protect_check = str9xpec_protect_check, + .info = str9xpec_info +}; + +int str9xpec_register_commands(struct command_context_s *cmd_ctx) +{ + command_t *str9xpec_cmd = register_command(cmd_ctx, NULL, "str9xpec", NULL, COMMAND_ANY, "str9xpec flash specific commands"); + + register_command(cmd_ctx, str9xpec_cmd, "enable_turbo", str9xpec_handle_flash_enable_turbo_command, COMMAND_EXEC, + "enable str9xpec turbo mode"); + register_command(cmd_ctx, str9xpec_cmd, "disable_turbo", str9xpec_handle_flash_disable_turbo_command, COMMAND_EXEC, + "disable str9xpec turbo mode"); + register_command(cmd_ctx, str9xpec_cmd, "options_cmap", str9xpec_handle_flash_options_cmap_command, COMMAND_EXEC, + "configure str9xpec boot sector"); + register_command(cmd_ctx, str9xpec_cmd, "options_lvdthd", str9xpec_handle_flash_options_lvdthd_command, COMMAND_EXEC, + "configure str9xpec lvd threshold"); + register_command(cmd_ctx, str9xpec_cmd, "options_lvdsel", str9xpec_handle_flash_options_lvdsel_command, COMMAND_EXEC, + "configure str9xpec lvd selection"); + register_command(cmd_ctx, str9xpec_cmd, "options_lvdwarn", str9xpec_handle_flash_options_lvdwarn_command, COMMAND_EXEC, + "configure str9xpec lvd warning"); + register_command(cmd_ctx, str9xpec_cmd, "options_read", str9xpec_handle_flash_options_read_command, COMMAND_EXEC, + "read str9xpec options"); + register_command(cmd_ctx, str9xpec_cmd, "options_write", str9xpec_handle_flash_options_write_command, COMMAND_EXEC, + "write str9xpec options"); + register_command(cmd_ctx, str9xpec_cmd, "lock", str9xpec_handle_flash_lock_command, COMMAND_EXEC, + "lock str9xpec device"); + register_command(cmd_ctx, str9xpec_cmd, "unlock", str9xpec_handle_flash_unlock_command, COMMAND_EXEC, + "unlock str9xpec device"); + register_command(cmd_ctx, str9xpec_cmd, "part_id", str9xpec_handle_part_id_command, COMMAND_EXEC, + "print part id of str9xpec flash bank "); + + return ERROR_OK; +} + +int str9xpec_set_instr(int chain_pos, u32 new_instr, enum tap_state end_state) +{ + jtag_device_t *device = jtag_get_device(chain_pos); + + if (device == NULL) + { + DEBUG("Invalid Target"); + return ERROR_TARGET_INVALID; + } + + if (buf_get_u32(device->cur_instr, 0, device->ir_length) != new_instr) + { + scan_field_t field; + + field.device = chain_pos; + field.num_bits = device->ir_length; + field.out_value = calloc(CEIL(field.num_bits, 8), 1); + buf_set_u32(field.out_value, 0, field.num_bits, new_instr); + field.out_mask = NULL; + field.in_value = NULL; + field.in_check_value = NULL; + field.in_check_mask = NULL; + field.in_handler = NULL; + field.in_handler_priv = NULL; + + jtag_add_ir_scan(1, &field, end_state); + + free(field.out_value); + } + + return ERROR_OK; +} + +u8 str9xpec_isc_status(int chain_pos) +{ + scan_field_t field; + u8 status; + + if (str9xpec_set_instr(chain_pos, ISC_NOOP, TAP_PI) != ERROR_OK) + return ISC_STATUS_ERROR; + + field.device = chain_pos; + field.num_bits = 8; + field.out_value = NULL; + field.out_mask = NULL; + field.in_value = &status; + field.in_check_value = NULL; + field.in_check_mask = NULL; + field.in_handler = NULL; + field.in_handler_priv = NULL; + + jtag_add_dr_scan(1, &field, TAP_RTI); + jtag_execute_queue(); + + DEBUG("status: 0x%2.2x", status); + + if (status & ISC_STATUS_SECURITY) + INFO("Device Security Bit Set"); + + return status; +} + +int str9xpec_isc_enable(struct flash_bank_s *bank) +{ + u8 status; + u32 chain_pos; + str9xpec_flash_controller_t *str9xpec_info = bank->driver_priv; + + chain_pos = str9xpec_info->chain_pos; + + if (str9xpec_info->isc_enable) + return ERROR_OK; + + /* enter isc mode */ + if (str9xpec_set_instr(chain_pos, ISC_ENABLE, TAP_RTI) != ERROR_OK) + return ERROR_TARGET_INVALID; + + /* check ISC status */ + status = str9xpec_isc_status(chain_pos); + if (status & ISC_STATUS_MODE) + { + /* we have entered isc mode */ + str9xpec_info->isc_enable = 1; + DEBUG("ISC_MODE Enabled"); + } + + return ERROR_OK; +} + +int str9xpec_isc_disable(struct flash_bank_s *bank) +{ + u8 status; + u32 chain_pos; + str9xpec_flash_controller_t *str9xpec_info = bank->driver_priv; + + chain_pos = str9xpec_info->chain_pos; + + if (!str9xpec_info->isc_enable) + return ERROR_OK; + + if (str9xpec_set_instr(chain_pos, ISC_DISABLE, TAP_RTI) != ERROR_OK) + return ERROR_TARGET_INVALID; + + /* delay to handle aborts */ + jtag_add_sleep(50); + + /* check ISC status */ + status = str9xpec_isc_status(chain_pos); + if (!(status & ISC_STATUS_MODE)) + { + /* we have left isc mode */ + str9xpec_info->isc_enable = 0; + DEBUG("ISC_MODE Disabled"); + } + + return ERROR_OK; +} + +int str9xpec_read_config(struct flash_bank_s *bank) +{ + scan_field_t field; + u8 status; + u32 chain_pos; + + str9xpec_flash_controller_t *str9xpec_info = bank->driver_priv; + + chain_pos = str9xpec_info->chain_pos; + + DEBUG("ISC_CONFIGURATION"); + + /* execute ISC_CONFIGURATION command */ + str9xpec_set_instr(chain_pos, ISC_CONFIGURATION, TAP_PI); + + field.device = chain_pos; + field.num_bits = 64; + field.out_value = NULL; + field.out_mask = NULL; + field.in_value = str9xpec_info->options; + field.in_check_value = NULL; + field.in_check_mask = NULL; + field.in_handler = NULL; + field.in_handler_priv = NULL; + + jtag_add_dr_scan(1, &field, TAP_RTI); + jtag_execute_queue(); + + status = str9xpec_isc_status(chain_pos); + + return status; +} + +int str9xpec_build_block_list(struct flash_bank_s *bank) +{ + str9xpec_flash_controller_t *str9xpec_info = bank->driver_priv; + + int i; + int num_sectors = 0, b0_sectors = 0; + + switch (bank->size) + { + case (256 * 1024): + b0_sectors = 4; + break; + case (512 * 1024): + b0_sectors = 8; + break; + default: + ERROR("BUG: unknown bank->size encountered"); + exit(-1); + } + + /* include bank 1 sectors */ + num_sectors = b0_sectors + 4; + bank->size += (32 * 1024); + + bank->num_sectors = num_sectors; + bank->sectors = malloc(sizeof(flash_sector_t) * num_sectors); + str9xpec_info->sector_bits = malloc(sizeof(u32) * num_sectors); + + num_sectors = 0; + + for (i = 0; i < b0_sectors; i++) + { + bank->sectors[num_sectors].offset = mem_layout_str9pec[i].sector_start; + bank->sectors[num_sectors].size = mem_layout_str9pec[i].sector_size; + bank->sectors[num_sectors].is_erased = -1; + bank->sectors[num_sectors].is_protected = 1; + str9xpec_info->sector_bits[num_sectors++] = mem_layout_str9pec[i].sector_bit; + } + + for (i = 8; i < 12; i++) + { + bank->sectors[num_sectors].offset = mem_layout_str9pec[i].sector_start; + bank->sectors[num_sectors].size = mem_layout_str9pec[i].sector_size; + bank->sectors[num_sectors].is_erased = -1; + bank->sectors[num_sectors].is_protected = 1; + str9xpec_info->sector_bits[num_sectors++] = mem_layout_str9pec[i].sector_bit; + } + + return ERROR_OK; +} + +/* flash bank str9x 0 0 + */ +int str9xpec_flash_bank_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc, struct flash_bank_s *bank) +{ + str9xpec_flash_controller_t *str9xpec_info; + armv4_5_common_t *armv4_5 = NULL; + arm7_9_common_t *arm7_9 = NULL; + arm_jtag_t *jtag_info = NULL; + + if (argc < 6) + { + WARNING("incomplete flash_bank str9x configuration"); + return ERROR_FLASH_BANK_INVALID; + } + + str9xpec_info = malloc(sizeof(str9xpec_flash_controller_t)); + bank->driver_priv = str9xpec_info; + + if (bank->base != 0x00000000) + { + WARNING("overriding flash base address for STR91x device with 0x00000000"); + bank->base = 0x00000000; + } + + /* find out jtag position of flash controller + * it is always after the arm966 core */ + + armv4_5 = bank->target->arch_info; + arm7_9 = armv4_5->arch_info; + jtag_info = &arm7_9->jtag_info; + + str9xpec_info->chain_pos = (jtag_info->chain_pos - 1); + str9xpec_info->isc_enable = 0; + str9xpec_info->devarm = NULL; + + str9xpec_build_block_list(bank); + + /* clear option byte register */ + buf_set_u32(str9xpec_info->options, 0, 64, 0); + + return ERROR_OK; +} + +int str9xpec_blank_check(struct flash_bank_s *bank, int first, int last) +{ + scan_field_t field; + u8 status; + u32 chain_pos; + int i; + u8 *buffer = NULL; + + str9xpec_flash_controller_t *str9xpec_info = bank->driver_priv; + + chain_pos = str9xpec_info->chain_pos; + + if (!str9xpec_info->isc_enable) { + str9xpec_isc_enable( bank ); + } + + if (!str9xpec_info->isc_enable) { + return ERROR_FLASH_OPERATION_FAILED; + } + + buffer = calloc(CEIL(64, 8), 1); + + DEBUG("blank check: first_bank: %i, last_bank: %i", first, last); + + for (i = first; i <= last; i++) { + buf_set_u32(buffer, str9xpec_info->sector_bits[i], 1, 1); + } + + /* execute ISC_BLANK_CHECK command */ + str9xpec_set_instr(chain_pos, ISC_BLANK_CHECK, TAP_PI); + + field.device = chain_pos; + field.num_bits = 64; + field.out_value = buffer; + field.out_mask = NULL; + field.in_value = NULL; + field.in_check_value = NULL; + field.in_check_mask = NULL; + field.in_handler = NULL; + field.in_handler_priv = NULL; + + jtag_add_dr_scan(1, &field, TAP_RTI); + jtag_add_sleep(40000); + + /* read blank check result */ + field.device = chain_pos; + field.num_bits = 64; + field.out_value = NULL; + field.out_mask = NULL; + field.in_value = buffer; + field.in_check_value = NULL; + field.in_check_mask = NULL; + field.in_handler = NULL; + field.in_handler_priv = NULL; + + jtag_add_dr_scan(1, &field, TAP_PI); + jtag_execute_queue(); + + status = str9xpec_isc_status(chain_pos); + + for (i = first; i <= last; i++) + { + if (buf_get_u32(buffer, str9xpec_info->sector_bits[i], 1)) + bank->sectors[i].is_erased = 0; + else + bank->sectors[i].is_erased = 1; + } + + free(buffer); + + str9xpec_isc_disable(bank); + + if ((status & ISC_STATUS_ERROR) != STR9XPEC_ISC_SUCCESS) + return ERROR_FLASH_OPERATION_FAILED; + return ERROR_OK; +} + +int str9xpec_protect_check(struct flash_bank_s *bank) +{ + u8 status; + int i; + + str9xpec_flash_controller_t *str9xpec_info = bank->driver_priv; + + status = str9xpec_read_config(bank); + + for (i = 0; i < bank->num_sectors; i++) + { + if (buf_get_u32(str9xpec_info->options, str9xpec_info->sector_bits[i], 1)) + bank->sectors[i].is_protected = 1; + else + bank->sectors[i].is_protected = 0; + } + + if ((status & ISC_STATUS_ERROR) != STR9XPEC_ISC_SUCCESS) + return ERROR_FLASH_OPERATION_FAILED; + return ERROR_OK; +} + +int str9xpec_erase_area(struct flash_bank_s *bank, int first, int last) +{ + scan_field_t field; + u8 status; + u32 chain_pos; + int i; + u8 *buffer = NULL; + + str9xpec_flash_controller_t *str9xpec_info = bank->driver_priv; + + chain_pos = str9xpec_info->chain_pos; + + if (!str9xpec_info->isc_enable) { + str9xpec_isc_enable( bank ); + } + + if (!str9xpec_info->isc_enable) { + return ISC_STATUS_ERROR; + } + + buffer = calloc(CEIL(64, 8), 1); + + DEBUG("erase: first_bank: %i, last_bank: %i", first, last); + + /* last bank: 0xFF signals a full erase (unlock complete device) */ + /* last bank: 0xFE signals a option byte erase */ + if (last == 0xFF) + { + for (i = 0; i < 64; i++) { + buf_set_u32(buffer, i, 1, 1); + } + } + else if (last == 0xFE) + { + buf_set_u32(buffer, 49, 1, 1); + } + else + { + for (i = first; i <= last; i++) { + buf_set_u32(buffer, str9xpec_info->sector_bits[i], 1, 1); + } + } + + DEBUG("ISC_ERASE"); + + /* execute ISC_ERASE command */ + str9xpec_set_instr(chain_pos, ISC_ERASE, TAP_PI); + + field.device = chain_pos; + field.num_bits = 64; + field.out_value = buffer; + field.out_mask = NULL; + field.in_value = NULL; + field.in_check_value = NULL; + field.in_check_mask = NULL; + field.in_handler = NULL; + field.in_handler_priv = NULL; + + jtag_add_dr_scan(1, &field, TAP_RTI); + jtag_execute_queue(); + + jtag_add_sleep(10); + + /* wait for erase completion */ + while (!((status = str9xpec_isc_status(chain_pos)) & ISC_STATUS_BUSY)) { + usleep(1000); + } + + free(buffer); + + str9xpec_isc_disable(bank); + + return status; +} + +int str9xpec_erase(struct flash_bank_s *bank, int first, int last) +{ + int status; + + status = str9xpec_erase_area(bank, first, last); + + if ((status & ISC_STATUS_ERROR) != STR9XPEC_ISC_SUCCESS) + return ERROR_FLASH_OPERATION_FAILED; + + return ERROR_OK; +} + +int str9xpec_lock_device(struct flash_bank_s *bank) +{ + scan_field_t field; + u8 status; + u32 chain_pos; + str9xpec_flash_controller_t *str9xpec_info = NULL; + + str9xpec_info = bank->driver_priv; + chain_pos = str9xpec_info->chain_pos; + + if (!str9xpec_info->isc_enable) { + str9xpec_isc_enable( bank ); + } + + if (!str9xpec_info->isc_enable) { + return ISC_STATUS_ERROR; + } + + /* set security address */ + str9xpec_set_address(bank, 0x80); + + /* execute ISC_PROGRAM command */ + str9xpec_set_instr(chain_pos, ISC_PROGRAM_SECURITY, TAP_RTI); + + str9xpec_set_instr(chain_pos, ISC_NOOP, TAP_PI); + + do { + field.device = chain_pos; + field.num_bits = 8; + field.out_value = NULL; + field.out_mask = NULL; + field.in_value = &status; + field.in_check_value = NULL; + field.in_check_mask = NULL; + field.in_handler = NULL; + field.in_handler_priv = NULL; + + jtag_add_dr_scan(1, &field, -1); + jtag_execute_queue(); + + } while(!(status & ISC_STATUS_BUSY)); + + str9xpec_isc_disable(bank); + + return status; +} + +int str9xpec_unlock_device(struct flash_bank_s *bank) +{ + u8 status; + + status = str9xpec_erase_area(bank, 0, 255); + + return status; +} + +int str9xpec_protect(struct flash_bank_s *bank, int set, int first, int last) +{ + u8 status; + int i; + + str9xpec_flash_controller_t *str9xpec_info = bank->driver_priv; + + status = str9xpec_read_config(bank); + + if ((status & ISC_STATUS_ERROR) != STR9XPEC_ISC_SUCCESS) + return ERROR_FLASH_OPERATION_FAILED; + + DEBUG("protect: first_bank: %i, last_bank: %i", first, last); + + /* last bank: 0xFF signals a full device protect */ + if (last == 0xFF) + { + if( set ) + { + status = str9xpec_lock_device(bank); + } + else + { + /* perform full erase to unlock device */ + status = str9xpec_unlock_device(bank); + } + } + else + { + for (i = first; i <= last; i++) + { + if( set ) + buf_set_u32(str9xpec_info->options, str9xpec_info->sector_bits[i], 1, 1); + else + buf_set_u32(str9xpec_info->options, str9xpec_info->sector_bits[i], 1, 0); + } + + status = str9xpec_write_options(bank); + } + + if ((status & ISC_STATUS_ERROR) != STR9XPEC_ISC_SUCCESS) + return ERROR_FLASH_OPERATION_FAILED; + + return ERROR_OK; +} + +int str9xpec_set_address(struct flash_bank_s *bank, u8 sector) +{ + u32 chain_pos; + scan_field_t field; + str9xpec_flash_controller_t *str9xpec_info = bank->driver_priv; + + chain_pos = str9xpec_info->chain_pos; + + /* set flash controller address */ + str9xpec_set_instr(chain_pos, ISC_ADDRESS_SHIFT, TAP_PI); + + field.device = chain_pos; + field.num_bits = 8; + field.out_value = §or; + field.out_mask = NULL; + field.in_value = NULL; + field.in_check_value = NULL; + field.in_check_mask = NULL; + field.in_handler = NULL; + field.in_handler_priv = NULL; + + jtag_add_dr_scan(1, &field, -1); + + return ERROR_OK; +} + +int str9xpec_write(struct flash_bank_s *bank, u8 *buffer, u32 offset, u32 count) +{ + str9xpec_flash_controller_t *str9xpec_info = bank->driver_priv; + u32 dwords_remaining = (count / 8); + u32 bytes_remaining = (count & 0x00000007); + u32 bytes_written = 0; + u8 status; + u32 check_address = offset; + u32 chain_pos; + scan_field_t field; + u8 *scanbuf; + int i; + u32 first_sector = 0; + u32 last_sector = 0; + + chain_pos = str9xpec_info->chain_pos; + + if (!str9xpec_info->isc_enable) { + str9xpec_isc_enable(bank); + } + + if (!str9xpec_info->isc_enable) { + return ERROR_FLASH_OPERATION_FAILED; + } + + if (offset & 0x7) + { + WARNING("offset 0x%x breaks required 8-byte alignment", offset); + return ERROR_FLASH_DST_BREAKS_ALIGNMENT; + } + + for (i = 0; i < bank->num_sectors; i++) + { + u32 sec_start = bank->sectors[i].offset; + u32 sec_end = sec_start + bank->sectors[i].size; + + /* check if destination falls within the current sector */ + if ((check_address >= sec_start) && (check_address < sec_end)) + { + /* check if destination ends in the current sector */ + if (offset + count < sec_end) + check_address = offset + count; + else + check_address = sec_end; + } + + if ((offset >= sec_start) && (offset < sec_end)){ + first_sector = i; + } + + if ((offset + count >= sec_start) && (offset + count < sec_end)){ + last_sector = i; + } + } + + if (check_address != offset + count) + return ERROR_FLASH_DST_OUT_OF_BANK; + + DEBUG("first_sector: %i, last_sector: %i", first_sector, last_sector); + + scanbuf = calloc(CEIL(64, 8), 1); + + DEBUG("ISC_PROGRAM"); + + for (i = first_sector; i <= last_sector; i++) + { + str9xpec_set_address(bank, str9xpec_info->sector_bits[i]); + + dwords_remaining = dwords_remaining < (bank->sectors[i].size/8) ? dwords_remaining : (bank->sectors[i].size/8); + + while (dwords_remaining > 0) + { + str9xpec_set_instr(chain_pos, ISC_PROGRAM, TAP_PI); + + field.device = chain_pos; + field.num_bits = 64; + field.out_value = (buffer + bytes_written); + field.out_mask = NULL; + field.in_value = NULL; + field.in_check_value = NULL; + field.in_check_mask = NULL; + field.in_handler = NULL; + field.in_handler_priv = NULL; + + jtag_add_dr_scan(1, &field, TAP_RTI); + + /* small delay before polling */ + jtag_add_sleep(50); + + str9xpec_set_instr(chain_pos, ISC_NOOP, TAP_PI); + + do { + field.device = chain_pos; + field.num_bits = 8; + field.out_value = NULL; + field.out_mask = NULL; + field.in_value = scanbuf; + field.in_check_value = NULL; + field.in_check_mask = NULL; + field.in_handler = NULL; + field.in_handler_priv = NULL; + + jtag_add_dr_scan(1, &field, -1); + jtag_execute_queue(); + + status = buf_get_u32(scanbuf, 0, 8); + + } while(!(status & ISC_STATUS_BUSY)); + + if ((status & ISC_STATUS_ERROR) != STR9XPEC_ISC_SUCCESS) + return ERROR_FLASH_OPERATION_FAILED; + + //if ((status & ISC_STATUS_INT_ERROR) != STR9XPEC_ISC_INTFAIL) + // return ERROR_FLASH_OPERATION_FAILED; + + dwords_remaining--; + bytes_written += 8; + } + } + + if (bytes_remaining) + { + u8 last_dword[8] = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff}; + int i = 0; + + while(bytes_remaining > 0) + { + last_dword[i++] = *(buffer + bytes_written); + bytes_remaining--; + bytes_written++; + } + + str9xpec_set_instr(chain_pos, ISC_PROGRAM, TAP_PI); + + field.device = chain_pos; + field.num_bits = 64; + field.out_value = last_dword; + field.out_mask = NULL; + field.in_value = NULL; + field.in_check_value = NULL; + field.in_check_mask = NULL; + field.in_handler = NULL; + field.in_handler_priv = NULL; + + jtag_add_dr_scan(1, &field, TAP_RTI); + + /* small delay before polling */ + jtag_add_sleep(50); + + str9xpec_set_instr(chain_pos, ISC_NOOP, TAP_PI); + + do { + field.device = chain_pos; + field.num_bits = 8; + field.out_value = NULL; + field.out_mask = NULL; + field.in_value = scanbuf; + field.in_check_value = NULL; + field.in_check_mask = NULL; + field.in_handler = NULL; + field.in_handler_priv = NULL; + + jtag_add_dr_scan(1, &field, -1); + jtag_execute_queue(); + + status = buf_get_u32(scanbuf, 0, 8); + + } while(!(status & ISC_STATUS_BUSY)); + + if ((status & ISC_STATUS_ERROR) != STR9XPEC_ISC_SUCCESS) + return ERROR_FLASH_OPERATION_FAILED; + + //if ((status & ISC_STATUS_INT_ERROR) != STR9XPEC_ISC_INTFAIL) + // return ERROR_FLASH_OPERATION_FAILED; + } + + free(scanbuf); + + str9xpec_isc_disable(bank); + + return ERROR_OK; +} + +int str9xpec_probe(struct flash_bank_s *bank) +{ + return ERROR_OK; +} + +int str9xpec_handle_part_id_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc) +{ + flash_bank_t *bank; + scan_field_t field; + u8 *buffer = NULL; + u32 chain_pos; + u32 idcode; + str9xpec_flash_controller_t *str9xpec_info = NULL; + + if (argc < 1) + { + return ERROR_COMMAND_SYNTAX_ERROR; + } + + bank = get_flash_bank_by_num(strtoul(args[0], NULL, 0)); + if (!bank) + { + command_print(cmd_ctx, "flash bank '#%s' is out of bounds", args[0]); + return ERROR_OK; + } + + str9xpec_info = bank->driver_priv; + chain_pos = str9xpec_info->chain_pos; + + buffer = calloc(CEIL(32, 8), 1); + + str9xpec_set_instr(chain_pos, ISC_IDCODE, TAP_PI); + + field.device = chain_pos; + field.num_bits = 32; + field.out_value = NULL; + field.out_mask = NULL; + field.in_value = buffer; + field.in_check_value = NULL; + field.in_check_mask = NULL; + field.in_handler = NULL; + field.in_handler_priv = NULL; + + jtag_add_dr_scan(1, &field, TAP_RTI); + jtag_execute_queue(); + + idcode = buf_get_u32(buffer, 0, 32); + + command_print(cmd_ctx, "str9xpec part id: 0x%8.8x", idcode); + + free(buffer); + + return ERROR_OK; +} + +int str9xpec_erase_check(struct flash_bank_s *bank) +{ + return str9xpec_blank_check(bank, 0, bank->num_sectors - 1); +} + +int str9xpec_info(struct flash_bank_s *bank, char *buf, int buf_size) +{ + snprintf(buf, buf_size, "str9xpec flash driver info" ); + return ERROR_OK; +} + +int str9xpec_handle_flash_options_read_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc) +{ + flash_bank_t *bank; + u8 status; + str9xpec_flash_controller_t *str9xpec_info = NULL; + + if (argc < 1) + { + command_print(cmd_ctx, "str9xpec options_read "); + return ERROR_OK; + } + + bank = get_flash_bank_by_num(strtoul(args[0], NULL, 0)); + if (!bank) + { + command_print(cmd_ctx, "flash bank '#%s' is out of bounds", args[0]); + return ERROR_OK; + } + + str9xpec_info = bank->driver_priv; + + status = str9xpec_read_config(bank); + + if ((status & ISC_STATUS_ERROR) != STR9XPEC_ISC_SUCCESS) + return ERROR_FLASH_OPERATION_FAILED; + + /* boot bank */ + if (buf_get_u32(str9xpec_info->options, STR9XPEC_OPT_CSMAPBIT, 1)) + command_print(cmd_ctx, "CS Map: bank1"); + else + command_print(cmd_ctx, "CS Map: bank0"); + + /* OTP lock */ + if (buf_get_u32(str9xpec_info->options, STR9XPEC_OPT_OTPBIT, 1)) + command_print(cmd_ctx, "OTP Lock: OTP Locked"); + else + command_print(cmd_ctx, "OTP Lock: OTP Unlocked"); + + /* LVD Threshold */ + if (buf_get_u32(str9xpec_info->options, STR9XPEC_OPT_LVDTHRESBIT, 1)) + command_print(cmd_ctx, "LVD Threshold: 2.7v"); + else + command_print(cmd_ctx, "LVD Threshold: 2.4v"); + + /* LVD reset warning */ + if (buf_get_u32(str9xpec_info->options, STR9XPEC_OPT_LVDWARNBIT, 1)) + command_print(cmd_ctx, "LVD Reset Warning: VDD or VDDQ Inputs"); + else + command_print(cmd_ctx, "LVD Reset Warning: VDD Input Only"); + + /* LVD reset select */ + if (buf_get_u32(str9xpec_info->options, STR9XPEC_OPT_LVDSELBIT, 1)) + command_print(cmd_ctx, "LVD Reset Selection: VDD or VDDQ Inputs"); + else + command_print(cmd_ctx, "LVD Reset Selection: VDD Input Only"); + + return ERROR_OK; +} + +int str9xpec_write_options(struct flash_bank_s *bank) +{ + scan_field_t field; + u8 status; + u32 chain_pos; + str9xpec_flash_controller_t *str9xpec_info = NULL; + + str9xpec_info = bank->driver_priv; + chain_pos = str9xpec_info->chain_pos; + + /* erase config options first */ + status = str9xpec_erase_area( bank, 0xFE, 0xFE ); + + if ((status & ISC_STATUS_ERROR) != STR9XPEC_ISC_SUCCESS) + return status; + + if (!str9xpec_info->isc_enable) { + str9xpec_isc_enable( bank ); + } + + if (!str9xpec_info->isc_enable) { + return ISC_STATUS_ERROR; + } + + /* according to data 64th bit has to be set */ + buf_set_u32(str9xpec_info->options, 63, 1, 1); + + /* set option byte address */ + str9xpec_set_address(bank, 0x50); + + /* execute ISC_PROGRAM command */ + str9xpec_set_instr(chain_pos, ISC_PROGRAM, TAP_PI); + + field.device = chain_pos; + field.num_bits = 64; + field.out_value = str9xpec_info->options; + field.out_mask = NULL; + field.in_value = NULL; + field.in_check_value = NULL; + field.in_check_mask = NULL; + field.in_handler = NULL; + field.in_handler_priv = NULL; + + jtag_add_dr_scan(1, &field, TAP_RTI); + + /* small delay before polling */ + jtag_add_sleep(50); + + str9xpec_set_instr(chain_pos, ISC_NOOP, TAP_PI); + + do { + field.device = chain_pos; + field.num_bits = 8; + field.out_value = NULL; + field.out_mask = NULL; + field.in_value = &status; + field.in_check_value = NULL; + field.in_check_mask = NULL; + field.in_handler = NULL; + field.in_handler_priv = NULL; + + jtag_add_dr_scan(1, &field, -1); + jtag_execute_queue(); + + } while(!(status & ISC_STATUS_BUSY)); + + str9xpec_isc_disable(bank); + + return status; +} + +int str9xpec_handle_flash_options_write_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc) +{ + flash_bank_t *bank; + u8 status; + + if (argc < 1) + { + command_print(cmd_ctx, "str9xpec options_write "); + return ERROR_OK; + } + + bank = get_flash_bank_by_num(strtoul(args[0], NULL, 0)); + if (!bank) + { + command_print(cmd_ctx, "flash bank '#%s' is out of bounds", args[0]); + return ERROR_OK; + } + + status = str9xpec_write_options(bank); + + if ((status & ISC_STATUS_ERROR) != STR9XPEC_ISC_SUCCESS) + return ERROR_FLASH_OPERATION_FAILED; + + return ERROR_OK; +} + +int str9xpec_handle_flash_options_cmap_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc) +{ + flash_bank_t *bank; + str9xpec_flash_controller_t *str9xpec_info = NULL; + + if (argc < 2) + { + command_print(cmd_ctx, "str9xpec options_cmap "); + return ERROR_OK; + } + + bank = get_flash_bank_by_num(strtoul(args[0], NULL, 0)); + if (!bank) + { + command_print(cmd_ctx, "flash bank '#%s' is out of bounds", args[0]); + return ERROR_OK; + } + + str9xpec_info = bank->driver_priv; + + if (strcmp(args[1], "bank1") == 0) + { + buf_set_u32(str9xpec_info->options, STR9XPEC_OPT_CSMAPBIT, 1, 1); + } + else + { + buf_set_u32(str9xpec_info->options, STR9XPEC_OPT_CSMAPBIT, 1, 0); + } + + return ERROR_OK; +} + +int str9xpec_handle_flash_options_lvdthd_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc) +{ + flash_bank_t *bank; + str9xpec_flash_controller_t *str9xpec_info = NULL; + + if (argc < 2) + { + command_print(cmd_ctx, "str9xpec options_lvdthd <2.4v|2.7v>"); + return ERROR_OK; + } + + bank = get_flash_bank_by_num(strtoul(args[0], NULL, 0)); + if (!bank) + { + command_print(cmd_ctx, "flash bank '#%s' is out of bounds", args[0]); + return ERROR_OK; + } + + str9xpec_info = bank->driver_priv; + + if (strcmp(args[1], "2.7v") == 0) + { + buf_set_u32(str9xpec_info->options, STR9XPEC_OPT_LVDTHRESBIT, 1, 1); + } + else + { + buf_set_u32(str9xpec_info->options, STR9XPEC_OPT_LVDTHRESBIT, 1, 0); + } + + return ERROR_OK; +} + +int str9xpec_handle_flash_options_lvdsel_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc) +{ + flash_bank_t *bank; + str9xpec_flash_controller_t *str9xpec_info = NULL; + + if (argc < 2) + { + command_print(cmd_ctx, "str9xpec options_lvdsel "); + return ERROR_OK; + } + + bank = get_flash_bank_by_num(strtoul(args[0], NULL, 0)); + if (!bank) + { + command_print(cmd_ctx, "flash bank '#%s' is out of bounds", args[0]); + return ERROR_OK; + } + + str9xpec_info = bank->driver_priv; + + if (strcmp(args[1], "vdd_vddq") == 0) + { + buf_set_u32(str9xpec_info->options, STR9XPEC_OPT_LVDSELBIT, 1, 1); + } + else + { + buf_set_u32(str9xpec_info->options, STR9XPEC_OPT_LVDSELBIT, 1, 0); + } + + return ERROR_OK; +} + +int str9xpec_handle_flash_options_lvdwarn_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc) +{ + flash_bank_t *bank; + str9xpec_flash_controller_t *str9xpec_info = NULL; + + if (argc < 2) + { + command_print(cmd_ctx, "str9xpec options_lvdwarn "); + return ERROR_OK; + } + + bank = get_flash_bank_by_num(strtoul(args[0], NULL, 0)); + if (!bank) + { + command_print(cmd_ctx, "flash bank '#%s' is out of bounds", args[0]); + return ERROR_OK; + } + + str9xpec_info = bank->driver_priv; + + if (strcmp(args[1], "vdd_vddq") == 0) + { + buf_set_u32(str9xpec_info->options, STR9XPEC_OPT_LVDWARNBIT, 1, 1); + } + else + { + buf_set_u32(str9xpec_info->options, STR9XPEC_OPT_LVDWARNBIT, 1, 0); + } + + return ERROR_OK; +} + +int str9xpec_handle_flash_lock_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc) +{ + u8 status; + flash_bank_t *bank; + + if (argc < 1) + { + command_print(cmd_ctx, "str9xpec lock "); + return ERROR_OK; + } + + bank = get_flash_bank_by_num(strtoul(args[0], NULL, 0)); + if (!bank) + { + command_print(cmd_ctx, "flash bank '#%s' is out of bounds", args[0]); + return ERROR_OK; + } + + status = str9xpec_lock_device(bank); + + if ((status & ISC_STATUS_ERROR) != STR9XPEC_ISC_SUCCESS) + return ERROR_FLASH_OPERATION_FAILED; + + return ERROR_OK; +} + +int str9xpec_handle_flash_unlock_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc) +{ + u8 status; + flash_bank_t *bank; + + if (argc < 1) + { + command_print(cmd_ctx, "str9xpec unlock "); + return ERROR_OK; + } + + bank = get_flash_bank_by_num(strtoul(args[0], NULL, 0)); + if (!bank) + { + command_print(cmd_ctx, "flash bank '#%s' is out of bounds", args[0]); + return ERROR_OK; + } + + status = str9xpec_unlock_device(bank); + + if ((status & ISC_STATUS_ERROR) != STR9XPEC_ISC_SUCCESS) + return ERROR_FLASH_OPERATION_FAILED; + + return ERROR_OK; +} + +int str9xpec_handle_flash_enable_turbo_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc) +{ + flash_bank_t *bank; + u32 chain_pos; + jtag_device_t* dev0; + jtag_device_t* dev2; + str9xpec_flash_controller_t *str9xpec_info = NULL; + + if (argc < 1) + { + command_print(cmd_ctx, "str9xpec enable_turbo "); + return ERROR_OK; + } + + bank = get_flash_bank_by_num(strtoul(args[0], NULL, 0)); + if (!bank) + { + command_print(cmd_ctx, "flash bank '#%s' is out of bounds", args[0]); + return ERROR_OK; + } + + str9xpec_info = bank->driver_priv; + + chain_pos = str9xpec_info->chain_pos; + + /* remove arm core from chain - enter turbo mode */ + + str9xpec_set_instr(chain_pos+2, 0xD, TAP_RTI); + jtag_execute_queue(); + + /* modify scan chain - str9 core has been removed */ + dev0 = jtag_get_device(chain_pos); + str9xpec_info->devarm = jtag_get_device(chain_pos+1); + dev2 = jtag_get_device(chain_pos+2); + dev0->next = dev2; + jtag_num_devices--; + + return ERROR_OK; +} + +int str9xpec_handle_flash_disable_turbo_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc) +{ + flash_bank_t *bank; + u32 chain_pos; + jtag_device_t* dev0; + str9xpec_flash_controller_t *str9xpec_info = NULL; + + if (argc < 1) + { + command_print(cmd_ctx, "str9xpec disable_turbo "); + return ERROR_OK; + } + + bank = get_flash_bank_by_num(strtoul(args[0], NULL, 0)); + if (!bank) + { + command_print(cmd_ctx, "flash bank '#%s' is out of bounds", args[0]); + return ERROR_OK; + } + + str9xpec_info = bank->driver_priv; + + chain_pos = str9xpec_info->chain_pos; + + dev0 = jtag_get_device(chain_pos); + + /* exit turbo mode via TLR */ + str9xpec_set_instr(chain_pos, ISC_NOOP, TAP_TLR); + jtag_execute_queue(); + + /* restore previous scan chain */ + if( str9xpec_info->devarm ) { + dev0->next = str9xpec_info->devarm; + jtag_num_devices++; + str9xpec_info->devarm = NULL; + } + + return ERROR_OK; +} -- cgit v1.2.3