From e9297b40b994f071474210e7d9e224d50e25fcaf Mon Sep 17 00:00:00 2001
From: drath <drath@b42882b7-edfa-0310-969c-e2dbd0fdcd60>
Date: Wed, 22 Nov 2006 13:03:10 +0000
Subject: - added a PLD (programmable logic device) subsystem for FPGA, CPLD
 etc. configuration - added support for loading .bit files into Xilinx
 Virtex-II devices - added support for the Gateworks GW16012 JTAG dongle -
 merged CFI fixes from XScale branch - a few minor fixes

git-svn-id: svn://svn.berlios.de/openocd/trunk@116 b42882b7-edfa-0310-969c-e2dbd0fdcd60
---
 src/pld/Makefile.am | 5 +++++
 1 file changed, 5 insertions(+)
 create mode 100644 src/pld/Makefile.am

(limited to 'src/pld/Makefile.am')

diff --git a/src/pld/Makefile.am b/src/pld/Makefile.am
new file mode 100644
index 00000000..e3386257
--- /dev/null
+++ b/src/pld/Makefile.am
@@ -0,0 +1,5 @@
+INCLUDES = -I$(top_srcdir)/src/server -I$(top_srcdir)/src/helper -I$(top_srcdir)/src/jtag $(all_includes)
+METASOURCES = AUTO
+noinst_LIBRARIES = libpld.a
+noinst_HEADERS = pld.h xilinx_bit.h virtex2.h
+libpld_a_SOURCES = pld.c xilinx_bit.c virtex2.c
-- 
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