From 3efc99b34a934cb4d657ec27a164769c46c10f28 Mon Sep 17 00:00:00 2001 From: David Brownell Date: Tue, 24 Nov 2009 01:27:29 -0800 Subject: ARM11: remove old R0..R15/CPSR code This finishes the basic switchover to the new register code, for everything except the debug registers. (And maybe we shouldn't have a cache for *those* which works this way...) The context save/restore code now uses the new code, but it's in a slightly different sequence. That should be fine since the R0/PC/CPSR stuff is all that really matters (and if we can update those, we can update the rest). Now there's no longer a way any code can be confused about which copy of "r1" (etc) to use. Signed-off-by: David Brownell --- src/target/arm11.h | 5 ++--- 1 file changed, 2 insertions(+), 3 deletions(-) (limited to 'src/target/arm11.h') diff --git a/src/target/arm11.h b/src/target/arm11.h index 033ba899..c3f4e864 100644 --- a/src/target/arm11.h +++ b/src/target/arm11.h @@ -26,8 +26,7 @@ #include "armv4_5.h" #include "arm_dpm.h" -/* TEMPORARY -- till we switch to the shared infrastructure */ -#define ARM11_REGCACHE_COUNT 20 +#define ARM11_REGCACHE_COUNT 3 #define ARM11_TAP_DEFAULT TAP_INVALID @@ -70,7 +69,7 @@ struct arm11_common bool simulate_reset_on_next_halt; /**< Perform cleanups of the ARM state on next halt */ - /** \name Shadow registers to save processor state */ + /** \name Shadow registers to save debug state */ /*@{*/ struct reg * reg_list; /**< target register list */ -- cgit v1.2.3