From d5e4e23f9a5b1074cd298d5386e638a9fa78b1ad Mon Sep 17 00:00:00 2001 From: David Brownell Date: Wed, 2 Dec 2009 22:57:08 -0800 Subject: ARM11: don't expose DSCR Remove the remaining extra copy of DSCR, and the register cache of which it was a part. That cache wasn't a very safe, or even necessary, idea; it was essentialy letting debugger-private state be manipulated by Tcl code that couldn't know how to do it right. This makes the "reg" output of an ARM11 resemble what most other ARM cores produce ... forward motion in the "make ARM11 work like the rest of the ARM cores" Jihad! --- src/target/arm11.h | 14 -------------- 1 file changed, 14 deletions(-) (limited to 'src/target/arm11.h') diff --git a/src/target/arm11.h b/src/target/arm11.h index 1cc09e14..cd528965 100644 --- a/src/target/arm11.h +++ b/src/target/arm11.h @@ -26,8 +26,6 @@ #include "armv4_5.h" #include "arm_dpm.h" -#define ARM11_REGCACHE_COUNT 1 - #define ARM11_TAP_DEFAULT TAP_INVALID #define CHECK_RETVAL(action) \ @@ -69,18 +67,6 @@ struct arm11_common bool simulate_reset_on_next_halt; /**< Perform cleanups of the ARM state on next halt */ - /** \name Shadow registers to save debug state */ - /*@{*/ - - struct reg * reg_list; /**< target register list */ - uint32_t reg_values[ARM11_REGCACHE_COUNT]; /**< data for registers */ - - /*@}*/ - - - // GA - struct reg_cache *core_cache; - struct arm_jtag jtag_info; }; -- cgit v1.2.3