From ec93209f51afc09e273a4742dc0b5f2cefc15e76 Mon Sep 17 00:00:00 2001 From: David Brownell Date: Tue, 17 Nov 2009 23:50:23 -0800 Subject: ARM: add arm_mode_name() Add and use arm_mode_name() to map from PSR bits to user meaningful names. It uses a new table which, later, can be used to hold other mode-coupled data. Add definitions for the "Secure Monitor" mode, as seen on some ARM11 cores (like ARM1176) and on Cortex-A8. The previous mode name scheme didn't understand that mode. Remove the old mechanism ... there were two copies, caused by Cortex-A8 needing to add "Secure Monitor" mode support. Signed-off-by: David Brownell --- src/target/arm920t.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'src/target/arm920t.c') diff --git a/src/target/arm920t.c b/src/target/arm920t.c index 99b4bbd3..e1dcea7a 100644 --- a/src/target/arm920t.c +++ b/src/target/arm920t.c @@ -451,7 +451,7 @@ int arm920t_arch_state(struct target *target) "MMU: %s, D-Cache: %s, I-Cache: %s", armv4_5_state_strings[armv4_5->core_state], Jim_Nvp_value2name_simple(nvp_target_debug_reason, target->debug_reason)->name, - armv4_5_mode_strings[armv4_5_mode_to_number(armv4_5->core_mode)], + arm_mode_name(armv4_5->core_mode), buf_get_u32(armv4_5->core_cache->reg_list[ARMV4_5_CPSR].value, 0, 32), buf_get_u32(armv4_5->core_cache->reg_list[15].value, 0, 32), state[arm920t->armv4_5_mmu.mmu_enabled], -- cgit v1.2.3