From 6d1d58a1fc3dfd60e9cac89460b5a6e438d11efa Mon Sep 17 00:00:00 2001
From: zwelch <zwelch@b42882b7-edfa-0310-969c-e2dbd0fdcd60>
Date: Tue, 23 Jun 2009 22:45:47 +0000
Subject: - Fixes '[<>]' whitespace - Replace ')\([<>]\)(' with ') \1 ('. -
 Replace ')\([<>]\)\(\w\)' with ') \1 \2'. - Replace '\(\w\)\([<>]\)(' with
 '\1 \2 ('. - Replace '\(\w\)\([<>]\)\(\w\)' with '\1 \2 \3'.

git-svn-id: svn://svn.berlios.de/openocd/trunk@2375 b42882b7-edfa-0310-969c-e2dbd0fdcd60
---
 src/target/arm_disassembler.c | 12 ++++++------
 1 file changed, 6 insertions(+), 6 deletions(-)

(limited to 'src/target/arm_disassembler.c')

diff --git a/src/target/arm_disassembler.c b/src/target/arm_disassembler.c
index e460e468..d290b670 100644
--- a/src/target/arm_disassembler.c
+++ b/src/target/arm_disassembler.c
@@ -891,7 +891,7 @@ int evaluate_misc_instr(uint32_t opcode, uint32_t address, arm_instruction_t *in
 		int x = (opcode & 0x20) >> 5;
 		int y = (opcode & 0x40) >> 6;
 		
-		/* SMLA<x><y> */
+		/* SMLA < x><y> */
 		if ((opcode & 0x00600000) == 0x00000000)
 		{
 			uint8_t Rd, Rm, Rs, Rn;
@@ -906,7 +906,7 @@ int evaluate_misc_instr(uint32_t opcode, uint32_t address, arm_instruction_t *in
 					 Rd, Rm, Rs, Rn);
 		}
 		
-		/* SMLAL<x><y> */
+		/* SMLAL < x><y> */
 		if ((opcode & 0x00600000) == 0x00400000)
 		{
 			uint8_t RdLow, RdHi, Rm, Rs;
@@ -921,7 +921,7 @@ int evaluate_misc_instr(uint32_t opcode, uint32_t address, arm_instruction_t *in
 					 RdLow, RdHi, Rm, Rs);
 		}
 		
-		/* SMLAW<y> */
+		/* SMLAW < y> */
 		if (((opcode & 0x00600000) == 0x00100000) && (x == 0))
 		{
 			uint8_t Rd, Rm, Rs, Rn;
@@ -936,7 +936,7 @@ int evaluate_misc_instr(uint32_t opcode, uint32_t address, arm_instruction_t *in
 					 Rd, Rm, Rs, Rn);
 		}
 		
-		/* SMUL<x><y> */
+		/* SMUL < x><y> */
 		if ((opcode & 0x00600000) == 0x00300000)
 		{
 			uint8_t Rd, Rm, Rs;
@@ -950,7 +950,7 @@ int evaluate_misc_instr(uint32_t opcode, uint32_t address, arm_instruction_t *in
 					 Rd, Rm, Rs);
 		}
 		
-		/* SMULW<y> */
+		/* SMULW < y> */
 		if (((opcode & 0x00600000) == 0x00100000) && (x == 1))
 		{
 			uint8_t Rd, Rm, Rs;
@@ -1922,7 +1922,7 @@ int evaluate_load_store_multiple_thumb(uint16_t opcode, uint32_t address, arm_in
 		if (reg_list & (1 << i))
 			reg_names_p += snprintf(reg_names_p, (reg_names + 40 - reg_names_p), "r%i, ", i);
 	}
-	if (reg_names_p>reg_names)
+	if (reg_names_p > reg_names)
 		reg_names_p[-2] = '\0';
 	else /* invalid op : no registers */
     		reg_names[0] = '\0';
-- 
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