From 237e894805dd757cc24029af1b4b1e824c51712b Mon Sep 17 00:00:00 2001 From: drath Date: Tue, 29 May 2007 11:23:42 +0000 Subject: - split fileio handling into fileio part and image handling - reworked etm/etb into a generic etm part with trace capture drivers (currently only etb supported) - added XScale debug handler binary to repository - added Thumb disassembling (thanks to Vincent Palatin for this patch) - added support for non-CFI compatible flashes to cfi driver (currently only SST39VFxxx devices supported) This checkin is experimental, not suitable for general use git-svn-id: svn://svn.berlios.de/openocd/trunk@155 b42882b7-edfa-0310-969c-e2dbd0fdcd60 --- src/target/arm_disassembler.h | 5 +++-- 1 file changed, 3 insertions(+), 2 deletions(-) (limited to 'src/target/arm_disassembler.h') diff --git a/src/target/arm_disassembler.h b/src/target/arm_disassembler.h index b55c8855..bdab113d 100644 --- a/src/target/arm_disassembler.h +++ b/src/target/arm_disassembler.h @@ -133,7 +133,7 @@ union arm_shifter_operand } immediate; struct { u8 Rm; - u8 shift; + u8 shift; /* 0: LSL, 1: LSR, 2: ASR, 3: ROR, 4: RRX */ u8 shift_imm; } immediate_shift; struct { @@ -164,7 +164,7 @@ typedef struct arm_load_store_instr_s u32 offset; struct { u8 Rm; - u8 shift; + u8 shift; /* 0: LSL, 1: LSR, 2: ASR, 3: ROR, 4: RRX */ u8 shift_imm; } reg; } offset; @@ -195,6 +195,7 @@ typedef struct arm_instruction_s } arm_instruction_t; extern int arm_evaluate_opcode(u32 opcode, u32 address, arm_instruction_t *instruction); +extern int thumb_evaluate_opcode(u16 opcode, u32 address, arm_instruction_t *instruction); #define COND(opcode) (arm_condition_strings[(opcode & 0xf0000000)>>28]) -- cgit v1.2.3