From 309870e414548e3cd6634819490239a2efb85a0e Mon Sep 17 00:00:00 2001 From: zwelch Date: Wed, 15 Jul 2009 23:39:37 +0000 Subject: David Brownell : Initial support for disassembling Thumb2 code. This works only for Cortex-M3 cores so far. Eventually other cores will also need Thumb2 support ... but they don't yet support any kind of disassembly. - Update the 16-bit Thumb decoder: * Understand CPS, REV*, SETEND, {U,S}XT{B,H} opcodes added by ARMv6. (It already seems to treat CPY as MOV.) * Understand CB, CBNZ, WFI, IT, and other opcodes added by in Thumb2. - A new Thumb2 instruction decode routine is provided. * This has a different signature: pass the target, not the instruction, so it can fetch a second halfword when needed. The instruction size is likewise returned to the caller. * 32-bit instructions are recognized but not yet decoded. - Start using the current "UAL" syntax in some cases. "SWI" is renamed as "SVC"; "LDMIA" as "LDM"; "STMIA" as "STM". - Define a new "cortex_m3 disassemble addr count" command to give access to this disassembly. Sanity checked against "objdump -d" output; a bunch of the new instructions checked out fine. git-svn-id: svn://svn.berlios.de/openocd/trunk@2530 b42882b7-edfa-0310-969c-e2dbd0fdcd60 --- src/target/arm_disassembler.h | 5 +++++ 1 file changed, 5 insertions(+) (limited to 'src/target/arm_disassembler.h') diff --git a/src/target/arm_disassembler.h b/src/target/arm_disassembler.h index a8b9aba1..b841d6cd 100644 --- a/src/target/arm_disassembler.h +++ b/src/target/arm_disassembler.h @@ -185,6 +185,9 @@ typedef struct arm_instruction_s char text[128]; uint32_t opcode; + /* return value ... Thumb-2 sizes vary */ + unsigned instruction_size; + union { arm_b_bl_bx_blx_instr_t b_bl_bx_blx; arm_data_proc_instr_t data_proc; @@ -196,6 +199,8 @@ typedef struct arm_instruction_s extern int arm_evaluate_opcode(uint32_t opcode, uint32_t address, arm_instruction_t *instruction); extern int thumb_evaluate_opcode(uint16_t opcode, uint32_t address, arm_instruction_t *instruction); +extern int thumb2_opcode(target_t *target, uint32_t address, + arm_instruction_t *instruction); extern int arm_access_size(arm_instruction_t *instruction); #define COND(opcode) (arm_condition_strings[(opcode & 0xf0000000) >> 28]) -- cgit v1.2.3