From a4a2808c2a849eddd5d7d454c048ffdfd89ca9c6 Mon Sep 17 00:00:00 2001 From: David Brownell Date: Mon, 7 Dec 2009 14:54:12 -0800 Subject: ARM: move opcode macros to Move the ARM opcode macros from , and a few Thumb2 ones from , to more appropriate homes in a new file. Removed duplicate opcodes from that v7m/Thumb2 set. Protected a few macro argument references by adding missing parentheses. Tightening up some of the line lengths turned up a curious artifact: the macros for the Thumb opcodes are all 32 bits wide, not 16 bits. There's currently no explanation for why it's done that way... Signed-off-by: David Brownell --- src/target/arm_opcodes.h | 260 +++++++++++++++++++++++++++++++++++++++++++++++ 1 file changed, 260 insertions(+) create mode 100644 src/target/arm_opcodes.h (limited to 'src/target/arm_opcodes.h') diff --git a/src/target/arm_opcodes.h b/src/target/arm_opcodes.h new file mode 100644 index 00000000..b3b51433 --- /dev/null +++ b/src/target/arm_opcodes.h @@ -0,0 +1,260 @@ +/* + * Copyright (C) 2005 by Dominic Rath + * Dominic.Rath@gmx.de + * + * Copyright (C) 2008 by Spencer Oliver + * spen@spen-soft.co.uk + * + * Copyright (C) 2009 by Øyvind Harboe + * oyvind.harboe@zylin.com + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the + * Free Software Foundation, Inc., + * 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. + */ +#ifndef __ARM_OPCODES_H +#define __ARM_OPCODES_H + +/* ARM mode instructions */ + +/* Store multiple increment after + * Rn: base register + * List: for each bit in list: store register + * S: in priviledged mode: store user-mode registers + * W = 1: update the base register. W = 0: leave the base register untouched + */ +#define ARMV4_5_STMIA(Rn, List, S, W) \ + (0xe8800000 | ((S) << 22) | ((W) << 21) | ((Rn) << 16) | (List)) + +/* Load multiple increment after + * Rn: base register + * List: for each bit in list: store register + * S: in priviledged mode: store user-mode registers + * W = 1: update the base register. W = 0: leave the base register untouched + */ +#define ARMV4_5_LDMIA(Rn, List, S, W) \ + (0xe8900000 | ((S) << 22) | ((W) << 21) | ((Rn) << 16) | (List)) + +/* MOV r8, r8 */ +#define ARMV4_5_NOP (0xe1a08008) + +/* Move PSR to general purpose register + * R = 1: SPSR R = 0: CPSR + * Rn: target register + */ +#define ARMV4_5_MRS(Rn, R) (0xe10f0000 | ((R) << 22) | ((Rn) << 12)) + +/* Store register + * Rd: register to store + * Rn: base register + */ +#define ARMV4_5_STR(Rd, Rn) (0xe5800000 | ((Rd) << 12) | ((Rn) << 16)) + +/* Load register + * Rd: register to load + * Rn: base register + */ +#define ARMV4_5_LDR(Rd, Rn) (0xe5900000 | ((Rd) << 12) | ((Rn) << 16)) + +/* Move general purpose register to PSR + * R = 1: SPSR R = 0: CPSR + * Field: Field mask + * 1: control field 2: extension field 4: status field 8: flags field + * Rm: source register + */ +#define ARMV4_5_MSR_GP(Rm, Field, R) \ + (0xe120f000 | (Rm) | ((Field) << 16) | ((R) << 22)) +#define ARMV4_5_MSR_IM(Im, Rotate, Field, R) \ + (0xe320f000 | (Im) | ((Rotate) << 8) | ((Field) << 16) | ((R) << 22)) + +/* Load Register Halfword Immediate Post-Index + * Rd: register to load + * Rn: base register + */ +#define ARMV4_5_LDRH_IP(Rd, Rn) (0xe0d000b2 | ((Rd) << 12) | ((Rn) << 16)) + +/* Load Register Byte Immediate Post-Index + * Rd: register to load + * Rn: base register + */ +#define ARMV4_5_LDRB_IP(Rd, Rn) (0xe4d00001 | ((Rd) << 12) | ((Rn) << 16)) + +/* Store register Halfword Immediate Post-Index + * Rd: register to store + * Rn: base register + */ +#define ARMV4_5_STRH_IP(Rd, Rn) (0xe0c000b2 | ((Rd) << 12) | ((Rn) << 16)) + +/* Store register Byte Immediate Post-Index + * Rd: register to store + * Rn: base register + */ +#define ARMV4_5_STRB_IP(Rd, Rn) (0xe4c00001 | ((Rd) << 12) | ((Rn) << 16)) + +/* Branch (and Link) + * Im: Branch target (left-shifted by 2 bits, added to PC) + * L: 1: branch and link 0: branch only + */ +#define ARMV4_5_B(Im, L) (0xea000000 | (Im) | ((L) << 24)) + +/* Branch and exchange (ARM state) + * Rm: register holding branch target address + */ +#define ARMV4_5_BX(Rm) (0xe12fff10 | (Rm)) + +/* Move to ARM register from coprocessor + * CP: Coprocessor number + * op1: Coprocessor opcode + * Rd: destination register + * CRn: first coprocessor operand + * CRm: second coprocessor operand + * op2: Second coprocessor opcode + */ +#define ARMV4_5_MRC(CP, op1, Rd, CRn, CRm, op2) \ + (0xee100010 | (CRm) | ((op2) << 5) | ((CP) << 8) \ + | ((Rd) << 12) | ((CRn) << 16) | ((op1) << 21)) + +/* Move to coprocessor from ARM register + * CP: Coprocessor number + * op1: Coprocessor opcode + * Rd: destination register + * CRn: first coprocessor operand + * CRm: second coprocessor operand + * op2: Second coprocessor opcode + */ +#define ARMV4_5_MCR(CP, op1, Rd, CRn, CRm, op2) \ + (0xee000010 | (CRm) | ((op2) << 5) | ((CP) << 8) \ + | ((Rd) << 12) | ((CRn) << 16) | ((op1) << 21)) + +/* Breakpoint instruction (ARMv5) + * Im: 16-bit immediate + */ +#define ARMV5_BKPT(Im) (0xe1200070 | ((Im & 0xfff0) << 8) | (Im & 0xf)) + + +/* Thumb mode instructions + * + * FIXME there must be some reason all these opcodes are 32-bits + * not 16-bits ... this should get either an explanatory comment, + * or be changed not to duplicate the opcode. + */ + +/* Store register (Thumb mode) + * Rd: source register + * Rn: base register + */ +#define ARMV4_5_T_STR(Rd, Rn) \ + ((0x6000 | (Rd) | ((Rn) << 3)) | \ + ((0x6000 | (Rd) | ((Rn) << 3)) << 16)) + +/* Load register (Thumb state) + * Rd: destination register + * Rn: base register + */ +#define ARMV4_5_T_LDR(Rd, Rn) \ + ((0x6800 | ((Rn) << 3) | (Rd)) \ + | ((0x6800 | ((Rn) << 3) | (Rd)) << 16)) + +/* Load multiple (Thumb state) + * Rn: base register + * List: for each bit in list: store register + */ +#define ARMV4_5_T_LDMIA(Rn, List) \ + ((0xc800 | ((Rn) << 8) | (List)) \ + | ((0xc800 | ((Rn) << 8) | (List)) << 16)) + +/* Load register with PC relative addressing + * Rd: register to load + */ +#define ARMV4_5_T_LDR_PCREL(Rd) \ + ((0x4800 | ((Rd) << 8)) \ + | ((0x4800 | ((Rd) << 8)) << 16)) + +/* Move hi register (Thumb mode) + * Rd: destination register + * Rm: source register + */ +#define ARMV4_5_T_MOV(Rd, Rm) \ + ((0x4600 | ((Rd) & 0x7) | (((Rd) & 0x8) << 4) | \ + (((Rm) & 0x7) << 3) | (((Rm) & 0x8) << 3)) \ + | ((0x4600 | ((Rd) & 0x7) | (((Rd) & 0x8) << 4) | \ + (((Rm) & 0x7) << 3) | (((Rm) & 0x8) << 3)) << 16)) + +/* No operation (Thumb mode) + * NOTE: this is "MOV r8, r8" ... Thumb2 adds two + * architected NOPs, 16-bit and 32-bit. + */ +#define ARMV4_5_T_NOP (0x46c0 | (0x46c0 << 16)) + +/* Move immediate to register (Thumb state) + * Rd: destination register + * Im: 8-bit immediate value + */ +#define ARMV4_5_T_MOV_IM(Rd, Im) \ + ((0x2000 | ((Rd) << 8) | (Im)) \ + | ((0x2000 | ((Rd) << 8) | (Im)) << 16)) + +/* Branch and Exchange + * Rm: register containing branch target + */ +#define ARMV4_5_T_BX(Rm) \ + ((0x4700 | ((Rm) << 3)) \ + | ((0x4700 | ((Rm) << 3)) << 16)) + +/* Branch (Thumb state) + * Imm: Branch target + */ +#define ARMV4_5_T_B(Imm) \ + ((0xe000 | (Imm)) \ + | ((0xe000 | (Imm)) << 16)) + +/* Breakpoint instruction (ARMv5) (Thumb state) + * Im: 8-bit immediate + */ +#define ARMV5_T_BKPT(Im) \ + ((0xbe00 | (Im)) \ + | ((0xbe00 | (Im)) << 16)) + +/* Move to Register from Special Register + * 32 bit Thumb2 instruction + * Rd: destination register + * SYSm: source special register + */ +#define ARM_T2_MRS(Rd, SYSm) \ + ((0xF3EF) | ((0x8000 | (Rd << 8) | SYSm) << 16)) + +/* Move from Register from Special Register + * 32 bit Thumb2 instruction + * Rd: source register + * SYSm: destination special register + */ +#define ARM_T2_MSR(SYSm, Rn) \ + ((0xF380 | (Rn << 8)) | ((0x8800 | SYSm) << 16)) + +/* Change Processor State. + * 16 bit Thumb2 instruction + * Rd: source register + * IF: A_FLAG and/or I_FLAG and/or F_FLAG + */ +#define A_FLAG 4 +#define I_FLAG 2 +#define F_FLAG 1 +#define ARM_T2_CPSID(IF) \ + ((0xB660 | (1 << 8) | ((IF)&0x3)) \ + | ((0xB660 | (1 << 8) | ((IF)&0x3)) << 16)) +#define ARM_T2_CPSIE(IF) \ + ((0xB660 | (0 << 8) | ((IF)&0x3)) \ + | ((0xB660 | (0 << 8) | ((IF)&0x3)) << 16)) + +#endif /* __ARM_OPCODES_H */ -- cgit v1.2.3