From 177bbd8891ae737ea7f8c0791a6236f72cedee40 Mon Sep 17 00:00:00 2001 From: David Brownell Date: Tue, 1 Dec 2009 00:48:53 -0800 Subject: target: "mcr" and "mrc" are ARM-specific Switch "mrc" and "mcr" commands to be toplevel ARM operations, as they should initially have been. Correct the usage message for both commands: it matches ARM documentation (as one wants!) instead of reordering them to match the funky mrc() and mcr() method usage (sigh). For Cortex-A8: restore a line that got accidentally dropped, so the secure monitor mode shadow registers will show again. Signed-off-by: David Brownell --- src/target/armv4_5.h | 15 +++++++++++++++ 1 file changed, 15 insertions(+) (limited to 'src/target/armv4_5.h') diff --git a/src/target/armv4_5.h b/src/target/armv4_5.h index 822d1439..7229a6c0 100644 --- a/src/target/armv4_5.h +++ b/src/target/armv4_5.h @@ -112,11 +112,26 @@ struct arm /** Handle for the Embedded Trace Module, if one is present. */ struct etm_context *etm; + /* FIXME all these methods should take "struct arm *" not target */ + int (*full_context)(struct target *target); int (*read_core_reg)(struct target *target, struct reg *reg, int num, enum armv4_5_mode mode); int (*write_core_reg)(struct target *target, struct reg *reg, int num, enum armv4_5_mode mode, uint32_t value); + + /** Read coprocessor register. */ + int (*mrc)(struct target *target, int cpnum, + uint32_t op1, uint32_t op2, + uint32_t CRn, uint32_t CRm, + uint32_t *value); + + /* Write coprocessor register. */ + int (*mcr)(struct target *target, int cpnum, + uint32_t op1, uint32_t op2, + uint32_t CRn, uint32_t CRm, + uint32_t value); + void *arch_info; }; -- cgit v1.2.3