From 5706fd7860ea01c591ecf74880a5a5e04e6df22e Mon Sep 17 00:00:00 2001 From: David Brownell Date: Sun, 22 Nov 2009 03:37:21 -0800 Subject: ARM: simplify CPSR handling Stash a pointer to the CPSR in the "struct arm", to help get rid of the (common) references to its index in the register cache. This removes almost all references to CPSR offsets outside of the toplevel ARM code ... except a pair related to the current ARM11 "simulator" logic (which should be removable soonish). This is a net minor code shrink of a few hundred bytes of object code, and also makes the code more readable. Signed-off-by: David Brownell --- src/target/armv4_5.h | 16 +++++----------- 1 file changed, 5 insertions(+), 11 deletions(-) (limited to 'src/target/armv4_5.h') diff --git a/src/target/armv4_5.h b/src/target/armv4_5.h index c8fc5580..5bce30b3 100644 --- a/src/target/armv4_5.h +++ b/src/target/armv4_5.h @@ -62,17 +62,8 @@ extern const int armv4_5_core_reg_map[8][17]; #define ARMV4_5_CORE_REG_MODE(cache, mode, num) \ cache->reg_list[armv4_5_core_reg_map[armv4_5_mode_to_number(mode)][num]] -/* offsets into armv4_5 core register cache */ -enum -{ - ARMV4_5_CPSR = 31, - ARMV4_5_SPSR_FIQ = 32, - ARMV4_5_SPSR_IRQ = 33, - ARMV4_5_SPSR_SVC = 34, - ARMV4_5_SPSR_ABT = 35, - ARMV4_5_SPSR_UND = 36, - ARM_SPSR_MON = 39, -}; +/* offset into armv4_5 core register cache -- OBSOLETE, DO NOT USE! */ +enum { ARMV4_5_CPSR = 31, }; #define ARMV4_5_COMMON_MAGIC 0x0A450A45 @@ -91,6 +82,9 @@ struct arm int common_magic; struct reg_cache *core_cache; + /** Handle to the CPSR; valid in all core modes. */ + struct reg *cpsr; + /** * Indicates what registers are in the ARM state core register set. * ARMV4_5_MODE_ANY indicates the standard set of 37 registers, -- cgit v1.2.3