From 8a6d4ced4c0d17626c3875d5f8819efa3ac0f155 Mon Sep 17 00:00:00 2001 From: David Brownell Date: Wed, 18 Nov 2009 13:23:00 -0800 Subject: ARM: setup "secure monitor mode" shadow regs Teach the "armv4_5" register code to understand about the secure monitor mode: - Add the other three shadowed registers to the arrays - Support another internal mode number (sigh) in mappings - Catch malloc/calloc failures building that register cache This should kick in for Cortex-A8 and ARM1176. Signed-off-by: David Brownell --- src/target/armv4_5.h | 5 +++-- 1 file changed, 3 insertions(+), 2 deletions(-) (limited to 'src/target/armv4_5.h') diff --git a/src/target/armv4_5.h b/src/target/armv4_5.h index f9aa4baf..e3d053c9 100644 --- a/src/target/armv4_5.h +++ b/src/target/armv4_5.h @@ -56,7 +56,7 @@ typedef enum armv4_5_state extern char* armv4_5_state_strings[]; -extern const int armv4_5_core_reg_map[7][17]; +extern const int armv4_5_core_reg_map[8][17]; #define ARMV4_5_CORE_REG_MODE(cache, mode, num) \ cache->reg_list[armv4_5_core_reg_map[armv4_5_mode_to_number(mode)][num]] @@ -69,7 +69,8 @@ enum ARMV4_5_SPSR_IRQ = 33, ARMV4_5_SPSR_SVC = 34, ARMV4_5_SPSR_ABT = 35, - ARMV4_5_SPSR_UND = 36 + ARMV4_5_SPSR_UND = 36, + ARM_SPSR_MON = 39, }; #define ARMV4_5_COMMON_MAGIC 0x0A450A45 -- cgit v1.2.3