From a28eaa85f73759bb189a46308642502c9fa5aa4b Mon Sep 17 00:00:00 2001
From: duane <duane@b42882b7-edfa-0310-969c-e2dbd0fdcd60>
Date: Sun, 30 Nov 2008 22:25:43 +0000
Subject: jtag newtap change & huge manual update

git-svn-id: svn://svn.berlios.de/openocd/trunk@1194 b42882b7-edfa-0310-969c-e2dbd0fdcd60
---
 src/target/board/eir.cfg | 94 ++++++++++++++++++++++++++++++++++++++++++++++++
 1 file changed, 94 insertions(+)
 create mode 100755 src/target/board/eir.cfg

(limited to 'src/target/board/eir.cfg')

diff --git a/src/target/board/eir.cfg b/src/target/board/eir.cfg
new file mode 100755
index 00000000..08765658
--- /dev/null
+++ b/src/target/board/eir.cfg
@@ -0,0 +1,94 @@
+# Elector Internet Radio board
+# http://www.ethernut.de/en/hardware/eir/index.html
+
+source [find target/sam7se512.cfg]
+
+$_TARGETNAME configure -event reset-init {
+	# WDT_MR, disable watchdog 
+	mww 0xFFFFFD44 0x00008000
+
+	# RSTC_MR, enable user reset
+	mww 0xfffffd08 0xa5000001
+
+	# CKGR_MOR
+	mww 0xFFFFFC20 0x00000601
+	sleep 10
+
+	# CKGR_PLLR
+	mww 0xFFFFFC2C 0x00481c0e
+	sleep 10
+
+	# PMC_MCKR
+	mww 0xFFFFFC30 0x00000007
+	sleep 10
+
+	# PMC_IER
+	mww 0xFFFFFF60 0x00480100
+
+	#
+	# Enable SDRAM interface.
+	#
+
+	# Enable SDRAM control at PIO A.
+	mww 0xfffff474 0x3f800000 # PIO_BSR_OFF
+	mww 0xfffff404 0x3f800000 # PIO_PDR_OFF
+
+	# Enable address bus (A0, A2-A11, A13-A17) at PIO B
+	mww 0xfffff674 0x0003effd # PIO_BSR_OFF
+	mww 0xfffff604 0x0003effd # PIO_PDR_OFF
+
+	# Enable 16 bit data bus at PIO C
+	mww 0xfffff870 0x0000ffff # PIO_ASR_OFF
+	mww 0xfffff804 0x0000ffff # PIO_PDR_OFF
+
+	# Enable SDRAM chip select
+	mww 0xffffff80 0x00000002 # EBI_CSA_OFF
+
+	# Set SDRAM characteristics in configuration register.
+	# Hard coded values for MT48LC32M16A2 with 48MHz CPU.
+	mww 0xffffffb8 0x2192215a # SDRAMC_CR_OFF
+	sleep 10
+
+	# Issue 16 bit SDRAM command: NOP
+	mww 0xffffffb0 0x00000011 # SDRAMC_MR_OFF
+	mww 0x20000000 0x00000000 
+
+	# Issue 16 bit SDRAM command: Precharge all
+	mww 0xffffffb0 0x00000012 # SDRAMC_MR_OFF
+	mww 0x20000000 0x00000000 
+
+	# Issue 8 auto-refresh cycles
+	mww 0xffffffb0 0x00000014 # SDRAMC_MR_OFF
+	mww 0x20000000 0x00000000 
+	mww 0xffffffb0 0x00000014 # SDRAMC_MR_OFF
+	mww 0x20000000 0x00000000 
+	mww 0xffffffb0 0x00000014 # SDRAMC_MR_OFF
+	mww 0x20000000 0x00000000 
+	mww 0xffffffb0 0x00000014 # SDRAMC_MR_OFF
+	mww 0x20000000 0x00000000 
+	mww 0xffffffb0 0x00000014 # SDRAMC_MR_OFF
+	mww 0x20000000 0x00000000 
+	mww 0xffffffb0 0x00000014 # SDRAMC_MR_OFF
+	mww 0x20000000 0x00000000 
+	mww 0xffffffb0 0x00000014 # SDRAMC_MR_OFF
+	mww 0x20000000 0x00000000 
+	mww 0xffffffb0 0x00000014 # SDRAMC_MR_OFF
+	mww 0x20000000 0x00000000 
+
+	# Issue 16 bit SDRAM command: Set mode register  
+	mww 0xffffffb0 0x00000013 # SDRAMC_MR_OFF
+	mww 0x20000014 0xcafedede
+
+	# Set refresh rate count ???
+	mww 0xffffffb4 0x00000013 # SDRAMC_TR_OFF
+
+	# Issue 16 bit SDRAM command: Normal mode
+	mww 0xffffffb0 0x00000010 # SDRAMC_MR_OFF
+	mww 0x20000000 0x00000180
+
+	#
+	# Enable external reset key.
+	#
+	mww 0xfffffd08 0xa5000001
+}
+
-- 
cgit v1.2.3