From dd9894f481d127266c201d7075ecbdd34b034124 Mon Sep 17 00:00:00 2001 From: David Brownell Date: Sun, 22 Nov 2009 03:41:14 -0800 Subject: ARM: arm_set_cpsr() handles T and J bits Have arm_set_cpsr() handle the two core state flags, updating the CPU state. This eliminates code in various debug_entry() paths, and marginally improves handling of the J bit. Catch and comment a few holes in the handling of the J bit on ARM926ejs cores ... it's unlikely our users will care about Jazelle mode, but we can at least warn of Impending Doom. If anyone does use it, these breadcrumbs may help them to find the right path through the code. Signed-off-by: David Brownell --- src/target/cortex_a8.c | 23 ----------------------- 1 file changed, 23 deletions(-) (limited to 'src/target/cortex_a8.c') diff --git a/src/target/cortex_a8.c b/src/target/cortex_a8.c index 71de3b79..fa26b6ab 100644 --- a/src/target/cortex_a8.c +++ b/src/target/cortex_a8.c @@ -650,29 +650,6 @@ static int cortex_a8_debug_entry(struct target *target) arm_set_cpsr(armv4_5, cpsr); - i = (cpsr >> 5) & 1; /* T */ - i |= (cpsr >> 23) & 1; /* J << 1 */ - switch (i) { - case 0: /* J = 0, T = 0 */ - armv4_5->core_state = ARMV4_5_STATE_ARM; - break; - case 1: /* J = 0, T = 1 */ - armv4_5->core_state = ARMV4_5_STATE_THUMB; - break; - case 2: /* J = 1, T = 0 */ - LOG_WARNING("Jazelle state -- not handled"); - armv4_5->core_state = ARMV4_5_STATE_JAZELLE; - break; - case 3: /* J = 1, T = 1 */ - /* ThumbEE is very much like Thumb, but some of the - * instructions are different. Single stepping and - * breakpoints need updating... - */ - LOG_WARNING("ThumbEE -- incomplete support"); - armv4_5->core_state = ARM_STATE_THUMB_EE; - break; - } - /* update cache */ for (i = 0; i <= ARM_PC; i++) { -- cgit v1.2.3