From 9c3dec377eb6eb822b85fa107ade2a62c9e1cfd1 Mon Sep 17 00:00:00 2001 From: ntfreak Date: Thu, 10 Apr 2008 11:43:48 +0000 Subject: - single core context used, removed debug context as thought unnecessary. - DCRDR now used to access special core registers - info is currently omitted from the cortex_m3 TRM ARM have told me this is the preferred access method and the docs will be updated soon. - now checks for User Thread Mode and Thread mode when halted. - removed repeated function declarations from command.c - cortex_m3_prepare_reset_halt removed, updated cortex_m3_assert_reset to suit git-svn-id: svn://svn.berlios.de/openocd/trunk@558 b42882b7-edfa-0310-969c-e2dbd0fdcd60 --- src/target/cortex_m3.h | 1 - 1 file changed, 1 deletion(-) (limited to 'src/target/cortex_m3.h') diff --git a/src/target/cortex_m3.h b/src/target/cortex_m3.h index 17c2b47b..0072e84b 100644 --- a/src/target/cortex_m3.h +++ b/src/target/cortex_m3.h @@ -173,7 +173,6 @@ int cortex_m3_step(struct target_s *target, int current, u32 address, int handle int cortex_m3_assert_reset(target_t *target); int cortex_m3_deassert_reset(target_t *target); int cortex_m3_soft_reset_halt(struct target_s *target); -int cortex_m3_prepare_reset_halt(struct target_s *target); int cortex_m3_read_memory(struct target_s *target, u32 address, u32 size, u32 count, u8 *buffer); int cortex_m3_write_memory(struct target_s *target, u32 address, u32 size, u32 count, u8 *buffer); -- cgit v1.2.3