From 3aa95240ece4c99fdb1b5d33e4153d96d3f278ee Mon Sep 17 00:00:00 2001 From: oharboe Date: Wed, 16 Apr 2008 07:34:22 +0000 Subject: fix SEGFAULT regression in cortex after TRST fixes git-svn-id: svn://svn.berlios.de/openocd/trunk@583 b42882b7-edfa-0310-969c-e2dbd0fdcd60 --- src/target/cortex_m3.c | 20 +++++++++++++++++--- src/target/cortex_swjdp.c | 10 +++++++--- src/target/target/stm32.cfg | 2 +- 3 files changed, 25 insertions(+), 7 deletions(-) (limited to 'src/target') diff --git a/src/target/cortex_m3.c b/src/target/cortex_m3.c index 6bdb1df6..b330fee3 100644 --- a/src/target/cortex_m3.c +++ b/src/target/cortex_m3.c @@ -51,6 +51,7 @@ int cortex_m3_quit(); int cortex_m3_load_core_reg_u32(target_t *target, enum armv7m_regtype type, u32 num, u32 *value); int cortex_m3_store_core_reg_u32(target_t *target, enum armv7m_regtype type, u32 num, u32 value); int cortex_m3_target_request_data(target_t *target, u32 size, u8 *buffer); +int cortex_m3_examine(struct command_context_s *cmd_ctx, struct target_s *target); target_type_t cortexm3_target = { @@ -86,6 +87,7 @@ target_type_t cortexm3_target = .register_commands = cortex_m3_register_commands, .target_command = cortex_m3_target_command, .init_target = cortex_m3_init_target, + .examine = cortex_m3_examine, .quit = cortex_m3_quit }; @@ -1227,6 +1229,13 @@ void cortex_m3_build_reg_cache(target_t *target) int cortex_m3_init_target(struct command_context_s *cmd_ctx, struct target_s *target) { + cortex_m3_build_reg_cache(target); + return ERROR_OK; +} + +int cortex_m3_examine(struct command_context_s *cmd_ctx, struct target_s *target) +{ + int retval; u32 cpuid, fpcr, dwtcr, ictr; int i; @@ -1234,12 +1243,16 @@ int cortex_m3_init_target(struct command_context_s *cmd_ctx, struct target_s *ta armv7m_common_t *armv7m = target->arch_info; cortex_m3_common_t *cortex_m3 = armv7m->arch_info; swjdp_common_t *swjdp = &cortex_m3->swjdp_info; + + target->type->examined = 1; - cortex_m3_build_reg_cache(target); - ahbap_debugport_init(swjdp); + if ((retval=ahbap_debugport_init(swjdp))!=ERROR_OK) + return retval; /* Read from Device Identification Registers */ - target_read_u32(target, CPUID, &cpuid); + if ((retval=target_read_u32(target, CPUID, &cpuid))!=ERROR_OK) + return retval; + if (((cpuid >> 4) & 0xc3f) == 0xc23) LOG_DEBUG("CORTEX-M3 processor detected"); LOG_DEBUG("cpuid: 0x%8.8x", cpuid); @@ -1280,6 +1293,7 @@ int cortex_m3_init_target(struct command_context_s *cmd_ctx, struct target_s *ta return ERROR_OK; } + int cortex_m3_quit() { diff --git a/src/target/cortex_swjdp.c b/src/target/cortex_swjdp.c index d1983ec5..dc50fea1 100644 --- a/src/target/cortex_swjdp.c +++ b/src/target/cortex_swjdp.c @@ -941,6 +941,7 @@ int ahbap_debugport_init(swjdp_common_t *swjdp) u32 idreg, romaddr, dummy; u32 ctrlstat; int cnt = 0; + int retval; LOG_DEBUG(" "); @@ -955,14 +956,16 @@ int ahbap_debugport_init(swjdp_common_t *swjdp) swjdp_write_dpacc(swjdp, swjdp->dp_ctrl_stat, DP_CTRL_STAT); swjdp_read_dpacc(swjdp, &ctrlstat, DP_CTRL_STAT); - jtag_execute_queue(); + if ((retval=jtag_execute_queue())!=ERROR_OK) + return retval; /* Check that we have debug power domains activated */ while (!(ctrlstat & CDBGPWRUPACK) && (cnt++ < 10)) { LOG_DEBUG("swjdp: wait CDBGPWRUPACK"); swjdp_read_dpacc(swjdp, &ctrlstat, DP_CTRL_STAT); - jtag_execute_queue(); + if ((retval=jtag_execute_queue())!=ERROR_OK) + return retval; usleep(10000); } @@ -970,7 +973,8 @@ int ahbap_debugport_init(swjdp_common_t *swjdp) { LOG_DEBUG("swjdp: wait CSYSPWRUPACK"); swjdp_read_dpacc(swjdp, &ctrlstat, DP_CTRL_STAT); - jtag_execute_queue(); + if ((retval=jtag_execute_queue())!=ERROR_OK) + return retval; usleep(10000); } diff --git a/src/target/target/stm32.cfg b/src/target/target/stm32.cfg index 8a93087d..371e4ab3 100644 --- a/src/target/target/stm32.cfg +++ b/src/target/target/stm32.cfg @@ -11,7 +11,7 @@ jtag_device 5 0x1 0x1 0x1e #target #target arm7tdmi -target cortex_m3 little reset_init 0 +target cortex_m3 little reset_halt 0 run_and_halt_time 0 30 working_area 0 0x20000000 16384 nobackup -- cgit v1.2.3