From 4411c2643e41d023a1909b1040361912422be6c0 Mon Sep 17 00:00:00 2001
From: oharboe <oharboe@b42882b7-edfa-0310-969c-e2dbd0fdcd60>
Date: Wed, 26 Mar 2008 13:29:48 +0000
Subject: TAP_SD/SI are now forbidden end states. jtag_add_reset() now returns
 void streamlining the API

git-svn-id: svn://svn.berlios.de/openocd/trunk@525 b42882b7-edfa-0310-969c-e2dbd0fdcd60
---
 src/target/arm7_9_common.c | 54 +++++++++++++---------------------------------
 src/target/cortex_m3.c     | 51 +++++++++++--------------------------------
 2 files changed, 28 insertions(+), 77 deletions(-)

(limited to 'src/target')

diff --git a/src/target/arm7_9_common.c b/src/target/arm7_9_common.c
index 4b393cc2..4208f38f 100644
--- a/src/target/arm7_9_common.c
+++ b/src/target/arm7_9_common.c
@@ -735,10 +735,14 @@ int arm7_9_poll(target_t *target)
 
 int arm7_9_assert_reset(target_t *target)
 {
-	int retval;
-	
 	LOG_DEBUG("target->state: %s", target_state_strings[target->state]);
 	
+	if (!(jtag_reset_config & RESET_HAS_SRST))
+	{
+		LOG_ERROR("Can't assert SRST");
+		return ERROR_FAIL;
+	}
+	
 	if (target->state == TARGET_HALTED || target->state == TARGET_UNKNOWN)
 	{
 		/* if the target wasn't running, there might be working areas allocated */
@@ -746,46 +750,18 @@ int arm7_9_assert_reset(target_t *target)
 		
 		/* assert SRST and TRST */
 		/* system would get ouf sync if we didn't reset test-logic, too */
-		if ((retval = jtag_add_reset(1, 1)) != ERROR_OK)
-		{
-			if (retval == ERROR_JTAG_RESET_CANT_SRST)
-			{
-				return retval;
-			}
-			else
-			{
-				LOG_ERROR("unknown error");
-				exit(-1);
-			}
-		}
+		jtag_add_reset(1, 1);
+		
 		jtag_add_sleep(5000);
-		if ((retval = jtag_add_reset(0, 1)) != ERROR_OK)
-		{
-			if (retval == ERROR_JTAG_RESET_WOULD_ASSERT_TRST)
-			{
-				retval = jtag_add_reset(1, 1);
-			}
-		}
+		
 	}
-	else
+	
+	if (jtag_reset_config & RESET_SRST_PULLS_TRST)
 	{
-		if ((retval = jtag_add_reset(0, 1)) != ERROR_OK)
-		{
-			if (retval == ERROR_JTAG_RESET_WOULD_ASSERT_TRST)
-			{
-				retval = jtag_add_reset(1, 1);
-			}
-			
-			if (retval == ERROR_JTAG_RESET_CANT_SRST)
-			{
-				return retval;
-			}
-			else if (retval != ERROR_OK)
-			{
-				LOG_ERROR("unknown error");
-				exit(-1);
-			}
-		}
+		jtag_add_reset(1, 1);
+	} else
+	{
+		jtag_add_reset(0, 1);
 	}
 	
 	target->state = TARGET_RESET;
diff --git a/src/target/cortex_m3.c b/src/target/cortex_m3.c
index aba15e7f..aa674745 100644
--- a/src/target/cortex_m3.c
+++ b/src/target/cortex_m3.c
@@ -701,13 +701,18 @@ int cortex_m3_step(struct target_s *target, int current, u32 address, int handle
 
 int cortex_m3_assert_reset(target_t *target)
 {
-	int retval;
 	armv7m_common_t *armv7m = target->arch_info;
 	cortex_m3_common_t *cortex_m3 = armv7m->arch_info;
 	swjdp_common_t *swjdp = &cortex_m3->swjdp_info;
 	
 	LOG_DEBUG("target->state: %s", target_state_strings[target->state]);
 	
+	if (!(jtag_reset_config & RESET_HAS_SRST))
+	{
+		LOG_ERROR("Can't assert SRST");
+		return ERROR_FAIL;
+	}
+
 	ahbap_write_system_u32(swjdp, DCB_DCRDR, 0 );
 	
 	if (target->reset_mode == RESET_RUN)
@@ -727,46 +732,16 @@ int cortex_m3_assert_reset(target_t *target)
 	{
 		/* assert SRST and TRST */
 		/* system would get ouf sync if we didn't reset test-logic, too */
-		if ((retval = jtag_add_reset(1, 1)) != ERROR_OK)
-		{
-			if (retval == ERROR_JTAG_RESET_CANT_SRST)
-			{
-				return retval;
-			}
-			else
-			{
-				LOG_ERROR("unknown error");
-				exit(-1);
-			}
-		}
+		jtag_add_reset(1, 1);
 		jtag_add_sleep(5000);
-		if ((retval = jtag_add_reset(0, 1)) != ERROR_OK)
-		{
-			if (retval == ERROR_JTAG_RESET_WOULD_ASSERT_TRST)
-			{
-				retval = jtag_add_reset(1, 1);
-			}
-		}
 	}
-	else
+
+	if (jtag_reset_config & RESET_SRST_PULLS_TRST)
 	{
-		if ((retval = jtag_add_reset(0, 1)) != ERROR_OK)
-		{
-			if (retval == ERROR_JTAG_RESET_WOULD_ASSERT_TRST)
-			{
-				retval = jtag_add_reset(1, 1);
-			}
-			
-			if (retval == ERROR_JTAG_RESET_CANT_SRST)
-			{
-				return retval;
-			}
-			else if (retval != ERROR_OK)
-			{
-				LOG_ERROR("unknown error");
-				exit(-1);
-			}
-		}
+		jtag_add_reset(1, 1);
+	} else
+	{
+		jtag_add_reset(0, 1);
 	}
 	
 	target->state = TARGET_RESET;
-- 
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