From 81f238f522ecba6c24217d94b17086e2d4fcce59 Mon Sep 17 00:00:00 2001 From: Luca Ellero Date: Wed, 13 Apr 2011 18:55:18 +0000 Subject: Add opcodes for load/store registers words immediate post-indexed Signed-off-by: Luca Ellero --- src/target/arm_opcodes.h | 12 ++++++++++++ 1 file changed, 12 insertions(+) mode change 100644 => 100755 src/target/arm_opcodes.h (limited to 'src/target') diff --git a/src/target/arm_opcodes.h b/src/target/arm_opcodes.h old mode 100644 new mode 100755 index b77721e6..9a48e6d0 --- a/src/target/arm_opcodes.h +++ b/src/target/arm_opcodes.h @@ -86,6 +86,12 @@ #define ARMV4_5_MSR_IM(Im, Rotate, Field, R) \ (0xe320f000 | (Im) | ((Rotate) << 8) | ((Field) << 16) | ((R) << 22)) +/* Load Register Word Immediate Post-Index + * Rd: register to load + * Rn: base register + */ +#define ARMV4_5_LDRW_IP(Rd, Rn) (0xe4900004 | ((Rd) << 12) | ((Rn) << 16)) + /* Load Register Halfword Immediate Post-Index * Rd: register to load * Rn: base register @@ -98,6 +104,12 @@ */ #define ARMV4_5_LDRB_IP(Rd, Rn) (0xe4d00001 | ((Rd) << 12) | ((Rn) << 16)) +/* Store register Word Immediate Post-Index + * Rd: register to store + * Rn: base register + */ +#define ARMV4_5_STRW_IP(Rd, Rn) (0xe4800004 | ((Rd) << 12) | ((Rn) << 16)) + /* Store register Halfword Immediate Post-Index * Rd: register to store * Rn: base register -- cgit v1.2.3