From 84df52f9ea78e2d71bde648a16b69d80404c6421 Mon Sep 17 00:00:00 2001 From: zwelch Date: Tue, 23 Jun 2009 22:42:54 +0000 Subject: - Fixes '=' whitespace - Replace ')\(=\)\(\w\)' with ') \1 \2'. - Replace '\(\w\)\(=\)(' with '\1 \2 ('. - Replace '\(\w\)\(=\)\(\w\)' with '\1 \2 \3'. git-svn-id: svn://svn.berlios.de/openocd/trunk@2372 b42882b7-edfa-0310-969c-e2dbd0fdcd60 --- src/target/arm11_dbgtap.c | 2 +- src/target/arm720t.c | 4 +- src/target/arm7_9_common.c | 60 +++++++++++----------- src/target/arm7tdmi.c | 14 ++--- src/target/arm920t.c | 4 +- src/target/arm926ejs.c | 6 +-- src/target/arm9tdmi.c | 12 ++--- src/target/arm_adi_v5.c | 24 ++++----- src/target/arm_jtag.h | 8 +-- src/target/armv4_5.c | 6 +-- src/target/armv4_5.h | 8 +-- src/target/armv7m.c | 6 +-- src/target/cortex_m3.c | 8 +-- src/target/embeddedice.c | 4 +- src/target/etb.c | 4 +- src/target/etm.c | 8 +-- src/target/image.c | 18 +++---- src/target/mips32_dmaacc.c | 12 ++--- src/target/mips32_pracc.c | 18 +++---- src/target/mips_m4k.c | 2 +- src/target/target.c | 124 ++++++++++++++++++++++----------------------- src/target/target.h | 2 +- src/target/xscale.c | 78 ++++++++++++++-------------- 23 files changed, 216 insertions(+), 216 deletions(-) (limited to 'src/target') diff --git a/src/target/arm11_dbgtap.c b/src/target/arm11_dbgtap.c index 6a5b7ba2..e69d5988 100644 --- a/src/target/arm11_dbgtap.c +++ b/src/target/arm11_dbgtap.c @@ -237,7 +237,7 @@ int arm11_read_DSCR(arm11_common_t * arm11, uint32_t *value) arm11->last_dscr = dscr; - *value=dscr; + *value = dscr; return ERROR_OK; } diff --git a/src/target/arm720t.c b/src/target/arm720t.c index d709bacc..efca08dd 100644 --- a/src/target/arm720t.c +++ b/src/target/arm720t.c @@ -373,9 +373,9 @@ int arm720t_soft_reset_halt(struct target_s *target) return retval; } - long long then=timeval_ms(); + long long then = timeval_ms(); int timeout; - while (!(timeout=((timeval_ms()-then)>1000))) + while (!(timeout = ((timeval_ms()-then)>1000))) { if (buf_get_u32(dbg_stat->value, EICE_DBG_STATUS_DBGACK, 1) == 0) { diff --git a/src/target/arm7_9_common.c b/src/target/arm7_9_common.c index 2b278747..c4b7c6a1 100644 --- a/src/target/arm7_9_common.c +++ b/src/target/arm7_9_common.c @@ -118,11 +118,11 @@ static int arm7_9_set_software_breakpoints(arm7_9_common_t *arm7_9) /* pick a breakpoint unit */ if (!arm7_9->wp0_used) { - arm7_9->sw_breakpoints_added=1; + arm7_9->sw_breakpoints_added = 1; arm7_9->wp0_used = 3; } else if (!arm7_9->wp1_used) { - arm7_9->sw_breakpoints_added=2; + arm7_9->sw_breakpoints_added = 2; arm7_9->wp1_used = 3; } else @@ -218,7 +218,7 @@ int arm7_9_set_breakpoint(struct target_s *target, breakpoint_t *breakpoint) { armv4_5_common_t *armv4_5 = target->arch_info; arm7_9_common_t *arm7_9 = armv4_5->arch_info; - int retval=ERROR_OK; + int retval = ERROR_OK; if (target->state != TARGET_HALTED) { @@ -259,11 +259,11 @@ int arm7_9_set_breakpoint(struct target_s *target, breakpoint_t *breakpoint) return ERROR_OK; } - retval=jtag_execute_queue(); + retval = jtag_execute_queue(); } else if (breakpoint->type == BKPT_SOFT) { - if ((retval=arm7_9_set_software_breakpoints(arm7_9)) != ERROR_OK) + if ((retval = arm7_9_set_software_breakpoints(arm7_9)) != ERROR_OK) return retval; /* did we already set this breakpoint? */ @@ -700,9 +700,9 @@ int arm7_9_execute_sys_speed(struct target_s *target) } arm_jtag_set_instr(jtag_info, 0x4, NULL); - long long then=timeval_ms(); + long long then = timeval_ms(); int timeout; - while (!(timeout=((timeval_ms()-then)>1000))) + while (!(timeout = ((timeval_ms()-then)>1000))) { /* read debug status register */ embeddedice_read_reg(dbg_stat); @@ -738,7 +738,7 @@ int arm7_9_execute_sys_speed(struct target_s *target) */ int arm7_9_execute_fast_sys_speed(struct target_s *target) { - static int set=0; + static int set = 0; static uint8_t check_value[4], check_mask[4]; armv4_5_common_t *armv4_5 = target->arch_info; @@ -764,7 +764,7 @@ int arm7_9_execute_fast_sys_speed(struct target_s *target) * */ buf_set_u32(check_value, 0, 32, 0x9); buf_set_u32(check_mask, 0, 32, 0x9); - set=1; + set = 1; } /* read debug status register */ @@ -900,7 +900,7 @@ int arm7_9_poll(target_t *target) } if ((target->state == TARGET_RUNNING) || (target->state == TARGET_RESET)) { - int check_pc=0; + int check_pc = 0; if (target->state == TARGET_RESET) { if (target->reset_halt) @@ -1042,7 +1042,7 @@ int arm7_9_assert_reset(target_t *target) */ int arm7_9_deassert_reset(target_t *target) { - int retval=ERROR_OK; + int retval = ERROR_OK; LOG_DEBUG("target->state: %s", Jim_Nvp_value2name_simple( nvp_target_state,target->state)->name); @@ -1057,12 +1057,12 @@ int arm7_9_deassert_reset(target_t *target) if ((retval = target_examine_one(target)) != ERROR_OK) return retval; - if ((retval=target_poll(target)) != ERROR_OK) + if ((retval = target_poll(target)) != ERROR_OK) { return retval; } - if ((retval=target_halt(target)) != ERROR_OK) + if ((retval = target_halt(target)) != ERROR_OK) { return retval; } @@ -1147,17 +1147,17 @@ int arm7_9_soft_reset_halt(struct target_s *target) int i; int retval; - if ((retval=target_halt(target)) != ERROR_OK) + if ((retval = target_halt(target)) != ERROR_OK) return retval; - long long then=timeval_ms(); + long long then = timeval_ms(); int timeout; - while (!(timeout=((timeval_ms()-then)>1000))) + while (!(timeout = ((timeval_ms()-then)>1000))) { if (buf_get_u32(dbg_stat->value, EICE_DBG_STATUS_DBGACK, 1) != 0) break; embeddedice_read_reg(dbg_stat); - if ((retval=jtag_execute_queue()) != ERROR_OK) + if ((retval = jtag_execute_queue()) != ERROR_OK) return retval; if (debug_level >= 3) { @@ -1428,7 +1428,7 @@ int arm7_9_debug_entry(target_t *target) if (armv4_5_mode_to_number(armv4_5->core_mode)==-1) return ERROR_FAIL; - for (i=0; i <= 15; i++) + for (i = 0; i <= 15; i++) { LOG_DEBUG("r%i: 0x%8.8" PRIx32 "", i, context[i]); buf_set_u32(ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5->core_mode, i).value, 0, 32, context[i]); @@ -2240,7 +2240,7 @@ int arm7_9_read_memory(struct target_s *target, uint32_t address, uint32_t size, reg[0] = address; arm7_9->write_core_regs(target, 0x1, reg); - int j=0; + int j = 0; switch (size) { @@ -2362,7 +2362,7 @@ int arm7_9_read_memory(struct target_s *target, uint32_t address, uint32_t size, if (armv4_5_mode_to_number(armv4_5->core_mode)==-1) return ERROR_FAIL; - for (i=0; i <= last_reg; i++) + for (i = 0; i <= last_reg; i++) ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5->core_mode, i).dirty = ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5->core_mode, i).valid; arm7_9->read_xpsr(target, &cpsr, 0); @@ -2545,7 +2545,7 @@ int arm7_9_write_memory(struct target_s *target, uint32_t address, uint32_t size if (armv4_5_mode_to_number(armv4_5->core_mode)==-1) return ERROR_FAIL; - for (i=0; i <= last_reg; i++) + for (i = 0; i <= last_reg; i++) ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5->core_mode, i).dirty = ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5->core_mode, i).valid; arm7_9->read_xpsr(target, &cpsr, 0); @@ -2576,12 +2576,12 @@ static int arm7_9_dcc_completion(struct target_s *target, uint32_t exit_point, i armv4_5_common_t *armv4_5 = target->arch_info; arm7_9_common_t *arm7_9 = armv4_5->arch_info; - if ((retval=target_wait_state(target, TARGET_DEBUG_RUNNING, 500)) != ERROR_OK) + if ((retval = target_wait_state(target, TARGET_DEBUG_RUNNING, 500)) != ERROR_OK) return retval; - int little=target->endianness == TARGET_LITTLE_ENDIAN; - int count=dcc_count; - uint8_t *buffer=dcc_buffer; + int little = target->endianness == TARGET_LITTLE_ENDIAN; + int count = dcc_count; + uint8_t *buffer = dcc_buffer; if (count>2) { /* Handle first & last using standard embeddedice_write_reg and the middle ones w/the @@ -2669,18 +2669,18 @@ int arm7_9_bulk_write_memory(target_t *target, uint32_t address, uint32_t count, buf_set_u32(reg_params[0].value, 0, 32, address); - dcc_count=count; - dcc_buffer=buffer; + dcc_count = count; + dcc_buffer = buffer; retval = armv4_5_run_algorithm_inner(target, 0, NULL, 1, reg_params, arm7_9->dcc_working_area->address, arm7_9->dcc_working_area->address+6*4, 20*1000, &armv4_5_info, arm7_9_dcc_completion); if (retval == ERROR_OK) { - uint32_t endaddress=buf_get_u32(reg_params[0].value, 0, 32); + uint32_t endaddress = buf_get_u32(reg_params[0].value, 0, 32); if (endaddress != (address+count*4)) { LOG_ERROR("DCC write failed, expected end address 0x%08" PRIx32 " got 0x%0" PRIx32 "", (address+count*4), endaddress); - retval=ERROR_FAIL; + retval = ERROR_FAIL; } } @@ -2734,7 +2734,7 @@ int arm7_9_checksum_memory(struct target_s *target, uint32_t address, uint32_t c /* convert flash writing code into a buffer in target endianness */ for (i = 0; i < (sizeof(arm7_9_crc_code)/sizeof(uint32_t)); i++) { - if ((retval=target_write_u32(target, crc_algorithm->address + i*sizeof(uint32_t), arm7_9_crc_code[i])) != ERROR_OK) + if ((retval = target_write_u32(target, crc_algorithm->address + i*sizeof(uint32_t), arm7_9_crc_code[i])) != ERROR_OK) { return retval; } diff --git a/src/target/arm7tdmi.c b/src/target/arm7tdmi.c index 541bede7..03c49663 100644 --- a/src/target/arm7tdmi.c +++ b/src/target/arm7tdmi.c @@ -216,9 +216,9 @@ int arm7tdmi_clock_data_in(arm_jtag_t *jtag_info, uint32_t *in) void arm_endianness(uint8_t *tmp, void *in, int size, int be, int flip) { - uint32_t readback=le_to_h_u32(tmp); + uint32_t readback = le_to_h_u32(tmp); if (flip) - readback=flip_u32(readback, 32); + readback = flip_u32(readback, 32); switch (size) { case 4: @@ -247,7 +247,7 @@ void arm_endianness(uint8_t *tmp, void *in, int size, int be, int flip) static int arm7endianness(jtag_callback_data_t arg, jtag_callback_data_t size, jtag_callback_data_t be, jtag_callback_data_t captured) { - uint8_t *in=(uint8_t *)arg; + uint8_t *in = (uint8_t *)arg; arm_endianness((uint8_t *)captured, in, (int)size, (int)be, 1); return ERROR_OK; } @@ -724,7 +724,7 @@ int arm7tdmi_examine(struct target_s *target) { /* get pointers to arch-specific information */ reg_cache_t **cache_p = register_get_last_cache_p(&target->reg_cache); - reg_cache_t *t=embeddedice_build_reg_cache(target, arm7_9); + reg_cache_t *t = embeddedice_build_reg_cache(target, arm7_9); if (t == NULL) return ERROR_FAIL; @@ -739,13 +739,13 @@ int arm7tdmi_examine(struct target_s *target) } target_set_examined(target); } - if ((retval=embeddedice_setup(target)) != ERROR_OK) + if ((retval = embeddedice_setup(target)) != ERROR_OK) return retval; - if ((retval=arm7_9_setup(target)) != ERROR_OK) + if ((retval = arm7_9_setup(target)) != ERROR_OK) return retval; if (arm7_9->etm_ctx) { - if ((retval=etm_setup(target)) != ERROR_OK) + if ((retval = etm_setup(target)) != ERROR_OK) return retval; } return ERROR_OK; diff --git a/src/target/arm920t.c b/src/target/arm920t.c index bf099e9d..10428a65 100644 --- a/src/target/arm920t.c +++ b/src/target/arm920t.c @@ -572,9 +572,9 @@ int arm920t_soft_reset_halt(struct target_s *target) return retval; } - long long then=timeval_ms(); + long long then = timeval_ms(); int timeout; - while (!(timeout=((timeval_ms()-then)>1000))) + while (!(timeout = ((timeval_ms()-then)>1000))) { if (buf_get_u32(dbg_stat->value, EICE_DBG_STATUS_DBGACK, 1) == 0) { diff --git a/src/target/arm926ejs.c b/src/target/arm926ejs.c index 5ffdeaff..0d6f0172 100644 --- a/src/target/arm926ejs.c +++ b/src/target/arm926ejs.c @@ -317,7 +317,7 @@ int arm926ejs_examine_debug_reason(target_t *target) * openocd development mailing list if you have hardware * to donate to look into this problem.... */ - LOG_ERROR("mystery debug reason MOE=0xc. Try issuing a resume + halt."); + LOG_ERROR("mystery debug reason MOE = 0xc. Try issuing a resume + halt."); target->debug_reason = DBG_REASON_DBGRQ; retval = ERROR_TARGET_FAILURE; break; @@ -572,9 +572,9 @@ int arm926ejs_soft_reset_halt(struct target_s *target) return retval; } - long long then=timeval_ms(); + long long then = timeval_ms(); int timeout; - while (!(timeout=((timeval_ms()-then)>1000))) + while (!(timeout = ((timeval_ms()-then)>1000))) { if (buf_get_u32(dbg_stat->value, EICE_DBG_STATUS_DBGACK, 1) == 0) { diff --git a/src/target/arm9tdmi.c b/src/target/arm9tdmi.c index 577a4252..fac0c8db 100644 --- a/src/target/arm9tdmi.c +++ b/src/target/arm9tdmi.c @@ -203,7 +203,7 @@ int arm9tdmi_clock_out(arm_jtag_t *jtag_info, uint32_t instr, uint32_t out, uint if (in) { - fields[0].in_value=(uint8_t *)in; + fields[0].in_value = (uint8_t *)in; jtag_add_dr_scan(3, fields, jtag_get_end_state()); jtag_add_callback(arm_le_to_h_u32, (jtag_callback_data_t)in); @@ -294,7 +294,7 @@ extern void arm_endianness(uint8_t *tmp, void *in, int size, int be, int flip); static int arm9endianness(jtag_callback_data_t arg, jtag_callback_data_t size, jtag_callback_data_t be, jtag_callback_data_t captured) { - uint8_t *in=(uint8_t *)arg; + uint8_t *in = (uint8_t *)arg; arm_endianness((uint8_t *)captured, in, (int)size, (int)be, 0); return ERROR_OK; } @@ -817,7 +817,7 @@ int arm9tdmi_examine(struct target_s *target) reg_cache_t **cache_p = register_get_last_cache_p(&target->reg_cache); reg_cache_t *t; /* one extra register (vector catch) */ - t=embeddedice_build_reg_cache(target, arm7_9); + t = embeddedice_build_reg_cache(target, arm7_9); if (t == NULL) return ERROR_FAIL; (*cache_p) = t; @@ -831,13 +831,13 @@ int arm9tdmi_examine(struct target_s *target) } target_set_examined(target); } - if ((retval=embeddedice_setup(target)) != ERROR_OK) + if ((retval = embeddedice_setup(target)) != ERROR_OK) return retval; - if ((retval=arm7_9_setup(target)) != ERROR_OK) + if ((retval = arm7_9_setup(target)) != ERROR_OK) return retval; if (arm7_9->etm_ctx) { - if ((retval=etm_setup(target)) != ERROR_OK) + if ((retval = etm_setup(target)) != ERROR_OK) return retval; } return ERROR_OK; diff --git a/src/target/arm_adi_v5.c b/src/target/arm_adi_v5.c index aac0a173..57f6603b 100644 --- a/src/target/arm_adi_v5.c +++ b/src/target/arm_adi_v5.c @@ -152,7 +152,7 @@ int scan_inout_check(swjdp_common_t *swjdp, uint8_t instr, uint8_t reg_addr, uin adi_jtag_dp_scan(swjdp, DAP_IR_DPACC, DP_RDBUFF, DPAP_READ, 0, invalue, &swjdp->ack); } - /* In TRANS_MODE_ATOMIC all DAP_IR_APACC transactions wait for ack=OK/FAULT and the check CTRL_STAT */ + /* In TRANS_MODE_ATOMIC all DAP_IR_APACC transactions wait for ack = OK/FAULT and the check CTRL_STAT */ if ((instr == DAP_IR_APACC) && (swjdp->trans_mode == TRANS_MODE_ATOMIC)) { return swjdp_transaction_endcheck(swjdp); @@ -170,7 +170,7 @@ int scan_inout_check_u32(swjdp_common_t *swjdp, uint8_t instr, uint8_t reg_addr, adi_jtag_dp_scan_u32(swjdp, DAP_IR_DPACC, DP_RDBUFF, DPAP_READ, 0, invalue, &swjdp->ack); } - /* In TRANS_MODE_ATOMIC all DAP_IR_APACC transactions wait for ack=OK/FAULT and then check CTRL_STAT */ + /* In TRANS_MODE_ATOMIC all DAP_IR_APACC transactions wait for ack = OK/FAULT and then check CTRL_STAT */ if ((instr == DAP_IR_APACC) && (swjdp->trans_mode == TRANS_MODE_ATOMIC)) { return swjdp_transaction_endcheck(swjdp); @@ -195,7 +195,7 @@ int swjdp_transaction_endcheck(swjdp_common_t *swjdp) https://lists.berlios.de/pipermail/openocd-development/2008-September/003107.html */ - if ((retval=jtag_execute_queue()) != ERROR_OK) + if ((retval = jtag_execute_queue()) != ERROR_OK) { LOG_ERROR("BUG: Why does this fail the first time????"); } @@ -203,14 +203,14 @@ int swjdp_transaction_endcheck(swjdp_common_t *swjdp) #endif scan_inout_check_u32(swjdp, DAP_IR_DPACC, DP_CTRL_STAT, DPAP_READ, 0, &ctrlstat); - if ((retval=jtag_execute_queue()) != ERROR_OK) + if ((retval = jtag_execute_queue()) != ERROR_OK) return retval; swjdp->ack = swjdp->ack & 0x7; if (swjdp->ack != 2) { - long long then=timeval_ms(); + long long then = timeval_ms(); while (swjdp->ack != 2) { if (swjdp->ack == 1) @@ -228,7 +228,7 @@ int swjdp_transaction_endcheck(swjdp_common_t *swjdp) } scan_inout_check_u32(swjdp, DAP_IR_DPACC, DP_CTRL_STAT, DPAP_READ, 0, &ctrlstat); - if ((retval=jtag_execute_queue()) != ERROR_OK) + if ((retval = jtag_execute_queue()) != ERROR_OK) return retval; swjdp->ack = swjdp->ack & 0x7; } @@ -261,19 +261,19 @@ int swjdp_transaction_endcheck(swjdp_common_t *swjdp) /* Clear Sticky Error Bits */ scan_inout_check_u32(swjdp, DAP_IR_DPACC, DP_CTRL_STAT, DPAP_WRITE, swjdp->dp_ctrl_stat | SSTICKYORUN | SSTICKYERR, NULL); scan_inout_check_u32(swjdp, DAP_IR_DPACC, DP_CTRL_STAT, DPAP_READ, 0, &ctrlstat); - if ((retval=jtag_execute_queue()) != ERROR_OK) + if ((retval = jtag_execute_queue()) != ERROR_OK) return retval; LOG_DEBUG("swjdp: status 0x%" PRIx32 "", ctrlstat); dap_ap_read_reg_u32(swjdp, AP_REG_CSW, &mem_ap_csw); dap_ap_read_reg_u32(swjdp, AP_REG_TAR, &mem_ap_tar); - if ((retval=jtag_execute_queue()) != ERROR_OK) + if ((retval = jtag_execute_queue()) != ERROR_OK) return retval; LOG_ERROR("Read MEM_AP_CSW 0x%" PRIx32 ", MEM_AP_TAR 0x%" PRIx32 "", mem_ap_csw, mem_ap_tar); } - if ((retval=jtag_execute_queue()) != ERROR_OK) + if ((retval = jtag_execute_queue()) != ERROR_OK) return retval; return ERROR_JTAG_DEVICE_ERROR; } @@ -971,7 +971,7 @@ int ahbap_debugport_init(swjdp_common_t *swjdp) dap_dp_write_reg(swjdp, swjdp->dp_ctrl_stat, DP_CTRL_STAT); dap_dp_read_reg(swjdp, &ctrlstat, DP_CTRL_STAT); - if ((retval=jtag_execute_queue()) != ERROR_OK) + if ((retval = jtag_execute_queue()) != ERROR_OK) return retval; /* Check that we have debug power domains activated */ @@ -979,7 +979,7 @@ int ahbap_debugport_init(swjdp_common_t *swjdp) { LOG_DEBUG("swjdp: wait CDBGPWRUPACK"); dap_dp_read_reg(swjdp, &ctrlstat, DP_CTRL_STAT); - if ((retval=jtag_execute_queue()) != ERROR_OK) + if ((retval = jtag_execute_queue()) != ERROR_OK) return retval; alive_sleep(10); } @@ -988,7 +988,7 @@ int ahbap_debugport_init(swjdp_common_t *swjdp) { LOG_DEBUG("swjdp: wait CSYSPWRUPACK"); dap_dp_read_reg(swjdp, &ctrlstat, DP_CTRL_STAT); - if ((retval=jtag_execute_queue()) != ERROR_OK) + if ((retval = jtag_execute_queue()) != ERROR_OK) return retval; alive_sleep(10); } diff --git a/src/target/arm_jtag.h b/src/target/arm_jtag.h index e562ac17..bcde47e2 100644 --- a/src/target/arm_jtag.h +++ b/src/target/arm_jtag.h @@ -60,14 +60,14 @@ int arm_jtag_buf_to_8(uint8_t *in_buf, void *priv, struct scan_field_s *field); /* use this as a static so we can inline it in -O3 and refer to it via a pointer */ static __inline__ void arm7flip32(jtag_callback_data_t arg) { - uint8_t *in=(uint8_t *)arg; - *((uint32_t *)in)=flip_u32(le_to_h_u32(in), 32); + uint8_t *in = (uint8_t *)arg; + *((uint32_t *)in) = flip_u32(le_to_h_u32(in), 32); } static __inline__ void arm_le_to_h_u32(jtag_callback_data_t arg) { - uint8_t *in=(uint8_t *)arg; - *((uint32_t *)in)=le_to_h_u32(in); + uint8_t *in = (uint8_t *)arg; + *((uint32_t *)in) = le_to_h_u32(in); } diff --git a/src/target/armv4_5.c b/src/target/armv4_5.c index b88cdc8c..f5e906a8 100644 --- a/src/target/armv4_5.c +++ b/src/target/armv4_5.c @@ -501,9 +501,9 @@ static int armv4_5_run_algorithm_completion(struct target_s *target, uint32_t ex } if (target->state != TARGET_HALTED) { - if ((retval=target_halt(target)) != ERROR_OK) + if ((retval = target_halt(target)) != ERROR_OK) return retval; - if ((retval=target_wait_state(target, TARGET_HALTED, 500)) != ERROR_OK) + if ((retval = target_wait_state(target, TARGET_HALTED, 500)) != ERROR_OK) { return retval; } @@ -614,7 +614,7 @@ int armv4_5_run_algorithm_inner(struct target_s *target, int num_mem_params, mem return retval; } int retvaltemp; - retval=run_it(target, exit_point, timeout_ms, arch_info); + retval = run_it(target, exit_point, timeout_ms, arch_info); breakpoint_remove(target, exit_point); diff --git a/src/target/armv4_5.h b/src/target/armv4_5.h index d37f7097..8e9710a8 100644 --- a/src/target/armv4_5.h +++ b/src/target/armv4_5.h @@ -154,7 +154,7 @@ extern int armv4_5_invalidate_core_regs(target_t *target); * Rn: base register * List: for each bit in list: store register * S: in priviledged mode: store user-mode registers - * W=1: update the base register. W=0: leave the base register untouched + * W = 1: update the base register. W = 0: leave the base register untouched */ #define ARMV4_5_STMIA(Rn, List, S, W) (0xe8800000 | ((S) << 22) | ((W) << 21) | ((Rn) << 16) | (List)) @@ -162,7 +162,7 @@ extern int armv4_5_invalidate_core_regs(target_t *target); * Rn: base register * List: for each bit in list: store register * S: in priviledged mode: store user-mode registers - * W=1: update the base register. W=0: leave the base register untouched + * W = 1: update the base register. W = 0: leave the base register untouched */ #define ARMV4_5_LDMIA(Rn, List, S, W) (0xe8900000 | ((S) << 22) | ((W) << 21) | ((Rn) << 16) | (List)) @@ -170,7 +170,7 @@ extern int armv4_5_invalidate_core_regs(target_t *target); #define ARMV4_5_NOP (0xe1a08008) /* Move PSR to general purpose register - * R=1: SPSR R=0: CPSR + * R = 1: SPSR R = 0: CPSR * Rn: target register */ #define ARMV4_5_MRS(Rn, R) (0xe10f0000 | ((R) << 22) | ((Rn) << 12)) @@ -188,7 +188,7 @@ extern int armv4_5_invalidate_core_regs(target_t *target); #define ARMV4_5_LDR(Rd, Rn) (0xe5900000 | ((Rd) << 12) | ((Rn) << 16)) /* Move general purpose register to PSR - * R=1: SPSR R=0: CPSR + * R = 1: SPSR R = 0: CPSR * Field: Field mask * 1: control field 2: extension field 4: status field 8: flags field * Rm: source register diff --git a/src/target/armv7m.c b/src/target/armv7m.c index 3e59040c..3f162f58 100644 --- a/src/target/armv7m.c +++ b/src/target/armv7m.c @@ -304,9 +304,9 @@ static int armv7m_run_and_wait(struct target_s *target, uint32_t entry_point, in /* If the target fails to halt due to the breakpoint, force a halt */ if (retval != ERROR_OK || target->state != TARGET_HALTED) { - if ((retval=target_halt(target)) != ERROR_OK) + if ((retval = target_halt(target)) != ERROR_OK) return retval; - if ((retval=target_wait_state(target, TARGET_HALTED, 500)) != ERROR_OK) + if ((retval = target_wait_state(target, TARGET_HALTED, 500)) != ERROR_OK) { return retval; } @@ -356,7 +356,7 @@ int armv7m_run_algorithm(struct target_s *target, int num_mem_params, mem_param_ for (i = 0; i < num_mem_params; i++) { - if ((retval=target_write_buffer(target, mem_params[i].address, mem_params[i].size, mem_params[i].value)) != ERROR_OK) + if ((retval = target_write_buffer(target, mem_params[i].address, mem_params[i].size, mem_params[i].value)) != ERROR_OK) return retval; } diff --git a/src/target/cortex_m3.c b/src/target/cortex_m3.c index 6079b9eb..c1ebae3f 100644 --- a/src/target/cortex_m3.c +++ b/src/target/cortex_m3.c @@ -694,7 +694,7 @@ int cortex_m3_resume(struct target_s *target, int current, uint32_t address, int return ERROR_OK; } -/* int irqstepcount=0; */ +/* int irqstepcount = 0; */ int cortex_m3_step(struct target_s *target, int current, uint32_t address, int handle_breakpoints) { /* get pointers to arch-specific information */ @@ -886,7 +886,7 @@ void cortex_m3_enable_breakpoints(struct target_s *target) int cortex_m3_set_breakpoint(struct target_s *target, breakpoint_t *breakpoint) { int retval; - int fp_num=0; + int fp_num = 0; uint32_t hilo; /* get pointers to arch-specific information */ @@ -1075,7 +1075,7 @@ int cortex_m3_remove_breakpoint(struct target_s *target, breakpoint_t *breakpoin int cortex_m3_set_watchpoint(struct target_s *target, watchpoint_t *watchpoint) { - int dwt_num=0; + int dwt_num = 0; uint32_t mask, temp; /* get pointers to arch-specific information */ @@ -1285,7 +1285,7 @@ int cortex_m3_store_core_reg_u32(struct target_s *target, enum armv7m_regtype ty * in "thumb" mode, or an INVSTATE exception will occur. This is a * hack to deal with the fact that gdb will sometimes "forge" * return addresses, and doesn't set the LSB correctly (i.e., when - * printing expressions containing function calls, it sets LR=0.) */ + * printing expressions containing function calls, it sets LR = 0.) */ if (num == 14) value |= 0x01; diff --git a/src/target/embeddedice.c b/src/target/embeddedice.c index 92e322bd..5f99120b 100644 --- a/src/target/embeddedice.c +++ b/src/target/embeddedice.c @@ -125,7 +125,7 @@ reg_cache_t* embeddedice_build_reg_cache(target_t *target, arm7_9_common_t *arm7 /* identify EmbeddedICE version by reading DCC control register */ embeddedice_read_reg(®_list[EICE_COMMS_CTRL]); - if ((retval=jtag_execute_queue()) != ERROR_OK) + if ((retval = jtag_execute_queue()) != ERROR_OK) { for (i = 0; i < num_regs; i++) { @@ -204,7 +204,7 @@ int embeddedice_setup(target_t *target) reg_t *dbg_ctrl = &arm7_9->eice_cache->reg_list[EICE_DBG_CTRL]; embeddedice_read_reg(dbg_ctrl); - if ((retval=jtag_execute_queue()) != ERROR_OK) + if ((retval = jtag_execute_queue()) != ERROR_OK) return retval; buf_set_u32(dbg_ctrl->value, 4, 1, 0); embeddedice_set_reg_w_exec(dbg_ctrl, dbg_ctrl->value); diff --git a/src/target/etb.c b/src/target/etb.c index 41f2f5c5..979d7a70 100644 --- a/src/target/etb.c +++ b/src/target/etb.c @@ -160,8 +160,8 @@ static int etb_get_reg(reg_t *reg) static void etb_getbuf(jtag_callback_data_t arg) { - uint8_t *in=(uint8_t *)arg; - *((uint32_t *)in)=buf_get_u32(in, 0, 32); + uint8_t *in = (uint8_t *)arg; + *((uint32_t *)in) = buf_get_u32(in, 0, 32); } diff --git a/src/target/etm.c b/src/target/etm.c index 342ff918..44ae9304 100644 --- a/src/target/etm.c +++ b/src/target/etm.c @@ -282,10 +282,10 @@ int etm_setup(target_t *target) buf_set_u32(etm_ctrl_reg->value, 0, etm_ctrl_reg->size, etm_ctrl_value); etm_store_reg(etm_ctrl_reg); - if ((retval=jtag_execute_queue()) != ERROR_OK) + if ((retval = jtag_execute_queue()) != ERROR_OK) return retval; - if ((retval=etm_ctx->capture_driver->init(etm_ctx)) != ERROR_OK) + if ((retval = etm_ctx->capture_driver->init(etm_ctx)) != ERROR_OK) { LOG_ERROR("ETM capture driver initialization failed"); return retval; @@ -1266,12 +1266,12 @@ static int handle_etm_config_command(struct command_context_s *cmd_ctx, char *cm return ERROR_FAIL; } - for (i=0; etm_capture_drivers[i]; i++) + for (i = 0; etm_capture_drivers[i]; i++) { if (strcmp(args[4], etm_capture_drivers[i]->name) == 0) { int retval; - if ((retval=etm_capture_drivers[i]->register_commands(cmd_ctx)) != ERROR_OK) + if ((retval = etm_capture_drivers[i]->register_commands(cmd_ctx)) != ERROR_OK) { free(etm_ctx); return retval; diff --git a/src/target/image.c b/src/target/image.c index d8c0cfc4..5cc7b0d8 100644 --- a/src/target/image.c +++ b/src/target/image.c @@ -59,7 +59,7 @@ static int autodetect_image_type(image_t *image, char *url) { if (read_bytes != 9) { - retval=ERROR_FILEIO_OPERATION_FAILED; + retval = ERROR_FILEIO_OPERATION_FAILED; } } fileio_close(&fileio); @@ -414,12 +414,12 @@ static int image_elf_read_headers(image_t *image) /* count useful segments (loadable), ignore BSS section */ image->num_sections = 0; - for (i=0;isegment_count;i++) + for (i = 0;isegment_count;i++) if ((field32(elf, elf->segments[i].p_type) == PT_LOAD) && (field32(elf, elf->segments[i].p_filesz) != 0)) image->num_sections++; /* alloc and fill sections array with loadable segments */ image->sections = malloc(image->num_sections * sizeof(image_section_t)); - for (i=0,j=0;isegment_count;i++) + for (i = 0,j = 0;isegment_count;i++) { if ((field32(elf, elf->segments[i].p_type) == PT_LOAD) && (field32(elf, elf->segments[i].p_filesz) != 0)) { @@ -446,7 +446,7 @@ static int image_elf_read_section(image_t *image, int section, uint32_t offset, *size_read = 0; - LOG_DEBUG("load segment %d at 0x%" PRIx32 " (sz=0x%" PRIx32 ")",section,offset,size); + LOG_DEBUG("load segment %d at 0x%" PRIx32 " (sz = 0x%" PRIx32 ")",section,offset,size); /* read initialized data in current segment if any */ if (offsetp_filesz)) @@ -762,15 +762,15 @@ int image_open(image_t *image, char *url, char *type_string) { /* relocate */ int section; - for (section=0; section < image->num_sections; section++) + for (section = 0; section < image->num_sections; section++) { image->sections[section].base_address += image->base_address; } /* we're done relocating. The two statements below are mainly * for documenation purposes: stop anyone from empirically * thinking they should use these values henceforth. */ - image->base_address=0; - image->base_address_set=0; + image->base_address = 0; + image->base_address_set = 0; } return retval; @@ -1017,10 +1017,10 @@ int image_calculate_checksum(uint8_t* buffer, uint32_t nbytes, uint32_t* checksu while (nbytes>0) { - int run=nbytes; + int run = nbytes; if (run>32768) { - run=32768; + run = 32768; } nbytes -= run; while (run--) diff --git a/src/target/mips32_dmaacc.c b/src/target/mips32_dmaacc.c index cd73d6e2..ab082cf2 100644 --- a/src/target/mips32_dmaacc.c +++ b/src/target/mips32_dmaacc.c @@ -369,7 +369,7 @@ int mips32_dmaacc_read_mem32(mips_ejtag_t *ejtag_info, uint32_t addr, int count, int i; int retval; - for (i=0; istate = TARGET_RUNNING; } -// LOG_DEBUG("ctrl=0x%08X", ejtag_ctrl); +// LOG_DEBUG("ctrl = 0x%08X", ejtag_ctrl); return ERROR_OK; } diff --git a/src/target/target.c b/src/target/target.c index 81d753e0..ac2528f7 100644 --- a/src/target/target.c +++ b/src/target/target.c @@ -1091,7 +1091,7 @@ int target_arch_state(struct target_s *target) if (target->state != TARGET_HALTED) return ERROR_OK; - retval=target->type->arch_state(target); + retval = target->type->arch_state(target); return retval; } @@ -1466,8 +1466,8 @@ int target_register_user_commands(struct command_context_s *cmd_ctx) /* script procedures */ register_command(cmd_ctx, NULL, "profile", handle_profile_command, COMMAND_EXEC, "profiling samples the CPU PC"); - register_jim(cmd_ctx, "ocd_mem2array", jim_mem2array, "read memory and return as a TCL array for script processing
"); - register_jim(cmd_ctx, "ocd_array2mem", jim_array2mem, "convert a TCL array to memory locations and write the values
"); + register_jim(cmd_ctx, "ocd_mem2array", jim_mem2array, "read memory and return as a TCL array for script processing
"); + register_jim(cmd_ctx, "ocd_array2mem", jim_array2mem, "convert a TCL array to memory locations and write the values
"); register_command(cmd_ctx, NULL, "fast_load_image", handle_fast_load_image_command, COMMAND_ANY, "same args as load_image, image stored in memory - mainly for profiling purposes"); @@ -1584,7 +1584,7 @@ static int sense_handler(void) static int prevPowerdropout = 0; int retval; - if ((retval=jtag_power_dropout(&powerDropout)) != ERROR_OK) + if ((retval = jtag_power_dropout(&powerDropout)) != ERROR_OK) return retval; int powerRestored; @@ -1603,7 +1603,7 @@ static int sense_handler(void) lastPower = current; } - if ((retval=jtag_srst_asserted(&srstAsserted)) != ERROR_OK) + if ((retval = jtag_srst_asserted(&srstAsserted)) != ERROR_OK) return retval; int srstDeasserted; @@ -1681,10 +1681,10 @@ int handle_target(void *priv) /* clear action flags */ - runSrstAsserted=0; - runSrstDeasserted=0; - runPowerRestore=0; - runPowerDropout=0; + runSrstAsserted = 0; + runSrstDeasserted = 0; + runPowerRestore = 0; + runPowerDropout = 0; recursive = 0; } @@ -1904,12 +1904,12 @@ static int handle_wait_halt_command(struct command_context_s *cmd_ctx, char *cmd int target_wait_state(target_t *target, enum target_state state, int ms) { int retval; - long long then=0, cur; - int once=1; + long long then = 0, cur; + int once = 1; for (;;) { - if ((retval=target_poll(target)) != ERROR_OK) + if ((retval = target_poll(target)) != ERROR_OK) return retval; if (target->state == state) { @@ -1918,7 +1918,7 @@ int target_wait_state(target_t *target, enum target_state state, int ms) cur = timeval_ms(); if (once) { - once=0; + once = 0; then = timeval_ms(); LOG_DEBUG("waiting for target %s...", Jim_Nvp_value2name_simple(nvp_target_state,state)->name); @@ -2070,7 +2070,7 @@ static void handle_md_output(struct command_context_s *cmd_ctx, (unsigned)(address + (i*size))); } - uint32_t value=0; + uint32_t value = 0; const uint8_t *value_ptr = buffer + i * size; switch (size) { case 4: value = target_buffer_get_u32(target, value_ptr); break; @@ -2274,8 +2274,8 @@ static int handle_load_image_command(struct command_context_s *cmd_ctx, char *cm break; } - uint32_t offset=0; - uint32_t length=buf_cnt; + uint32_t offset = 0; + uint32_t length = buf_cnt; /* DANGER!!! beware of unsigned comparision here!!! */ @@ -2447,13 +2447,13 @@ static int handle_verify_image_command_internal(struct command_context_s *cmd_ct image.start_address_set = 0; - if ((retval=image_open(&image, args[0], (argc == 3) ? args[2] : NULL)) != ERROR_OK) + if ((retval = image_open(&image, args[0], (argc == 3) ? args[2] : NULL)) != ERROR_OK) { return retval; } image_size = 0x0; - retval=ERROR_OK; + retval = ERROR_OK; for (i = 0; i < image.num_sections; i++) { buffer = malloc(image.sections[i].size); @@ -2514,7 +2514,7 @@ static int handle_verify_image_command_internal(struct command_context_s *cmd_ct buffer[t]); free(data); free(buffer); - retval=ERROR_FAIL; + retval = ERROR_FAIL; goto done; } if ((t%16384) == 0) @@ -2790,9 +2790,9 @@ static void writeData(FILE *f, const void *data, size_t len) static void writeLong(FILE *f, int l) { int i; - for (i=0; i<4; i++) + for (i = 0; i<4; i++) { - char c=(l >> (i*8))&0xff; + char c = (l >> (i*8))&0xff; writeData(f, &c, 1); } @@ -2807,7 +2807,7 @@ static void writeString(FILE *f, char *s) static void writeGmon(uint32_t *samples, uint32_t sampleNum, char *filename) { uint32_t i; - FILE *f=fopen(filename, "w"); + FILE *f = fopen(filename, "w"); if (f == NULL) return; writeString(f, "gmon"); @@ -2820,42 +2820,42 @@ static void writeGmon(uint32_t *samples, uint32_t sampleNum, char *filename) writeData(f, &zero, 1); /* figure out bucket size */ - uint32_t min=samples[0]; - uint32_t max=samples[0]; - for (i=0; isamples[i]) { - min=samples[i]; + min = samples[i]; } if (max maxBuckets) { - length=maxBuckets; + length = maxBuckets; } - int *buckets=malloc(sizeof(int)*length); + int *buckets = malloc(sizeof(int)*length); if (buckets == NULL) { fclose(f); return; } memset(buckets, 0, sizeof(int)*length); - for (i=0; i65535) { - val=65535; + val = 65535; } data[i*2]=val&0xff; data[i*2+1]=(val >> 8)&0xff; @@ -2916,12 +2916,12 @@ static int handle_profile_command(struct command_context_s *cmd_ctx, char *cmd, command_print(cmd_ctx, "Starting profiling. Halting and resuming the target as often as we can..."); - static const int maxSample=10000; - uint32_t *samples=malloc(sizeof(uint32_t)*maxSample); + static const int maxSample = 10000; + uint32_t *samples = malloc(sizeof(uint32_t)*maxSample); if (samples == NULL) return ERROR_OK; - int numSamples=0; + int numSamples = 0; /* hopefully it is safe to cache! We want to stop/restart as quickly as possible. */ reg_t *reg = register_get_by_name(target->reg_cache, "pc", 1); @@ -2946,7 +2946,7 @@ static int handle_profile_command(struct command_context_s *cmd_ctx, char *cmd, } else { command_print(cmd_ctx, "Target not halted or running"); - retval=ERROR_OK; + retval = ERROR_OK; break; } if (retval != ERROR_OK) @@ -4206,7 +4206,7 @@ static int target_create( Jim_GetOptInfo *goi ) if (target->tap == NULL) { Jim_SetResultString( interp, "-chain-position required when creating target", -1); - e=JIM_ERR; + e = JIM_ERR; } if ( e != JIM_OK ){ @@ -4389,13 +4389,13 @@ static void free_fastload(void) if (fastload != NULL) { int i; - for (i=0; iarch_info; xscale_common_t *xscale = armv4_5->arch_info; @@ -351,7 +351,7 @@ int xscale_receive(target_t *target, uint32_t *buffer, int num_words) jtag_add_runtest(1, jtag_get_end_state()); /* ensures that we're in the TAP_IDLE state as the above could be a no-op */ /* repeat until all words have been collected */ - int attempts=0; + int attempts = 0; while (words_done < num_words) { /* schedule reads */ @@ -397,7 +397,7 @@ int xscale_receive(target_t *target, uint32_t *buffer, int num_words) if (attempts++==1000) { LOG_ERROR("Failed to receiving data from debug handler after 1000 attempts"); - retval=ERROR_TARGET_TIMEOUT; + retval = ERROR_TARGET_TIMEOUT; break; } } @@ -886,7 +886,7 @@ int xscale_update_vectors(target_t *target) } else { - retval=target_read_u32(target, 0xffff0000 + 4*i, &xscale->high_vectors[i]); + retval = target_read_u32(target, 0xffff0000 + 4*i, &xscale->high_vectors[i]); if (retval == ERROR_TARGET_TIMEOUT) return retval; if (retval != ERROR_OK) @@ -905,7 +905,7 @@ int xscale_update_vectors(target_t *target) } else { - retval=target_read_u32(target, 0x0 + 4*i, &xscale->low_vectors[i]); + retval = target_read_u32(target, 0x0 + 4*i, &xscale->low_vectors[i]); if (retval == ERROR_TARGET_TIMEOUT) return retval; if (retval != ERROR_OK) @@ -973,7 +973,7 @@ int xscale_arch_state(struct target_s *target) int xscale_poll(target_t *target) { - int retval=ERROR_OK; + int retval = ERROR_OK; armv4_5_common_t *armv4_5 = target->arch_info; xscale_common_t *xscale = armv4_5->arch_info; @@ -1028,11 +1028,11 @@ int xscale_debug_entry(target_t *target) /* clear external dbg break (will be written on next DCSR read) */ xscale->external_debug_break = 0; - if ((retval=xscale_read_dcsr(target)) != ERROR_OK) + if ((retval = xscale_read_dcsr(target)) != ERROR_OK) return retval; /* get r0, pc, r1 to r7 and cpsr */ - if ((retval=xscale_receive(target, buffer, 10)) != ERROR_OK) + if ((retval = xscale_receive(target, buffer, 10)) != ERROR_OK) return retval; /* move r0 from buffer to register cache */ @@ -1253,7 +1253,7 @@ int xscale_enable_single_step(struct target_s *target, uint32_t next_pc) } } - if ((retval=xscale_set_reg_u32(ibcr0, next_pc | 0x1)) != ERROR_OK) + if ((retval = xscale_set_reg_u32(ibcr0, next_pc | 0x1)) != ERROR_OK) return retval; return ERROR_OK; @@ -1266,7 +1266,7 @@ int xscale_disable_single_step(struct target_s *target) reg_t *ibcr0 = &xscale->reg_cache->reg_list[XSCALE_IBCR0]; int retval; - if ((retval=xscale_set_reg_u32(ibcr0, 0x0)) != ERROR_OK) + if ((retval = xscale_set_reg_u32(ibcr0, 0x0)) != ERROR_OK) return retval; return ERROR_OK; @@ -1297,7 +1297,7 @@ int xscale_resume(struct target_s *target, int current, uint32_t address, int ha } /* update vector tables */ - if ((retval=xscale_update_vectors(target)) != ERROR_OK) + if ((retval = xscale_update_vectors(target)) != ERROR_OK) return retval; /* current = 1: continue on current pc, otherwise continue at
*/ @@ -1451,56 +1451,56 @@ static int xscale_step_inner(struct target_s *target, int current, uint32_t addr } LOG_DEBUG("enable single-step"); - if ((retval=xscale_enable_single_step(target, next_pc)) != ERROR_OK) + if ((retval = xscale_enable_single_step(target, next_pc)) != ERROR_OK) return retval; /* restore banked registers */ - if ((retval=xscale_restore_context(target)) != ERROR_OK) + if ((retval = xscale_restore_context(target)) != ERROR_OK) return retval; /* send resume request (command 0x30 or 0x31) * clean the trace buffer if it is to be enabled (0x62) */ if (xscale->trace.buffer_enabled) { - if ((retval=xscale_send_u32(target, 0x62)) != ERROR_OK) + if ((retval = xscale_send_u32(target, 0x62)) != ERROR_OK) return retval; - if ((retval=xscale_send_u32(target, 0x31)) != ERROR_OK) + if ((retval = xscale_send_u32(target, 0x31)) != ERROR_OK) return retval; } else - if ((retval=xscale_send_u32(target, 0x30)) != ERROR_OK) + if ((retval = xscale_send_u32(target, 0x30)) != ERROR_OK) return retval; /* send CPSR */ - if ((retval=xscale_send_u32(target, buf_get_u32(armv4_5->core_cache->reg_list[ARMV4_5_CPSR].value, 0, 32))) != ERROR_OK) + if ((retval = xscale_send_u32(target, buf_get_u32(armv4_5->core_cache->reg_list[ARMV4_5_CPSR].value, 0, 32))) != ERROR_OK) return retval; LOG_DEBUG("writing cpsr with value 0x%8.8" PRIx32 "", buf_get_u32(armv4_5->core_cache->reg_list[ARMV4_5_CPSR].value, 0, 32)); for (i = 7; i >= 0; i--) { /* send register */ - if ((retval=xscale_send_u32(target, buf_get_u32(armv4_5->core_cache->reg_list[i].value, 0, 32))) != ERROR_OK) + if ((retval = xscale_send_u32(target, buf_get_u32(armv4_5->core_cache->reg_list[i].value, 0, 32))) != ERROR_OK) return retval; LOG_DEBUG("writing r%i with value 0x%8.8" PRIx32 "", i, buf_get_u32(armv4_5->core_cache->reg_list[i].value, 0, 32)); } /* send PC */ - if ((retval=xscale_send_u32(target, buf_get_u32(armv4_5->core_cache->reg_list[15].value, 0, 32))) != ERROR_OK) + if ((retval = xscale_send_u32(target, buf_get_u32(armv4_5->core_cache->reg_list[15].value, 0, 32))) != ERROR_OK) return retval; LOG_DEBUG("writing PC with value 0x%8.8" PRIx32, buf_get_u32(armv4_5->core_cache->reg_list[15].value, 0, 32)); target_call_event_callbacks(target, TARGET_EVENT_RESUMED); /* registers are now invalid */ - if ((retval=armv4_5_invalidate_core_regs(target)) != ERROR_OK) + if ((retval = armv4_5_invalidate_core_regs(target)) != ERROR_OK) return retval; /* wait for and process debug entry */ - if ((retval=xscale_debug_entry(target)) != ERROR_OK) + if ((retval = xscale_debug_entry(target)) != ERROR_OK) return retval; LOG_DEBUG("disable single-step"); - if ((retval=xscale_disable_single_step(target)) != ERROR_OK) + if ((retval = xscale_disable_single_step(target)) != ERROR_OK) return retval; target_call_event_callbacks(target, TARGET_EVENT_HALTED); @@ -1531,7 +1531,7 @@ int xscale_step(struct target_s *target, int current, uint32_t address, int hand /* if we're at the reset vector, we have to simulate the step */ if (current_pc == 0x0) { - if ((retval=arm_simulate_step(target, NULL)) != ERROR_OK) + if ((retval = arm_simulate_step(target, NULL)) != ERROR_OK) return retval; current_pc = buf_get_u32(armv4_5->core_cache->reg_list[15].value, 0, 32); @@ -1545,7 +1545,7 @@ int xscale_step(struct target_s *target, int current, uint32_t address, int hand if (handle_breakpoints) if ((breakpoint = breakpoint_find(target, buf_get_u32(armv4_5->core_cache->reg_list[15].value, 0, 32)))) { - if ((retval=xscale_unset_breakpoint(target, breakpoint)) != ERROR_OK) + if ((retval = xscale_unset_breakpoint(target, breakpoint)) != ERROR_OK) return retval; } @@ -1930,20 +1930,20 @@ int xscale_read_memory(struct target_s *target, uint32_t address, uint32_t size, return ERROR_TARGET_UNALIGNED_ACCESS; /* send memory read request (command 0x1n, n: access size) */ - if ((retval=xscale_send_u32(target, 0x10 | size)) != ERROR_OK) + if ((retval = xscale_send_u32(target, 0x10 | size)) != ERROR_OK) return retval; /* send base address for read request */ - if ((retval=xscale_send_u32(target, address)) != ERROR_OK) + if ((retval = xscale_send_u32(target, address)) != ERROR_OK) return retval; /* send number of requested data words */ - if ((retval=xscale_send_u32(target, count)) != ERROR_OK) + if ((retval = xscale_send_u32(target, count)) != ERROR_OK) return retval; /* receive data from target (count times 32-bit words in host endianness) */ buf32 = malloc(4 * count); - if ((retval=xscale_receive(target, buf32, count)) != ERROR_OK) + if ((retval = xscale_receive(target, buf32, count)) != ERROR_OK) return retval; /* extract data from host-endian buffer into byte stream */ @@ -1971,12 +1971,12 @@ int xscale_read_memory(struct target_s *target, uint32_t address, uint32_t size, free(buf32); /* examine DCSR, to see if Sticky Abort (SA) got set */ - if ((retval=xscale_read_dcsr(target)) != ERROR_OK) + if ((retval = xscale_read_dcsr(target)) != ERROR_OK) return retval; if (buf_get_u32(xscale->reg_cache->reg_list[XSCALE_DCSR].value, 5, 1) == 1) { /* clear SA bit */ - if ((retval=xscale_send_u32(target, 0x60)) != ERROR_OK) + if ((retval = xscale_send_u32(target, 0x60)) != ERROR_OK) return retval; return ERROR_TARGET_DATA_ABORT; @@ -2007,15 +2007,15 @@ int xscale_write_memory(struct target_s *target, uint32_t address, uint32_t size return ERROR_TARGET_UNALIGNED_ACCESS; /* send memory write request (command 0x2n, n: access size) */ - if ((retval=xscale_send_u32(target, 0x20 | size)) != ERROR_OK) + if ((retval = xscale_send_u32(target, 0x20 | size)) != ERROR_OK) return retval; /* send base address for read request */ - if ((retval=xscale_send_u32(target, address)) != ERROR_OK) + if ((retval = xscale_send_u32(target, address)) != ERROR_OK) return retval; /* send number of requested data words to be written*/ - if ((retval=xscale_send_u32(target, count)) != ERROR_OK) + if ((retval = xscale_send_u32(target, count)) != ERROR_OK) return retval; /* extract data from host-endian buffer into byte stream */ @@ -2045,16 +2045,16 @@ int xscale_write_memory(struct target_s *target, uint32_t address, uint32_t size } } #endif - if ((retval=xscale_send(target, buffer, count, size)) != ERROR_OK) + if ((retval = xscale_send(target, buffer, count, size)) != ERROR_OK) return retval; /* examine DCSR, to see if Sticky Abort (SA) got set */ - if ((retval=xscale_read_dcsr(target)) != ERROR_OK) + if ((retval = xscale_read_dcsr(target)) != ERROR_OK) return retval; if (buf_get_u32(xscale->reg_cache->reg_list[XSCALE_DCSR].value, 5, 1) == 1) { /* clear SA bit */ - if ((retval=xscale_send_u32(target, 0x60)) != ERROR_OK) + if ((retval = xscale_send_u32(target, 0x60)) != ERROR_OK) return retval; return ERROR_TARGET_DATA_ABORT; @@ -2330,7 +2330,7 @@ int xscale_set_watchpoint(struct target_s *target, watchpoint_t *watchpoint) { armv4_5_common_t *armv4_5 = target->arch_info; xscale_common_t *xscale = armv4_5->arch_info; - uint8_t enable=0; + uint8_t enable = 0; reg_t *dbcon = &xscale->reg_cache->reg_list[XSCALE_DBCON]; uint32_t dbcon_value = buf_get_u32(dbcon->value, 0, 32); -- cgit v1.2.3