From 8e60d4955f4a89da39bf9b91217c651b44052538 Mon Sep 17 00:00:00 2001 From: Aaron Carroll <aaronc@cse.unsw.edu.au> Date: Mon, 24 Jan 2011 18:06:45 +1100 Subject: arm_dpm: add some SCR/RCR macros Signed-off-by: Aaron Carroll <aaronc@cse.unsw.edu.au> --- src/target/arm_dpm.h | 10 ++++++++-- 1 file changed, 8 insertions(+), 2 deletions(-) (limited to 'src/target') diff --git a/src/target/arm_dpm.h b/src/target/arm_dpm.h index e180807f..b20184c8 100644 --- a/src/target/arm_dpm.h +++ b/src/target/arm_dpm.h @@ -143,14 +143,20 @@ void arm_dpm_report_wfar(struct arm_dpm *, uint32_t wfar); #define DSCR_CORE_HALTED (1 << 0) #define DSCR_CORE_RESTARTED (1 << 1) #define DSCR_INT_DIS (1 << 11) -#define DSCR_ITR_EN (1 << 13) +#define DSCR_ITR_EN (1 << 13) #define DSCR_HALT_DBG_MODE (1 << 14) #define DSCR_MON_DBG_MODE (1 << 15) #define DSCR_INSTR_COMP (1 << 24) #define DSCR_DTR_TX_FULL (1 << 29) #define DSCR_DTR_RX_FULL (1 << 30) -#define DSCR_ENTRY(dscr) (((dscr) >> 2) & 0xf) +#define DSCR_ENTRY(dscr) (((dscr) >> 2) & 0xf) +#define DSCR_RUN_MODE(dscr) ((dscr) & (DSCR_CORE_HALTED | DSCR_CORE_RESTARTED)) + +/* DRCR (debug run control register) bits */ +#define DRCR_HALT (1 << 0) +#define DRCR_RESTART (1 << 1) +#define DRCR_CLEAR_EXCEPTIONS (1 << 2) void arm_dpm_report_dscr(struct arm_dpm *dpm, uint32_t dcsr); -- cgit v1.2.3