From b83d79a42f908d3860f06910fdec8fb4fc670e6c Mon Sep 17 00:00:00 2001 From: dbrownell Date: Wed, 7 Oct 2009 15:31:33 +0000 Subject: Updates for "reset_config": - revert to previous default: don't talk JTAG during SRST - add "srst_nogates" flag, the converse of "srst_gates_jtag" - with no args, display the current configuration And update the User's Guide text with bullet lists to be a bit more clear. git-svn-id: svn://svn.berlios.de/openocd/trunk@2818 b42882b7-edfa-0310-969c-e2dbd0fdcd60 --- src/target/arm7_9_common.c | 15 +++++++++++---- 1 file changed, 11 insertions(+), 4 deletions(-) (limited to 'src/target') diff --git a/src/target/arm7_9_common.c b/src/target/arm7_9_common.c index 40dddda6..2b064f23 100644 --- a/src/target/arm7_9_common.c +++ b/src/target/arm7_9_common.c @@ -1021,12 +1021,19 @@ int arm7_9_assert_reset(target_t *target) return ERROR_FAIL; } - /* at this point trst has been asserted/deasserted once. We want to - * program embedded ice while SRST is asserted, but some CPUs gate - * the JTAG clock while SRST is asserted + /* At this point trst has been asserted/deasserted once. We would + * like to program EmbeddedICE while SRST is asserted, instead of + * depending on SRST to leave that module alone. However, many CPUs + * gate the JTAG clock while SRST is asserted; or JTAG may need + * clock stability guarantees (adaptive clocking might help). + * + * So we assume JTAG access during SRST is off the menu unless it's + * been specifically enabled. */ bool srst_asserted = false; - if (((jtag_reset_config & RESET_SRST_PULLS_TRST) == 0) && ((jtag_reset_config & RESET_SRST_GATES_JTAG) == 0)) + + if (((jtag_reset_config & RESET_SRST_PULLS_TRST) == 0) + && (jtag_reset_config & RESET_SRST_NO_GATING)) { jtag_add_reset(0, 1); srst_asserted = true; -- cgit v1.2.3