From ccc2e3fe760a425f831b9e1f0e143d7d01d73a25 Mon Sep 17 00:00:00 2001
From: oharboe <oharboe@b42882b7-edfa-0310-969c-e2dbd0fdcd60>
Date: Wed, 15 Oct 2008 11:44:36 +0000
Subject: Laurentiu Cocanu - memory read/write and exit() error path fixes
git-svn-id: svn://svn.berlios.de/openocd/trunk@1064 b42882b7-edfa-0310-969c-e2dbd0fdcd60
---
src/target/arm7_9_common.c | 47 ++++++++++++++++++++++++++++++++++++----------
src/target/arm920t.c | 5 +++--
src/target/cortex_m3.c | 22 ++++++++++++++++++----
src/target/embeddedice.c | 13 ++++++++-----
src/target/etb.c | 18 +++++++++++-------
src/target/etm.c | 18 +++++++++++-------
src/target/feroceon.c | 6 +++++-
src/target/target.c | 4 ++--
src/target/xscale.c | 32 +++++++++++++++++++++++++------
9 files changed, 121 insertions(+), 44 deletions(-)
(limited to 'src/target')
diff --git a/src/target/arm7_9_common.c b/src/target/arm7_9_common.c
index 39e46981..a814d2e9 100644
--- a/src/target/arm7_9_common.c
+++ b/src/target/arm7_9_common.c
@@ -217,14 +217,20 @@ int arm7_9_set_breakpoint(struct target_s *target, breakpoint_t *breakpoint)
{
u32 verify = 0xffffffff;
/* keep the original instruction in target endianness */
- target->type->read_memory(target, breakpoint->address, 4, 1, breakpoint->orig_instr);
+ if ((retval = target->type->read_memory(target, breakpoint->address, 4, 1, breakpoint->orig_instr)) != ERROR_OK)
+ {
+ return retval;
+ }
/* write the breakpoint instruction in target endianness (arm7_9->arm_bkpt is host endian) */
if ((retval = target_write_u32(target, breakpoint->address, arm7_9->arm_bkpt)) != ERROR_OK)
{
return retval;
}
- target->type->read_memory(target, breakpoint->address, 4, 1, (u8 *)&verify);
+ if ((retval = target->type->read_memory(target, breakpoint->address, 4, 1, (u8 *)&verify)) != ERROR_OK)
+ {
+ return retval;
+ }
if (verify != arm7_9->arm_bkpt)
{
LOG_ERROR("Unable to set 32 bit software breakpoint at address %08x - check that memory is read/writable", breakpoint->address);
@@ -235,14 +241,20 @@ int arm7_9_set_breakpoint(struct target_s *target, breakpoint_t *breakpoint)
{
u16 verify = 0xffff;
/* keep the original instruction in target endianness */
- target->type->read_memory(target, breakpoint->address, 2, 1, breakpoint->orig_instr);
+ if ((retval = target->type->read_memory(target, breakpoint->address, 2, 1, breakpoint->orig_instr)) != ERROR_OK)
+ {
+ return retval;
+ }
/* write the breakpoint instruction in target endianness (arm7_9->thumb_bkpt is host endian) */
if ((retval = target_write_u16(target, breakpoint->address, arm7_9->thumb_bkpt)) != ERROR_OK)
{
return retval;
}
- target->type->read_memory(target, breakpoint->address, 2, 1, (u8 *)&verify);
+ if ((retval = target->type->read_memory(target, breakpoint->address, 2, 1, (u8 *)&verify)) != ERROR_OK)
+ {
+ return retval;
+ }
if (verify != arm7_9->thumb_bkpt)
{
LOG_ERROR("Unable to set thumb software breakpoint at address %08x - check that memory is read/writable", breakpoint->address);
@@ -291,17 +303,29 @@ int arm7_9_unset_breakpoint(struct target_s *target, breakpoint_t *breakpoint)
{
u32 current_instr;
/* check that user program as not modified breakpoint instruction */
- target->type->read_memory(target, breakpoint->address, 4, 1, (u8*)¤t_instr);
+ if ((retval = target->type->read_memory(target, breakpoint->address, 4, 1, (u8*)¤t_instr)) != ERROR_OK)
+ {
+ return retval;
+ }
if (current_instr==arm7_9->arm_bkpt)
- target->type->write_memory(target, breakpoint->address, 4, 1, breakpoint->orig_instr);
+ if ((retval = target->type->write_memory(target, breakpoint->address, 4, 1, breakpoint->orig_instr)) != ERROR_OK)
+ {
+ return retval;
+ }
}
else
{
u16 current_instr;
/* check that user program as not modified breakpoint instruction */
- target->type->read_memory(target, breakpoint->address, 2, 1, (u8*)¤t_instr);
+ if ((retval = target->type->read_memory(target, breakpoint->address, 2, 1, (u8*)¤t_instr)) != ERROR_OK)
+ {
+ return retval;
+ }
if (current_instr==arm7_9->thumb_bkpt)
- target->type->write_memory(target, breakpoint->address, 2, 1, breakpoint->orig_instr);
+ if ((retval = target->type->write_memory(target, breakpoint->address, 2, 1, breakpoint->orig_instr)) != ERROR_OK)
+ {
+ return retval;
+ }
}
breakpoint->set = 0;
}
@@ -2306,6 +2330,7 @@ int armv4_5_run_algorithm_inner(struct target_s *target, int num_mem_params, mem
int arm7_9_bulk_write_memory(target_t *target, u32 address, u32 count, u8 *buffer)
{
+ int retval;
armv4_5_common_t *armv4_5 = target->arch_info;
arm7_9_common_t *arm7_9 = armv4_5->arch_info;
int i;
@@ -2332,7 +2357,10 @@ int arm7_9_bulk_write_memory(target_t *target, u32 address, u32 count, u8 *buffe
}
/* write DCC code to working area */
- target->type->write_memory(target, arm7_9->dcc_working_area->address, 4, 6, dcc_code_buf);
+ if ((retval = target->type->write_memory(target, arm7_9->dcc_working_area->address, 4, 6, dcc_code_buf)) != ERROR_OK)
+ {
+ return retval;
+ }
}
armv4_5_algorithm_t armv4_5_info;
@@ -2348,7 +2376,6 @@ int arm7_9_bulk_write_memory(target_t *target, u32 address, u32 count, u8 *buffe
//armv4_5_run_algorithm_inner(struct target_s *target, int num_mem_params, mem_param_t *mem_params,
// int num_reg_params, reg_param_t *reg_params, u32 entry_point, u32 exit_point, int timeout_ms, void *arch_info, int (*run_it)(struct target_s *target, u32 exit_point, int timeout_ms, void *arch_info))
- int retval;
dcc_count=count;
dcc_buffer=buffer;
retval = armv4_5_run_algorithm_inner(target, 0, NULL, 1, reg_params,
diff --git a/src/target/arm920t.c b/src/target/arm920t.c
index b45d0f61..5f499d64 100644
--- a/src/target/arm920t.c
+++ b/src/target/arm920t.c
@@ -233,6 +233,7 @@ int arm920t_write_cp15_physical(target_t *target, int reg_addr, u32 value)
int arm920t_execute_cp15(target_t *target, u32 cp15_opcode, u32 arm_opcode)
{
+ int retval;
armv4_5_common_t *armv4_5 = target->arch_info;
arm7_9_common_t *arm7_9 = armv4_5->arch_info;
arm_jtag_t *jtag_info = &arm7_9->jtag_info;
@@ -294,10 +295,10 @@ int arm920t_execute_cp15(target_t *target, u32 cp15_opcode, u32 arm_opcode)
arm9tdmi_clock_out(jtag_info, ARMV4_5_NOP, 0, NULL, 1);
arm7_9_execute_sys_speed(target);
- if (jtag_execute_queue() != ERROR_OK)
+ if ((retval = jtag_execute_queue()) != ERROR_OK)
{
LOG_ERROR("failed executing JTAG queue, exiting");
- exit(-1);
+ return retval;
}
return ERROR_OK;
diff --git a/src/target/cortex_m3.c b/src/target/cortex_m3.c
index 7b65c8bd..ee9ee257 100644
--- a/src/target/cortex_m3.c
+++ b/src/target/cortex_m3.c
@@ -810,6 +810,7 @@ void cortex_m3_enable_breakpoints(struct target_s *target)
int cortex_m3_set_breakpoint(struct target_s *target, breakpoint_t *breakpoint)
{
+ int retval;
int fp_num=0;
u32 hilo;
@@ -851,8 +852,14 @@ int cortex_m3_set_breakpoint(struct target_s *target, breakpoint_t *breakpoint)
{
u8 code[4];
buf_set_u32(code, 0, 32, ARMV7M_T_BKPT(0x11));
- target->type->read_memory(target, breakpoint->address & 0xFFFFFFFE, breakpoint->length, 1, breakpoint->orig_instr);
- target->type->write_memory(target, breakpoint->address & 0xFFFFFFFE, breakpoint->length, 1, code);
+ if((retval = target->type->read_memory(target, breakpoint->address & 0xFFFFFFFE, breakpoint->length, 1, breakpoint->orig_instr)) != ERROR_OK)
+ {
+ return retval;
+ }
+ if((retval = target->type->write_memory(target, breakpoint->address & 0xFFFFFFFE, breakpoint->length, 1, code)) != ERROR_OK)
+ {
+ return retval;
+ }
breakpoint->set = 0x11; /* Any nice value but 0 */
}
@@ -861,6 +868,7 @@ int cortex_m3_set_breakpoint(struct target_s *target, breakpoint_t *breakpoint)
int cortex_m3_unset_breakpoint(struct target_s *target, breakpoint_t *breakpoint)
{
+ int retval;
/* get pointers to arch-specific information */
armv7m_common_t *armv7m = target->arch_info;
cortex_m3_common_t *cortex_m3 = armv7m->arch_info;
@@ -889,11 +897,17 @@ int cortex_m3_unset_breakpoint(struct target_s *target, breakpoint_t *breakpoint
/* restore original instruction (kept in target endianness) */
if (breakpoint->length == 4)
{
- target->type->write_memory(target, breakpoint->address & 0xFFFFFFFE, 4, 1, breakpoint->orig_instr);
+ if((retval = target->type->write_memory(target, breakpoint->address & 0xFFFFFFFE, 4, 1, breakpoint->orig_instr)) != ERROR_OK)
+ {
+ return retval;
+ }
}
else
{
- target->type->write_memory(target, breakpoint->address & 0xFFFFFFFE, 2, 1, breakpoint->orig_instr);
+ if((retval = target->type->write_memory(target, breakpoint->address & 0xFFFFFFFE, 2, 1, breakpoint->orig_instr)) != ERROR_OK)
+ {
+ return retval;
+ }
}
}
breakpoint->set = 0;
diff --git a/src/target/embeddedice.c b/src/target/embeddedice.c
index 7da32fa8..19021cab 100644
--- a/src/target/embeddedice.c
+++ b/src/target/embeddedice.c
@@ -222,15 +222,17 @@ int embeddedice_setup(target_t *target)
int embeddedice_get_reg(reg_t *reg)
{
- if (embeddedice_read_reg(reg) != ERROR_OK)
+ int retval;
+ if ((retval = embeddedice_read_reg(reg)) != ERROR_OK)
{
LOG_ERROR("BUG: error scheduling EmbeddedICE register read");
- exit(-1);
+ return retval;
}
- if (jtag_execute_queue() != ERROR_OK)
+ if ((retval = jtag_execute_queue()) != ERROR_OK)
{
LOG_ERROR("register read failed");
+ return retval;
}
return ERROR_OK;
@@ -381,12 +383,13 @@ void embeddedice_set_reg(reg_t *reg, u32 value)
int embeddedice_set_reg_w_exec(reg_t *reg, u8 *buf)
{
+ int retval;
embeddedice_set_reg(reg, buf_get_u32(buf, 0, reg->size));
- if (jtag_execute_queue() != ERROR_OK)
+ if ((retval = jtag_execute_queue()) != ERROR_OK)
{
LOG_ERROR("register write failed");
- exit(-1);
+ return retval;
}
return ERROR_OK;
}
diff --git a/src/target/etb.c b/src/target/etb.c
index e81049d3..5aa85a1f 100644
--- a/src/target/etb.c
+++ b/src/target/etb.c
@@ -160,15 +160,17 @@ reg_cache_t* etb_build_reg_cache(etb_t *etb)
int etb_get_reg(reg_t *reg)
{
- if (etb_read_reg(reg) != ERROR_OK)
+ int retval;
+ if ((retval = etb_read_reg(reg)) != ERROR_OK)
{
LOG_ERROR("BUG: error scheduling etm register read");
- exit(-1);
+ return retval;
}
- if (jtag_execute_queue() != ERROR_OK)
+ if ((retval = jtag_execute_queue()) != ERROR_OK)
{
LOG_ERROR("register read failed");
+ return retval;
}
return ERROR_OK;
@@ -311,10 +313,11 @@ int etb_read_reg(reg_t *reg)
int etb_set_reg(reg_t *reg, u32 value)
{
- if (etb_write_reg(reg, value) != ERROR_OK)
+ int retval;
+ if ((retval = etb_write_reg(reg, value)) != ERROR_OK)
{
LOG_ERROR("BUG: error scheduling etm register write");
- exit(-1);
+ return retval;
}
buf_set_u32(reg->value, 0, reg->size, value);
@@ -326,12 +329,13 @@ int etb_set_reg(reg_t *reg, u32 value)
int etb_set_reg_w_exec(reg_t *reg, u8 *buf)
{
+ int retval;
etb_set_reg(reg, buf_get_u32(buf, 0, reg->size));
- if (jtag_execute_queue() != ERROR_OK)
+ if ((retval = jtag_execute_queue()) != ERROR_OK)
{
LOG_ERROR("register write failed");
- exit(-1);
+ return retval;
}
return ERROR_OK;
}
diff --git a/src/target/etm.c b/src/target/etm.c
index b07f1a75..c3750557 100644
--- a/src/target/etm.c
+++ b/src/target/etm.c
@@ -311,15 +311,17 @@ int etm_setup(target_t *target)
int etm_get_reg(reg_t *reg)
{
- if (etm_read_reg(reg) != ERROR_OK)
+ int retval;
+ if ((retval = etm_read_reg(reg)) != ERROR_OK)
{
LOG_ERROR("BUG: error scheduling etm register read");
- exit(-1);
+ return retval;
}
- if (jtag_execute_queue() != ERROR_OK)
+ if ((retval = jtag_execute_queue()) != ERROR_OK)
{
LOG_ERROR("register read failed");
+ return retval;
}
return ERROR_OK;
@@ -389,10 +391,11 @@ int etm_read_reg(reg_t *reg)
int etm_set_reg(reg_t *reg, u32 value)
{
- if (etm_write_reg(reg, value) != ERROR_OK)
+ int retval;
+ if ((retval = etm_write_reg(reg, value)) != ERROR_OK)
{
LOG_ERROR("BUG: error scheduling etm register write");
- exit(-1);
+ return retval;
}
buf_set_u32(reg->value, 0, reg->size, value);
@@ -404,12 +407,13 @@ int etm_set_reg(reg_t *reg, u32 value)
int etm_set_reg_w_exec(reg_t *reg, u8 *buf)
{
+ int retval;
etm_set_reg(reg, buf_get_u32(buf, 0, reg->size));
- if (jtag_execute_queue() != ERROR_OK)
+ if ((retval = jtag_execute_queue()) != ERROR_OK)
{
LOG_ERROR("register write failed");
- exit(-1);
+ return retval;
}
return ERROR_OK;
}
diff --git a/src/target/feroceon.c b/src/target/feroceon.c
index 7388307d..4baa20ca 100644
--- a/src/target/feroceon.c
+++ b/src/target/feroceon.c
@@ -523,6 +523,7 @@ int feroceon_examine_debug_reason(target_t *target)
int feroceon_bulk_write_memory(target_t *target, u32 address, u32 count, u8 *buffer)
{
+ int retval;
armv4_5_common_t *armv4_5 = target->arch_info;
arm7_9_common_t *arm7_9 = armv4_5->arch_info;
enum armv4_5_state core_state = armv4_5->core_state;
@@ -579,7 +580,10 @@ int feroceon_bulk_write_memory(target_t *target, u32 address, u32 count, u8 *buf
target_buffer_set_u32(target, dcc_code_buf + i*4, dcc_code[i]);
/* write DCC code to working area */
- target->type->write_memory(target, arm7_9->dcc_working_area->address, 4, dcc_size, dcc_code_buf);
+ if((retval = target->type->write_memory(target, arm7_9->dcc_working_area->address, 4, dcc_size, dcc_code_buf)) != ERROR_OK)
+ {
+ return retval;
+ }
}
/* backup clobbered processor state */
diff --git a/src/target/target.c b/src/target/target.c
index 5fde4f8f..5805d0c7 100644
--- a/src/target/target.c
+++ b/src/target/target.c
@@ -533,10 +533,10 @@ int target_init(struct command_context_s *cmd_ctx)
target->type->examine = default_examine;
}
- if (target->type->init_target(cmd_ctx, target) != ERROR_OK)
+ if ((retval = target->type->init_target(cmd_ctx, target)) != ERROR_OK)
{
LOG_ERROR("target '%s' init failed", target->type->name);
- exit(-1);
+ return retval;
}
/* Set up default functions if none are provided by target */
diff --git a/src/target/xscale.c b/src/target/xscale.c
index 20c7f646..9cf43891 100644
--- a/src/target/xscale.c
+++ b/src/target/xscale.c
@@ -2142,6 +2142,7 @@ void xscale_enable_mmu_caches(target_t *target, int mmu, int d_u_cache, int i_ca
int xscale_set_breakpoint(struct target_s *target, breakpoint_t *breakpoint)
{
+ int retval;
armv4_5_common_t *armv4_5 = target->arch_info;
xscale_common_t *xscale = armv4_5->arch_info;
@@ -2186,16 +2187,28 @@ int xscale_set_breakpoint(struct target_s *target, breakpoint_t *breakpoint)
if (breakpoint->length == 4)
{
/* keep the original instruction in target endianness */
- target->type->read_memory(target, breakpoint->address, 4, 1, breakpoint->orig_instr);
+ if((retval = target->type->read_memory(target, breakpoint->address, 4, 1, breakpoint->orig_instr)) != ERROR_OK)
+ {
+ return retval;
+ }
/* write the original instruction in target endianness (arm7_9->arm_bkpt is host endian) */
- target_write_u32(target, breakpoint->address, xscale->arm_bkpt);
+ if((retval = target_write_u32(target, breakpoint->address, xscale->arm_bkpt)) != ERROR_OK)
+ {
+ return retval;
+ }
}
else
{
/* keep the original instruction in target endianness */
- target->type->read_memory(target, breakpoint->address, 2, 1, breakpoint->orig_instr);
+ if((retval = target->type->read_memory(target, breakpoint->address, 2, 1, breakpoint->orig_instr)) != ERROR_OK)
+ {
+ return retval;
+ }
/* write the original instruction in target endianness (arm7_9->arm_bkpt is host endian) */
- target_write_u32(target, breakpoint->address, xscale->thumb_bkpt);
+ if((retval = target_write_u32(target, breakpoint->address, xscale->thumb_bkpt)) != ERROR_OK)
+ {
+ return retval;
+ }
}
breakpoint->set = 1;
}
@@ -2242,6 +2255,7 @@ int xscale_add_breakpoint(struct target_s *target, breakpoint_t *breakpoint)
int xscale_unset_breakpoint(struct target_s *target, breakpoint_t *breakpoint)
{
+ int retval;
armv4_5_common_t *armv4_5 = target->arch_info;
xscale_common_t *xscale = armv4_5->arch_info;
@@ -2276,11 +2290,17 @@ int xscale_unset_breakpoint(struct target_s *target, breakpoint_t *breakpoint)
/* restore original instruction (kept in target endianness) */
if (breakpoint->length == 4)
{
- target->type->write_memory(target, breakpoint->address, 4, 1, breakpoint->orig_instr);
+ if((retval = target->type->write_memory(target, breakpoint->address, 4, 1, breakpoint->orig_instr)) != ERROR_OK)
+ {
+ return retval;
+ }
}
else
{
- target->type->write_memory(target, breakpoint->address, 2, 1, breakpoint->orig_instr);
+ if((retval = target->type->write_memory(target, breakpoint->address, 2, 1, breakpoint->orig_instr)) != ERROR_OK)
+ {
+ return retval;
+ }
}
breakpoint->set = 0;
}
--
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