From dbbc9c41f7db210b0a4e226540a28e0a8a5019bf Mon Sep 17 00:00:00 2001 From: zwelch Date: Wed, 27 May 2009 06:49:24 +0000 Subject: Move TCL script files -- Step 2 of 2: - Move src/tcl to tcl/. - Update top Makefile.am to use new path name. git-svn-id: svn://svn.berlios.de/openocd/trunk@1919 b42882b7-edfa-0310-969c-e2dbd0fdcd60 --- src/tcl/board/unknown-board-atmel-at91sam9260.cfg | 82 ----------------------- 1 file changed, 82 deletions(-) delete mode 100644 src/tcl/board/unknown-board-atmel-at91sam9260.cfg (limited to 'src/tcl/board/unknown-board-atmel-at91sam9260.cfg') diff --git a/src/tcl/board/unknown-board-atmel-at91sam9260.cfg b/src/tcl/board/unknown-board-atmel-at91sam9260.cfg deleted file mode 100644 index 4d69f0fd..00000000 --- a/src/tcl/board/unknown-board-atmel-at91sam9260.cfg +++ /dev/null @@ -1,82 +0,0 @@ -# Thanks to Pieter Conradie for this script! -# Target: Atmel AT91SAM9260 -###################################### - -# We add to the minimal configuration. -source [find target/at91sam9260.cfg] - -###################### -# Target configuration -###################### - -$_TARGETNAME configure -event reset-init { - # at reset chip runs at 32khz - jtag_khz 8 - mww 0xfffffd08 0xa5000501 # RSTC_MR : enable user reset - mww 0xfffffd44 0x00008000 # WDT_MR : disable watchdog - - mww 0xfffffc20 0x00004001 # CKGR_MOR : enable the main oscillator - sleep 20 # wait 20 ms - mww 0xfffffc30 0x00000001 # PMC_MCKR : switch to main oscillator - sleep 10 # wait 10 ms - mww 0xfffffc28 0x2060bf09 # CKGR_PLLAR: Set PLLA Register for 198,656MHz - sleep 20 # wait 20 ms - mww 0xfffffc30 0x00000101 # PMC_MCKR : Select prescaler - sleep 10 # wait 10 ms - mww 0xfffffc30 0x00000102 # PMC_MCKR : Clock from PLLA is selected - sleep 10 # wait 10 ms - - # Now run at anything fast... ie: 10mhz! - jtag_khz 10000 # Increase JTAG Speed to 6 MHz - arm7_9 dcc_downloads enable # Enable faster DCC downloads - - mww 0xffffec00 0x01020102 # SMC_SETUP0 : Setup SMC for Intel NOR Flash JS28F128P30T85 128MBit - mww 0xffffec04 0x09070806 # SMC_PULSE0 - mww 0xffffec08 0x000d000b # SMC_CYCLE0 - mww 0xffffec0c 0x00001003 # SMC_MODE0 - - flash probe 0 # Identify flash bank 0 - - mww 0xfffff870 0xffff0000 # PIO_ASR : Select peripheral function for D15..D31 - mww 0xfffff804 0xffff0000 # PIO_PDR : Disable PIO function for D15..D31 - - mww 0xffffef1c 0x2 # EBI_CSA : Assign EBI Chip Select 1 to SDRAM - - #mww 0xffffea08 0x85227259 # SDRAMC_CR : Configure SDRAM (2 x Samsung K4S561632H-UC75 : 4M x 16Bit x 4 Banks) - mww 0xffffea08 0x85227254 # SDRAMC_CR : Configure SDRAM (2 x Samsung K4S641632H-UC75 : 1M x 16Bit x 4 Banks) - - mww 0xffffea00 0x1 # SDRAMC_MR : issue a NOP command - mww 0x20000000 0 - mww 0xffffea00 0x2 # SDRAMC_MR : issue an 'All Banks Precharge' command - mww 0x20000000 0 - mww 0xffffea00 0x4 # SDRAMC_MR : issue 8 x 'Auto-Refresh' Command - mww 0x20000000 0 - mww 0xffffea00 0x4 - mww 0x20000000 0 - mww 0xffffea00 0x4 - mww 0x20000000 0 - mww 0xffffea00 0x4 - mww 0x20000000 0 - mww 0xffffea00 0x4 - mww 0x20000000 0 - mww 0xffffea00 0x4 - mww 0x20000000 0 - mww 0xffffea00 0x4 - mww 0x20000000 0 - mww 0xffffea00 0x4 - mww 0x20000000 0 - mww 0xffffea00 0x3 # SDRAMC_MR : issue a 'Load Mode Register' command - mww 0x20000000 0 - mww 0xffffea00 0x0 # SDRAMC_MR : normal mode - mww 0x20000000 0 - mww 0xffffea04 0x5d2 # SDRAMC_TR : Set refresh timer count to 15us -} - - -##################### -# Flash configuration -##################### - -#flash bank cfi -flash bank cfi 0x10000000 0x01000000 2 2 0 - -- cgit v1.2.3