From 52377759a2c5c6a291c9bbd110a7f9efca4e1e46 Mon Sep 17 00:00:00 2001 From: oharboe Date: Fri, 9 May 2008 18:38:51 +0000 Subject: Michael Fischer spotted a problem in the reset routines for srst_pulls_trst. It is a bit of a mystery why this was only visible w/LPC2148. Embedded ICE registers are now set up after SRST pulls TRST. git-svn-id: svn://svn.berlios.de/openocd/trunk@650 b42882b7-edfa-0310-969c-e2dbd0fdcd60 --- src/target/target.c | 17 +++++++++++++++++ 1 file changed, 17 insertions(+) (limited to 'src') diff --git a/src/target/target.c b/src/target/target.c index 3e9cce5b..d5e4ea56 100644 --- a/src/target/target.c +++ b/src/target/target.c @@ -298,6 +298,16 @@ int target_process_reset(struct command_context_s *cmd_ctx) if ((retval = jtag_init_reset(cmd_ctx)) != ERROR_OK) return retval; + /* First time this is executed after launching OpenOCD, it will read out + * the type of CPU, etc. and init Embedded ICE registers in host + * memory. + * + * It will also set up ICE registers in the target. + * + * However, if we assert TRST later, we need to set up the registers again. + * + * For the "reset halt/init" case we must only set up the registers here. + */ if ((retval = target_examine(cmd_ctx)) != ERROR_OK) return retval; @@ -384,6 +394,13 @@ int target_process_reset(struct command_context_s *cmd_ctx) target = target->next; } + if (jtag_reset_config & RESET_SRST_PULLS_TRST) + { + /* If TRST was asserted we need to set up registers again */ + if ((retval = target_examine(cmd_ctx)) != ERROR_OK) + return retval; + } + if ((retval = jtag_execute_queue()) != ERROR_OK) { LOG_WARNING("JTAG communication failed while deasserting reset."); -- cgit v1.2.3