From 8fc9bcb7f57306e822deaf2e0facd51b96dc4fb2 Mon Sep 17 00:00:00 2001
From: oharboe <oharboe@b42882b7-edfa-0310-969c-e2dbd0fdcd60>
Date: Thu, 15 Jan 2009 13:09:20 +0000
Subject: Alan Carvalho de Assis <acassis@gmail.com> imx31pdk.cfg reset init
 event

git-svn-id: svn://svn.berlios.de/openocd/trunk@1322 b42882b7-edfa-0310-969c-e2dbd0fdcd60
---
 src/target/board/imx31pdk.cfg | 101 ++++++++++++++++++++++++++++++++++++++++++
 1 file changed, 101 insertions(+)
 create mode 100644 src/target/board/imx31pdk.cfg

(limited to 'src')

diff --git a/src/target/board/imx31pdk.cfg b/src/target/board/imx31pdk.cfg
new file mode 100644
index 00000000..c6c423ce
--- /dev/null
+++ b/src/target/board/imx31pdk.cfg
@@ -0,0 +1,101 @@
+# The IMX31PDK eval board has a single IMX31 chip
+source [find target/imx31.cfg]
+$_TARGETNAME configure -event gdb-attach { reset init }
+$_TARGETNAME configure -event reset-init { imx31pdk_init }
+
+proc imx31pdk_init { } {
+	# This setup puts RAM at 0x80000000
+
+	# reset the board correctly
+	reset run
+	reset halt
+
+	# ========================================
+	# Init CCM
+	# ========================================
+	mww 0x53FC0000 0x040
+	mww 0x53F80000 0x074B0B7D
+
+	sleep 100
+
+	# ========================================
+	# 399MHz - 26MHz input, PD=1,MFI=7, MFN=27, MFD=40
+	# ========================================
+	mww 0x53F80004 0xFF871D50
+	mww 0x53F80010 0x00271C1B
+
+	# ========================================
+	# Configure CPLD on CS5 
+	# ========================================
+	mww 0xb8002050 0x0000DCF6
+	mww 0xb8002054 0x444A4541
+	mww 0xb8002058 0x44443302
+
+	# ========================================
+	# SDCLK
+	# ========================================
+	mww 0x43FAC26C 0
+
+	# ========================================
+	# CAS
+	# ========================================
+	mww 0x43FAC270 0
+
+	# ========================================
+	# RAS
+	# ========================================
+	mww 0x43FAC274 0
+
+	# ========================================
+	# CS2 (CSD0)
+	# ========================================
+	mww 0x43FAC27C 0x1000
+
+	# ========================================
+	# DQM3
+	# ========================================
+	mww 0x43FAC284 0
+
+	# ========================================
+	# DQM2, DQM1, DQM0, SD31-SD0, A25-A0, MA10 (0x288..0x2DC)
+	# ========================================
+	mww 0x43FAC288 0
+	mww 0x43FAC28C 0
+	mww 0x43FAC290 0
+	mww 0x43FAC294 0
+	mww 0x43FAC298 0
+	mww 0x43FAC29C 0
+	mww 0x43FAC2A0 0
+	mww 0x43FAC2A4 0
+	mww 0x43FAC2A8 0
+	mww 0x43FAC2AC 0
+	mww 0x43FAC2B0 0
+	mww 0x43FAC2B4 0
+	mww 0x43FAC2B8 0
+	mww 0x43FAC2BC 0
+	mww 0x43FAC2C0 0
+	mww 0x43FAC2C4 0
+	mww 0x43FAC2C8 0
+	mww 0x43FAC2CC 0
+	mww 0x43FAC2D0 0
+	mww 0x43FAC2D4 0
+	mww 0x43FAC2D8 0
+	mww 0x43FAC2DC 0
+
+	# ========================================
+	# Initialization script for 32 bit DDR on MX31 PDK
+	# ========================================
+	mww 0xB8001010 0x00000004
+	mww 0xB8001004 0x006ac73a
+	mww 0xB8001000 0x92100000
+	mww 0x80000f00 0x12344321
+	mww 0xB8001000 0xa2100000
+	mww 0x80000000 0x12344321
+	mww 0x80000000 0x12344321
+	mww 0xB8001000 0xb2100000
+	mwb 0x80000033 0xda
+	mwb 0x81000000 0xff
+	mww 0xB8001000 0x82226080
+	mww 0x80000000 0xDEADBEEF
+	mww 0xB8001010 0x0000000c
+}
-- 
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