From ad3a24f9446c264c0e2de754494d0d3e69c8fc51 Mon Sep 17 00:00:00 2001 From: oharboe Date: Fri, 24 Jul 2009 16:48:12 +0000 Subject: David Brownell Bugfix some instruction decoding ... I've crafted asm files with testcases covering several new encodings in these sections of the ARMv7-M arch manual: A5.3.12 Data processing (register) A5.3.13 Miscellaneous operations A5.3.14 Multiply, and multiply accumulate A5.3.15 Long multiply, long multiply accumulate, and divide The issues were mostly in '12 and '13; some new related 16-bit opcodes had issues too. git-svn-id: svn://svn.berlios.de/openocd/trunk@2563 b42882b7-edfa-0310-969c-e2dbd0fdcd60 --- src/target/arm_disassembler.c | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) (limited to 'src') diff --git a/src/target/arm_disassembler.c b/src/target/arm_disassembler.c index 2af07c4e..149d1976 100644 --- a/src/target/arm_disassembler.c +++ b/src/target/arm_disassembler.c @@ -2098,7 +2098,7 @@ static int evaluate_byterev_thumb(uint16_t opcode, uint32_t address, char *suffix; /* added in ARMv6 */ - switch (opcode & 0x00c0) { + switch ((opcode >> 6) & 3) { case 0: suffix = ""; break; @@ -3201,7 +3201,7 @@ static int t2ev_data_reg(uint32_t opcode, uint32_t address, (int) (opcode >> 0) & 0xf); } else if (opcode & (1 << 7)) { - switch ((opcode >> 24) & 0xf) { + switch ((opcode >> 20) & 0xf) { case 0: case 1: case 4: @@ -3221,7 +3221,7 @@ static int t2ev_data_reg(uint32_t opcode, uint32_t address, (opcode & (1 << 24)) ? 'U' : 'S', (opcode & (1 << 26)) ? 'B' : 'H', (int) (opcode >> 8) & 0xf, - (int) (opcode >> 16) & 0xf, + (int) (opcode >> 0) & 0xf, suffix); break; case 8: @@ -3230,7 +3230,7 @@ static int t2ev_data_reg(uint32_t opcode, uint32_t address, case 0xb: if (opcode & (1 << 6)) return ERROR_INVALID_ARGUMENTS; - if (~opcode & (0xff << 12)) + if (((opcode >> 12) & 0xf) != 0xf) return ERROR_INVALID_ARGUMENTS; if (!(opcode & (1 << 20))) return ERROR_INVALID_ARGUMENTS; -- cgit v1.2.3