From b25574e16aadb92f00882ef743179ab8b6c91502 Mon Sep 17 00:00:00 2001
From: oharboe <oharboe@b42882b7-edfa-0310-969c-e2dbd0fdcd60>
Date: Mon, 5 Jan 2009 09:25:23 +0000
Subject: Andi <opencode@gmx.net> basic support for the MIPS based SMP8634 SoC.
git-svn-id: svn://svn.berlios.de/openocd/trunk@1299 b42882b7-edfa-0310-969c-e2dbd0fdcd60
---
src/target/board/x300t.cfg | 17 +++++++++++++++++
src/target/interface/parport_dlc5.cfg | 7 +++++++
src/target/target/smp8634.cfg | 32 ++++++++++++++++++++++++++++++++
3 files changed, 56 insertions(+)
create mode 100644 src/target/board/x300t.cfg
create mode 100644 src/target/interface/parport_dlc5.cfg
create mode 100644 src/target/target/smp8634.cfg
(limited to 'src')
diff --git a/src/target/board/x300t.cfg b/src/target/board/x300t.cfg
new file mode 100644
index 00000000..200bb58b
--- /dev/null
+++ b/src/target/board/x300t.cfg
@@ -0,0 +1,17 @@
+# This is for the T-Home X300T / X301T IPTV box,
+# which are based on IPTV reference designs from Kiss/Cisco KMM-32**
+#
+# It has Sigma Designs SMP8634 chip.
+source [find target/smp8634.cfg]
+
+$_TARGETNAME configure -event reset-init { x300t_init }
+
+# 1MB CFI capable flash
+# flash bank <driver> <base> <size> <chip_width> <bus_width>
+flash bank cfi 0xac000000 0x100000 2 2 0
+
+proc x300t_init { } {
+ # Setup SDRAM config and flash mapping
+ # map flash to CPU address space REG_BASE_cpu_block+CPU_remap4
+ mww 0x6f010 0x48000000
+}
diff --git a/src/target/interface/parport_dlc5.cfg b/src/target/interface/parport_dlc5.cfg
new file mode 100644
index 00000000..346aedec
--- /dev/null
+++ b/src/target/interface/parport_dlc5.cfg
@@ -0,0 +1,7 @@
+telnet_port 4444
+gdb_port 2001
+
+interface parport
+parport_port /dev/parport0
+parport_cable dlc5
+jtag_speed 0
diff --git a/src/target/target/smp8634.cfg b/src/target/target/smp8634.cfg
new file mode 100644
index 00000000..2470a5da
--- /dev/null
+++ b/src/target/target/smp8634.cfg
@@ -0,0 +1,32 @@
+# script for Sigma Designs SMP8634 (eventually even SMP8635)
+
+if { [info exists CHIPNAME] } {
+ set _CHIPNAME $CHIPNAME
+} else {
+ set _CHIPNAME smp8634
+}
+
+if { [info exists ENDIAN] } {
+ set _ENDIAN $ENDIAN
+} else {
+ set _ENDIAN little
+}
+
+if { [info exists CPUTAPID ] } {
+ set _CPUTAPID $CPUTAPID
+} else {
+ # force an error till we get a good number
+ set _CPUTAPID 0x08630001
+}
+
+jtag_nsrst_delay 100
+jtag_ntrst_delay 100
+
+reset_config trst_and_srst separate
+
+# jtag scan chain
+# format L IRC IRCM IDCODE (Length, IR Capture, IR Capture Mask, IDCODE)
+jtag newtap $_CHIPNAME cpu -irlen 5 -ircapture 0x1 -irmask 0x1
+
+set _TARGETNAME [format "%s.cpu" $_CHIPNAME]
+target create $_TARGETNAME mips_m4k -endian $_ENDIAN -variant
--
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