From d4e4d65d284fa0347e601f30aebf4291074d9888 Mon Sep 17 00:00:00 2001 From: mlu Date: Mon, 14 Sep 2009 22:36:27 +0000 Subject: Cache invalidation when writing to memory git-svn-id: svn://svn.berlios.de/openocd/trunk@2708 b42882b7-edfa-0310-969c-e2dbd0fdcd60 --- src/target/cortex_a8.c | 18 ++++++++++++++++++ 1 file changed, 18 insertions(+) (limited to 'src') diff --git a/src/target/cortex_a8.c b/src/target/cortex_a8.c index 7a705153..e73994e9 100644 --- a/src/target/cortex_a8.c +++ b/src/target/cortex_a8.c @@ -1253,6 +1253,24 @@ int cortex_a8_write_memory(struct target_s *target, uint32_t address, exit(-1); } + /* The Cache handling will NOT work with MMU active, the wrong addresses will be invalidated */ + /* invalidate I-Cache */ + if (armv7a->armv4_5_mmu.armv4_5_cache.i_cache_enabled) + { + /* Invalidate ICache single entry with MVA, repeat this for all cache + lines in the address range, Cortex-A8 has fixed 64 byte line length */ + /* Invalidate Cache single entry with MVA to PoU */ + for (uint32_t cacheline=address; cachelinewrite_cp15(target, 0, 1, 7, 5, cacheline); /* I-Cache to PoU */ + } + /* invalidate D-Cache */ + if (armv7a->armv4_5_mmu.armv4_5_cache.d_u_cache_enabled) + { + /* Invalidate Cache single entry with MVA to PoC */ + for (uint32_t cacheline=address; cachelinewrite_cp15(target, 0, 1, 7, 6, cacheline); /* U/D cache to PoC */ + } + return retval; } -- cgit v1.2.3