From 6839618062f07a12bd969da8dc54546f96938b67 Mon Sep 17 00:00:00 2001
From: Michael Trensch <MTrensch@googlemail.com>
Date: Thu, 16 Dec 2010 15:33:16 +0100
Subject: Add support for Hilscher netX controllers

---
 tcl/board/hilscher_nxhx10.cfg | 82 +++++++++++++++++++++++++++++++++++++++++++
 1 file changed, 82 insertions(+)
 create mode 100644 tcl/board/hilscher_nxhx10.cfg

(limited to 'tcl/board/hilscher_nxhx10.cfg')

diff --git a/tcl/board/hilscher_nxhx10.cfg b/tcl/board/hilscher_nxhx10.cfg
new file mode 100644
index 00000000..4a6b972a
--- /dev/null
+++ b/tcl/board/hilscher_nxhx10.cfg
@@ -0,0 +1,82 @@
+################################################################################
+# Author: Michael Trensch (MTrensch@googlemail.com)
+################################################################################
+
+source [find target/hilscher_netx10.cfg]
+
+# Usually it is not needed to set srst_pulls_trst
+# but sometimes it does not work without it. If you encounter
+# problems try to line below
+# reset_config trst_and_srst srst_pulls_trst
+reset_config trst_and_srst
+jtag_nsrst_delay 500
+jtag_ntrst_delay 500
+
+$_TARGETNAME configure -work-area-virt 0x08000000 -work-area-phys 0x08000000 -work-area-size 0x4000 -work-area-backup 1
+
+# Par. Flash can only be accessed if DIP switch on the board is set in proper
+# position and init_sdrambus was called. Don't call these functions if the DIP
+# switch is in invalid position, as some outputs may collide. This is why this
+# function is not called automatically
+proc flash_init { } {
+  puts "Configuring SRAM nCS0 for 90ns Par. Flash (x16)"
+  mww 0x101C0100 0x01010008
+
+  flash probe 0
+}
+
+proc mread32 {addr} {
+  set value(0) 0
+  mem2array value 32 $addr 1
+  return $value(0)
+}
+
+proc init_clocks { } {
+  puts "Enabling all clocks "
+  set accesskey [mread32 0x101c0070]
+  mww  0x101c0070 [expr $accesskey]
+
+  mww  0x101c0028 0x00007511
+}
+
+proc init_sdrambus { } {
+  puts "Initializing external SDRAM Bus 16 Bit "
+  set accesskey [mread32 0x101c0070]
+  mww  0x101c0070 [expr $accesskey]
+  mww  0x101c0C40 0x00000050
+
+  puts "Configuring SDRAM controller for K4S561632E (32MB) "
+  mww 0x101C0140 0
+  sleep 100
+  #mww 0x101C0144 0x00a13262
+  mww 0x101C0144 0x00a13251
+  mww 0x101C0148 0x00000033
+  mww 0x101C0140 0x030d0121
+}
+
+$_TARGETNAME configure -event reset-init {
+  halt
+  wait_halt 1000
+
+  arm7_9 fast_memory_access enable
+  arm7_9 dcc_downloads enable
+
+  init_clocks
+#  init_sdrambus
+
+  puts ""
+  puts "-------------------------------------------------"
+  puts "Call 'init_clocks' to enable all clocks"
+  puts "Call 'init_sdrambus' to enable external SDRAM bus"
+  puts "-------------------------------------------------"
+}
+
+#####################
+# Flash configuration
+#####################
+
+#flash bank <name> <driver> <base> <size> <chip width> <bus width> <target#>
+#flash bank parflash cfi 0xC0000000 0x01000000 2 2 $_TARGETNAME
+
+init
+reset init
\ No newline at end of file
-- 
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